HD74HCT564, HD74HCT574 Octal D-type Flip-Flops (with 3-state outputs) REJ03D0670–0200 (Previous ADE-205-560) Rev.2.00 Mar 30, 2006 Description These devices are positive edge triggered flip-flops. The difference between HD74HCT564 and HD74HCT574 is only that the former has inverting outputs and the latter has noninvertering outputs. Data at the D inputs, meeting the set-up and hold time requirements, are transferred to the Q or Q outputs on positive going transitions of the clock (CK) input. when a high logic level is applied to the output control (OC) input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. Features • • • • • • • LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility High Speed Operation: tpd (D to Q, Q) = 15 ns typ (CL = 50 pF) High Output Current: Fanout of 15 LSTTL Loads Wide Operating Voltage: VCC = 4.5 to 5.5 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) Ordering Information Part Name Package Type Package Code (Previous Code) HD74HCT564P PRDP0020AC-B DILP-20 pin P (DP-20NEV) HD74HCT574P HD74HCT564FPEL PRSP0020DD-B SOP-20 pin (JEITA) FP (FP-20DAV) HD74HCT574FPEL HD74HCT564RPEL PRSP0020DC-A SOP-20 pin (JEDEC) RP (FP-20DBV) HD74HCT574RPEL Note: Please consult the sales office for the above package availability. Package Abbreviation Taping Abbreviation (Quantity) — EL (2,000 pcs/reel) EL (1,000 pcs/reel) Function Table Inputs Clock Outputs Output Control Data HD74HCT564 HD74HCT574 L H L H L L H L L L X Q0 Q0 H X X Z Z Q0 : level of Q before the indicated Steady-sate input conditions were established. Q0 : complement of Q0 or level of Q before the indicated Steady-state input Conditions were established. Rev.2.00 Mar 30, 2006 page 1 of 8 HD74HCT564, HD74HCT574 Pin Arrangement HD74HC564 Output Control 1 20 VCC OE 1D 2 2D 3 D OE D OE D OE D OE OE OE OE 15 5Q 14 6Q D D Q Q 7D 8 8D 9 17 3Q 16 4Q D D Q Q 5D 6 6D 7 19 1Q 18 2Q Q 3D 4 4D 5 Q Q 13 7Q 12 8Q Q 11 Clock GND 10 (Top view) HD74HC574 Output Control 1 20 VCC OE 1D 2 2D 3 D OE D OE D OE D OE D OE D Q 13 7Q 12 8Q Q 11 Clock GND 10 (Top view) Rev.2.00 Mar 30, 2006 page 2 of 8 15 5Q 14 6Q Q 7D 8 8D 9 Q OE D 17 3Q 16 4Q Q 5D 6 6D 7 Q OE D 19 1Q 18 2Q Q 3D 4 4D 5 Q HD74HCT564, HD74HCT574 Logic Diagram HD74HC564 1D D C Q C 1Q 2D D C Q C 2Q 3D D C Q C 3Q 4D D C Q C 4Q 5D D C Q C 5Q 6D D C Q C 6Q 7D D C Q C 7Q 8D D C Q C 8Q 1D D C Q C 1Q 2D D C Q C 2Q 3D D C Q C 3Q 4D D C Q C 4Q 5D D C Q C 5Q 6D D C Q C 6Q 7D D C Q C 7Q 8D D C Q C 8Q CLK OC HD74HC574 CLK OC Rev.2.00 Mar 30, 2006 page 3 of 8 HD74HCT564, HD74HCT574 Absolute Maximum Ratings Item Supply voltage range Input / Output voltage Input / Output diode current Output current VCC, GND current Power dissipation Storage temperature Symbol VCC VIN, VOUT IIK, IOK IO ICC or IGND PT Tstg Ratings –0.5 to 7.0 –0.5 to VCC +0.5 ±20 ±35 ±75 500 –65 to +150 Unit V V mA mA mA mW °C Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. Recommended Operating Conditions Item Supply voltage Input / Output voltage Operating temperature Input rise / fall time*1 Symbol VCC VIN, VOUT Ta tr, tf Ratings 4.5 to 5.5 0 to VCC –40 to 85 0 to 500 Unit V V °C ns Conditions VCC = 4.5 V Notes: 1. This item guarantees maximum limit when one input switches. Waveform: Refer to test circuit of switching characteristics. Electrical Characteristics Item Input voltage Output voltage Symbol VCC (V) VIH VIL VOH VOL Off-state output current Input current Quiescent current IOZ Iin ICC Min 4.5 to 5.5 2.0 4.5 to 5.5 — 4.5 4.4 4.5 4.18 4.5 — 4.5 — 5.5 — 5.5 5.5 Rev.2.00 Mar 30, 2006 page 4 of 8 — — Ta = 25°C Typ Max Ta = –40 to+85°C Min Max Unit — — — — — — — — 0.8 — — 0.1 0.26 ±0.5 2.0 — 4.4 4.13 — — — — 0.8 — — 0.1 0.33 ±5.0 V V V µA — — ±0.1 4.0 — — ±1.0 40 µA µA V Test Conditions Vin = VIH or VIL IOH = –20 µA IOH = –6 mA Vin = VIH or VIL IOL = 20 µA IOL = 6 mA Vin = VIH or VIL, Vout = VCC or GND Vin = VCC or GND Vin = VCC or GND, Iout = 0 µA HD74HCT564, HD74HCT574 Switching Characteristics (CL = 50 pF, Input tr = tf = 6 ns) Item Symbol VCC (V) Maximum clock frequency Propagation delay time Output enable time Output disable time Setup time Hold time Pulse width Output rise/fall time Input capacitance fmax 4.5 Min — tPLH tPHL tZL tZH tLZ tHZ tsu th tw tTLH tTHL Cin 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 — — — — — — — 20 5 16 — — — Ta = 25°C Typ Max — 30 14 15 16 16 15 18 3 –2 7 4 4 5 31 31 30 30 30 30 — — — 12 12 10 Ta = –40 to +85°C Min Max — 24 — — — — — — 25 5 20 — — — 39 39 38 38 38 38 — — — 15 15 10 Unit Test Conditions ns ns ns ns ns ns ns ns pF Test Circuit VCC VCC Input Pulse Generator Zout = 50 Ω Input Pulse Generator Zout = 50 Ω See Function Table Output OC 1Q to 8Q or 1Q to 8Q S1 OPEN GND CL = 50 pF VCC 1D to 8D Clock Note : 1. CL includes probe and jig capacitance. Rev.2.00 Mar 30, 2006 page 5 of 8 1 kΩ TEST t PLH / t PHL S1 OPEN t ZH/ t HZ t ZL / t LZ GND VCC HD74HCT564, HD74HCT574 Waveforms • Waveform –1 tr tf VCC 90 % 90 % 1.3 V Input Clock 10 % tr 90 % Input Data 1.3 V 10 % tf 0V VCC 90 % 10 % 10 % 0V tPHL tPLH Output Q VOH 1.3 V 1.3 V VOL Output Q • Waveform –2 Input OC tf tr 90 % 1.3 V 10 % VCC 90 % 1.3 V 10 % tLZ tZL 0V VOH 1.3 V Waveform - A tZH Waveform - B 10 % VOL tHZ 50 % 90 % VOH VOL Notes : 1. Input waveform : PRR ≤ 1 MHz, duty cycle 50%, tr ≤ 6 ns, tf ≤ 6 ns 2. Waveform– A is for an output with internal conditions such that the output is low except when disabled by the output control. 3. Waveform– B is for an output with internal conditions such that the output is high except when disabled by the output control. 4. The output are measured one at a time with one transition per measurement. Rev.2.00 Mar 30, 2006 page 6 of 8 HD74HCT564, HD74HCT574 Package Dimensions JEITA Package Code P-DIP20-6.3x24.5-2.54 RENESAS Code PRDP0020AC-B Previous Code DP-20NEV MASS[Typ.] 1.26g D 11 E 20 1 10 b3 0.89 A1 A Z Reference Symbol L e1 D E A A1 bp b3 c θ e Z L θ bp e c e1 ( Ni/Pd/Au plating ) JEITA Package Code P-SOP20-7.5x12.8-1.27 RENESAS Code PRSP0020DC-A *1 Previous Code FP-20DBV Dimension in Millimeters Min Nom Max 7.62 24.50 25.40 6.30 7.00 5.08 0.51 0.40 0.48 0.56 1.30 0.19 0.25 0.31 0° 15° 2.29 2.54 2.79 1.27 2.54 MASS[Typ.] 0.52g D F 20 NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" @ DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT @ INCLUDE TRIM OFFSET. 11 HE c *2 E bp Index mark Terminal cross section ( Ni/Pd/Au plating ) 1 e *3 bp x M L1 A Z Reference Dimension in Millimeters Symbol 10 A1 θ L y Detail F Rev.2.00 Mar 30, 2006 page 7 of 8 D E A2 A1 A bp b1 c c1 θ HE e x y Z L L1 Min Nom Max 12.80 13.2 7.50 0.10 0.20 0.30 2.65 0.34 0.40 0.46 0.20 0.25 0.30 0° 8° 10.00 10.40 10.65 1.27 0.12 0.15 0.935 0.40 0.70 1.27 1.45 HD74HCT564, HD74HCT574 JEITA Package Code P-SOP20-5.5x12.6-1.27 RENESAS Code PRSP0020DD-B *1 Previous Code FP-20DAV MASS[Typ.] 0.31g D NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. F 20 11 c HE *2 E bp Index mark Terminal cross section ( Ni/Pd/Au plating ) 1 Z 10 e *3 bp x Reference Dimension in Millimeters Symbol M A L1 A1 θ y L Detail F Rev.2.00 Mar 30, 2006 page 8 of 8 D E A2 A1 A bp b1 c c1 θ HE e x y Z L L1 Min Nom Max 12.60 13.0 5.50 0.00 0.10 0.20 2.20 0.34 0.40 0.46 0.15 0.20 0.25 0° 8° 7.50 7.80 8.00 1.27 0.12 0.15 0.80 0.50 0.70 0.90 1.15 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. 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