Renesas HD74LVC540ATELL Octal buffers / line drivers with 3-state output Datasheet

HD74LVC540A
Octal Buffers / Line Drivers with 3-state Outputs
REJ03D0358–0400Z
(Previous ADE-205-114B (Z))
Rev.4.00
Jul. 28, 2004
Description
The HD74LVC540A has eight inverter drivers with three state outputs in a 20 pin package. When G1 and G2 is low
level, this drivers set up output is enable. Low voltage and high-speed operation is suitable at the battery drive product
(note type personal computer) and low power consumption extends the life of a battery for long time operation.
Features
•
•
•
•
•
•
•
VCC = 2.0 V to 5.5 V
All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
All outputs VOUT (Max.) = 5.5 V (@VCC = 0 V or output off state)
Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)
High output current ±24 mA (@VCC = 3.0 V to 5.5 V)
Ordering Information
Part Name
Package Type
Package Code
Package
Abbreviation
Taping Abbreviation
(Quantity)
HD74LVC540AFPEL
HD74LVC540ATELL
SOP–20 pin (JEITA)
TSSOP–20 pin
FP–20DAV
TTP–20DAV
FP
T
EL (2,000 pcs/reel)
ELL (2,000 pcs/reel)
Note: Please consult the sales office for the above package availability.
Function Table
Inputs
G1
G2
A
Output Y
L
L
H
X
L
L
X
H
L
H
X
X
H
L
Z
Z
H:
L:
X:
Z:
High level
Low level
Immaterial
High impedance
Rev.4.00 Jul. 28, 2004 page 1 of 6
HD74LVC540A
Pin Arrangement
20 VCC
G1 1
A1
2
19 G2
A2
3
18 Y1
A3 4
17 Y2
A4
5
16 Y3
A5
6
15 Y4
A6
7
14 Y5
A7 8
13 Y6
A8 9
12 Y7
GND 10
11 Y8
(Top view)
Absolute Maximum Ratings
Item
Symbol
Ratings
Unit
Supply voltage
Input diode current
Input voltage
Output diode current
VCC
IIK
VI
IOK
V
mA
V
mA
Output voltage
VO
Output current
VCC, GND current / pin
Storage temperature
IO
ICC or IGND
Tstg
–0.5 to 6.0
–50
–0.5 to 6.0
–50
50
–0.5 to VCC +0.5
–0.5 to 6.0
±50
100
–65 to +150
V
Conditions
VI = –0.5 V
VO = –0.5 V
VO = VCC+0.5 V
Output "H" or "L"
Output "Z" or VCC:OFF
mA
mA
°C
Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of
which may be realized at the same time.
Rev.4.00 Jul. 28, 2004 page 2 of 6
HD74LVC540A
Recommended Operating Conditions
Item
Symbol
Ratings
Unit
Conditions
Supply voltage
VCC
1.5 to 5.5
V
Data hold
V
V
At operation
G1, G2, A
Output "H" or "L"
Output "Z" or VCC:OFF
Input / output voltage
VI
VO
Operating temperature
Output current
Ta
IOH
IOL
Input rise / fall time *1
tr, tf
2.0 to 5.5
0 to 5.5
0 to VCC
0 to 5.5
–40 to 85
–12
–24*2
12
24*2
10
°C
mA
mA
VCC = 2.7 V
VCC = 3.0 V to 5.5 V
VCC = 2.7 V
VCC = 3.0 V to 5.5 V
ns/V
Notes: 1. This item guarantees maximum limit when one input switches.
Waveform: Refer to test circuit of switching characteristics.
2. Duty cycle ≤ 50%
Electrical Characteristics
Ta = –40 to 85°C
Item
Symbol
VCC (V)
Min
Max
Unit
Input voltage
VIH
2.7 to 3.6
4.5 to 5.5
2.7 to 3.6
4.5 to 5.5
2.7 to 5.5
2.7
3.0
3.0
4.5
2.7 to 5.5
2.7
3.0
4.5
0 to 5.5
2.7 to 5.5
2.0
VCC×0.7
—
—
VCC–0.2
2.2
2.4
2.2
3.8
—
—
—
—
—
—
—
—
0.8
VCC×0.3
—
—
—
—
—
0.2
0.4
0.55
0.55
±5.0
±5.0
V
0
2.7 to 3.6
2.7 to 5.5
3.0 to 3.6
—
—
—
—
20
±10
10
500
µA
µA
VIL
Output voltage
VOH
VOL
Input current
Off state output current
IIN
IOZ
Output leak current
Quiescent supply current
IOFF
ICC
∆ICC
Rev.4.00 Jul. 28, 2004 page 3 of 6
Test Conditions
V
V
IOH = –100 µA
IOH = –12 mA
IOH = –24 mA
V
IOL = 100 µA
IOL = 12 mA
IOL = 24 mA
µA
µA
VIN = 5.5 V or GND
VIN = VCC, GND
VOUT = 5.5 V or GND
VIN / VOUT = 5.5 V
VIN / VOUT = 3.6 to 5.5 V
VIN = VCC or GND
VIN = one input at(VCC–0.6)V,
other inputs at VCC or GND
µA
HD74LVC540A
Switching Characteristics
Ta = –40 to 85°C
Item
Symbol
VCC (V)
Min
Typ
Propagation delay time
tPLH
tPHL
Output enable time
tZH
tZL
Output disable time
tHZ
tLZ
Between output
pins skew *1
tOSLH
tOSHL
Input capacitance
Output capacitance
CIN
CO
2.7
3.3±0.3
5.0±0.5
2.7
3.3±0.3
5.0±0.5
2.7
3.3±0.3
5.0±0.5
2.7
3.3±0.3
5.0±0.5
2.7
2.7
—
1.5
—
—
1.5
—
—
1.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3.0
15.0
Note:
Max
Unit
From
(Input)
To
(Output)
7.5
6.5
5.0
9.5
8.5
7.0
8.5
7.5
6.5
—
1.0
1.0
—
—
ns
A
Y
ns
G1 or G2
Y
ns
G1 or G2
Y
ns
pF
pF
1. This parameter is characterized but not tested.
tosLH = | tPLHm - tPLHn|, tosHL = | tPHLm - tPHLn|
Test Circuit
VCC
VCC
G1
Output
Pulse generator
Zout = 50 Ω
See Function Table
Input
A1
500 Ω S1
Y1
CL =
50 pF
450 Ω
OPEN
*1 See under table
GND
50 Ω Scope
G2
Symbol
t PLH / t PHL
t ZH/ t HZ
t ZL / t LZ
Notes:
1. CL includes probe and jig capacitance.
2. A2-Y2 to A8-Y8 are identical to above load circuit.
Rev.4.00 Jul. 28, 2004 page 4 of 6
S1
Vcc=2.7V,
3.3±0.3V
Vcc=5.0±0.5V
OPEN
GND
OPEN
GND
6V
2×Vcc
HD74LVC540A
Waveforms – 1
tf
tr
Input A
VIH
90 %
90 %
Vref
Vref
10 %
10 %
GND
t PHL
t PLH
VOH
Output Y
Vref
Vref
VOL
Notes:
1. tr = 2.5 ns, tf = 2.5 ns
2. Input waveform : PRR = 10 MHz, duty cycle 50%
Waveforms – 2
tf
Input G
tr
90 %
Vref
10 %
VIH
90 %
Vref
10 %
t LZ
t ZL
GND
≈V OH1
Vref
Waveform - A
t ZH
Waveform - B
VOL + 0.3 V
t HZ
VOH – 0.3 V
Vref
VOL
VOH
≈V OL1
TEST
VIH
Vref
VOH1
VOL1
Notes:
Vcc=2.7V,
3.3±0.3V
Vcc=5.0±0.5V
2.7 V
Vcc
1.5 V
3V
50%Vcc
GND
GND
Vcc
1. tr = 2.5 ns, tf = 2.5 ns
2. Input waveform : PRR = 10 MHz, duty cycle 50%
3. Waveform – A shows input conditions such that the output is "L" level when enable by the
output control.
4. Waveform – B shows input conditions such that the output is "H" level when enable by the
output control.
Rev.4.00 Jul. 28, 2004 page 5 of 6
HD74LVC540A
Package Dimensions
As of January, 2002
Unit: mm
12.6
13 Max
11
1
10
5.5
20
*0.20 ± 0.05
2.20 Max
1.15
0˚ – 8˚
0.10 ± 0.10
0.80 Max
0.20
7.80 +– 0.30
1.27
*0.40 ± 0.06
0.70 ± 0.20
0.15
0.12 M
Package Code
JEDEC
JEITA
Mass (reference value)
*Pd plating
FP–20DAV
—
Conforms
0.31 g
As of January, 2002
Unit: mm
6.50
6.80 Max
11
1
10
4.40
20
0.65
*0.20 ± 0.05
1.0
0.13 M
6.40 ± 0.20
*Pd plating
Rev.4.00 Jul. 28, 2004 page 6 of 6
0.07 +0.03
–0.04
0.10
*0.15 ± 0.05
1.10 Max
0.65 Max
0˚ – 8˚
0.50 ± 0.10
Package Code
JEDEC
JEITA
Mass (reference value)
TTP–20DAV
—
—
0.07 g
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Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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