Intersil HFA1149EVAL 450mhz, low power, video operational amplifier with programmable output disable Datasheet

HFA1149
TM
Data Sheet
June 2000
450MHz, Low Power, Video Operational
Amplifier with Programmable Output
Disable
The HFA1149 is a high speed, low power, current feedback
amplifier built with Intersil’s proprietary complementary
bipolar UHF-1 process. This amplifier features a unique
combination of power and performance specifically tailored
for video applications.
The HFA1149 incorporates an output disable pin which is
TTL/CMOS compatible, and user programmable for polarity
(active high or low). This feature eliminates the inverter
required between amplifiers in multiplexer configurations.
The ultra-fast (12ns/20ns) disable/enable times make the
HFA1149 the obvious choice for pixel switching and other
high speed multiplexing applications. The HFA1149 is a high
performance, pin compatible upgrade for the popular HA-5020
and HFA1145, as well as the CLC410.
For a comparably performing op amp without an output
disable, please refer to the HFA1109 data sheet.
File Number
4304.3
Features
• Wide - 3dB Bandwidth (AV = +2) . . . . . . . . . . . . . 450MHz
• Gain Flatness (To 250MHz) . . . . . . . . . . . . . . . . . . . 0.8dB
• Very Fast Slew Rate (AV = +2) . . . . . . . . . . . . . . 1100V/µs
• High Input Impedance . . . . . . . . . . . . . . . . . . . . . . 1.7MΩ
• Differential Gain/Phase. . . . . . . . . . . 0.02%/0.02 Degrees
• Low Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
• Fast Output Disable/Enable . . . . . . . . . . . . . . . 12ns/20ns
Applications
• Professional Video Processing
• Video Switchers and Routers
• Medical Imaging
• PC Multimedia Systems
• Video Pixel Switching
• Video Distribution Amplifiers
Ordering Information
PART NUMBER
(BRAND)
HFA1149IB
(H1149)
HFA11XXEVAL
• Flash Converter Drivers
TEMP.
RANGE (oC)
-40 to 85
PKG.
NO.
PACKAGE
8 Ld SOIC
Pinout
HFA1149
(SOIC)
TOP VIEW
-IN 2
+IN 3
HFA1149 PIN DESCRIPTIONS
M8.15
DIP Evaluation Board for High Speed
Op Amps
THRESHOLD SET 1
• Radar/IF Processing
PIN NAME
DESCRIPTION
Threshold Set
Optional Logic Threshold Set. Maintains disable
pin TTL compatibility with asymmetrical supplies
(e.g., +10V, 0V).
Polarity Set
Defines Polarity of Disable Input. High or floating
selects active low disable (i.e., DIS).
DIS/DIS
TTL Compatible Disable Input. Output is driven to
a true Hi-Z state when active. Polarity depends on
state of Polarity Set Pin.
8 DIS / DIS
7 V+
+
6 OUT
5 POLARITY SET
V- 4
1
HFA1149 DISABLE FUNCTIONALITY
POLARITY SET
(PIN 5)
DISABLE (PIN 8)
OUTPUT (PIN 6)
High or Float
High or Float
Enabled
High or Float
Low
Disabled
Low
High or Float
Disabled
Low
Low
Enabled
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000
HFA1149
Absolute Maximum Ratings
Thermal Information
Voltage Between V+ and V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V
DC Analog Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . VSUPPLY
Digital Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . VSUPPLY ±1V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V
Output Current (Note 2) . . . . . . . . . . . . . . . . Short Circuit Protected
30mA Continuous
60mA ≤ 50% Duty Cycle
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7) . . 1000V
Charged Device Model (Per EOS/ESD DS5.3, 4/14/93) . . 1000V
Machine Model (Per EIAJ ED-4701 Method C-111). . . . . . . . 50V
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
160
Maximum Junction Temperature (Die) . . . . . . . . . . . . . . . . . . . 175oC
Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
2. Output is short circuit protected to ground. Brief short circuits to ground will not degrade reliability, however, continuous (100% duty cycle) output
current must not exceed 30mA for maximum reliability.
VSUPPLY = ±5V, AV = +2, RF = 250Ω, RL = 100Ω, Unless Otherwise Specified
Electrical Specifications
PARAMETER
TEST CONDITIONS
(NOTE 3)
TEST
LEVEL
TEMP.
(oC)
MIN
TYP
MAX
UNITS
A
25
-
1
5
mV
A
Full
-
2
8
mV
B
Full
-
10
-
µV/oC
INPUT CHARACTERISTICS
Input Offset Voltage
Average Input Offset Voltage Drift
Input Offset Voltage
Common-Mode Rejection Ratio
Input Offset Voltage
Power Supply Rejection Ratio
∆VCM = ±2V
A
25
47
50
-
dB
∆VCM = ±2V
A
Full
45
48
-
dB
∆VPS = ±1.25V
A
25
50
53
-
dB
∆VPS = ±1.25V
A
Full
47
51
-
dB
A
25
-
4
10
µA
A
Full
-
5
15
µA
B
Full
-
30
-
nA/oC
∆VPS = ±1.25V
A
25
-
0.5
1
µA/V
∆VPS = ±1.25V
Non-Inverting Input Bias Current
Non-Inverting Input Bias Current Drift
Non-Inverting Input Bias Current
Power Supply Sensitivity
A
Full
-
0.5
3
µA/V
Inverting Input Bias Current
A
25
-
2
10
µA
A
Full
-
3
15
µA
Inverting Input Bias Current Drift
B
Full
-
40
-
nA/oC
Inverting Input Bias Current
Common-Mode Sensitivity
∆VCM = ±2V
A
25
-
3
6
µA/V
∆VCM = ±2V
A
Full
-
3
8
µA/V
∆VPS = ±1.25V
A
25
-
1.6
5
µA/V
∆VPS = ±1.25V
A
Full
-
1.6
8
µA/V
∆VCM = ±2V
A
25, 85
0.8
1.7
-
MΩ
∆VCM = ±2V
A
-40
0.5
1.4
-
MΩ
Inverting Input Resistance
B
25
-
60
-
Ω
Input Capacitance
B
25
-
1.6
-
pF
Input Voltage Common Mode Range (Implied
by VIO CMRR, +RIN, and -IBIAS CMS tests)
A
Full
±2
±2.5
-
V
Inverting Input Bias Current
Power Supply Sensitivity
Non-Inverting Input Resistance
2
HFA1149
VSUPPLY = ±5V, AV = +2, RF = 250Ω, RL = 100Ω, Unless Otherwise Specified (Continued)
Electrical Specifications
PARAMETER
TEST CONDITIONS
(NOTE 3)
TEST
LEVEL
TEMP.
(oC)
MIN
TYP
MAX
UNITS
Input Noise Voltage Density (Note 5)
f = 100kHz
B
25
-
4
-
nV/√Hz
Non-Inverting Input Noise Current Density
(Note 5)
f = 100kHz
B
25
-
2.4
-
pA/√Hz
Inverting Input Noise Current Density
(Note 5)
f = 100kHz
B
25
-
40
-
pA/√Hz
TRANSFER CHARACTERISTICS
Open Loop Transimpedance Gain (Note 5)
B
25
-
500
-
kΩ
Minimum Stable Gain
B
Full
-
1
-
V/V
AV = -1, RF = 200Ω
B
25
300
375
-
MHz
B
Full
290
360
-
MHz
AV = +1, +RS = 700Ω
B
25
280
330
-
MHz
AC CHARACTERISTICS
-3dB Bandwidth
(VOUT = 0.2VP-P, Note 5)
B
Full
260
320
-
MHz
AV = +2
B
25
390
450
-
MHz
B
Full
350
410
-
MHz
Gain Peaking
AV = +2, VOUT = 0.2VP-P
B
25
-
0
0.2
dB
B
Full
-
0
0.5
dB
Gain Flatness
(AV = +2, VOUT = 0.2VP-P, Note 5)
To 125MHz
B
25
-1.0
-0.45
-
dB
B
Full
-1.1
-0.45
-
dB
B
25
-1.6
-0.75
-
dB
B
Full
-1.7
-0.75
-
dB
B
25
-1.9
-0.85
-
dB
To 200MHz
To 250MHz
B
Full
-2.2
-0.85
-
dB
Gain Flatness
To 125MHz
AV = +1, +RS = 700Ω, VOUT = 0.2VP-P (Note 5)
B
25
±0.3
±0.1
-
dB
B
Full
±0.4
±0.1
-
dB
To 200MHz
B
25
±0.8
±0.35
-
dB
B
Full
±0.9
±0.35
-
dB
B
25
±1.3
±0.6
-
dB
B
Full
±1.4
±0.6
-
dB
To 250MHz
OUTPUT CHARACTERISTICS
Output Voltage Swing, Unloaded
(Note 5)
AV = -1, RL = ∞
Output Current
(Note 5)
AV = -1, RL = 75Ω
A
25
±3
±3.2
-
V
A
Full
±2.8
±3
-
V
A
25, 85
±33
±36
-
mA
A
-40
±30
±33
-
mA
Output Short Circuit Current
AV = -1
B
25
-
120
-
mA
Closed Loop Output Resistance (Note 5)
DC, AV = +1, Enabled
B
25
-
0.05
-
Ω
Second Harmonic Distortion
(VOUT = 2VP-P, Note 5)
20MHz
B
25
-
-55
-
dBc
60MHz
B
25
-
-57
-
dBc
Third Harmonic Distortion
(VOUT = 2VP-P, Note 5)
20MHz
B
25
-
-68
-
dBc
60MHz
B
25
-
-60
-
dBc
Reverse Isolation (S12)
30MHz
B
25
-
-65
-
dB
VOUT = 0.5VP-P
B
25
-
1.1
1.3
ns
B
Full
-
1.1
1.4
ns
TRANSIENT CHARACTERISTICS
Rise and Fall Times
3
HFA1149
VSUPPLY = ±5V, AV = +2, RF = 250Ω, RL = 100Ω, Unless Otherwise Specified (Continued)
Electrical Specifications
PARAMETER
TEST CONDITIONS
Overshoot
VOUT = 0.5VP-P
Slew Rate
(NOTE 3)
TEST
LEVEL
TEMP.
(oC)
MIN
B
25
B
Full
TYP
MAX
UNITS
-
0
2
%
-
0.5
5
%
AV = -1, RF = 200Ω
VOUT = 5VP-P
B
25
2300
2600
-
V/µs
B
Full
2200
2500
-
V/µs
AV = +1, VOUT = 4VP-P,
+RS = 700Ω
B
25
475
550
-
V/µs
B
Full
430
500
-
V/µs
AV = +2, VOUT = 5VP-P
B
25
940
1100
-
V/µs
B
Full
800
950
-
V/µs
Settling Time
(VOUT = +2V to 0V step, Note 5)
To 0.1%
B
25
-
19
-
ns
To 0.05%
B
25
-
23
-
ns
To 0.01%
B
25
-
36
-
ns
Overdrive Recovery Time
VIN = ±2V
B
25
-
5
-
ns
RL = 150Ω
B
25
-
0.02
0.06
%
B
Full
-
0.03
0.09
%
B
25
-
0.04
0.09
%
B
Full
-
0.05
0.12
%
B
25
-
0.02
0.06
Degrees
B
Full
-
0.02
0.06
Degrees
B
25
-
0.05
0.09
Degrees
B
Full
-
0.06
0.13
Degrees
Power Supply Range
C
25
±4.5
-
±5.5
V
Power Supply Current (Note 4)
A
25
-
9.6
10
mA
A
Full
-
10
11
mA
VIDEO CHARACTERISTICS
Differential Gain
(f = 3.58MHz)
RL = 75Ω
Differential Phase
(f = 3.58MHz)
RL = 150Ω
RL = 75Ω
POWER SUPPLY CHARACTERISTICS
HFA1149 DISABLE CHARACTERISTICS Polarity Set = Floating, Threshold Set = Floating, Unless Otherwise Specified
Disabled Supply Current
A
Full
-
2.8
3.5
mA
Digital Input Logic Low (Note 4)
VDIS = 0V
A
Full
-
-
0.8
V
Digital Input Logic High (Note 4)
A
25
2.0
-
-
V
A
Full
2.2
-
-
V
Digital Input Logic Low Current (Note 4)
VDIGITAL = 0V
A
Full
-
100
200
µA
Digital Input Logic High Current (Note 4)
VDIGITAL = 5V
A
Full
-
1
15
µA
Output Disable Time (Note 5)
VIN = ±0.5V,
VDIS = 2.4V to 0V
B
25
-
12
-
ns
Output Enable Time (Note 5)
VIN = ±0.5V,
VDIS = 0V to 2.4V
B
25
-
20
-
ns
B
25
-
2.5
-
pF
A
Full
-
3
10
µA
Disabled Output Capacitance
VDIS = 0V
Disabled Output Leakage
VDIS = 0V, VIN =
VOUT = ±3V
Off Isolation
(VDIS = 0V, VIN = 1VP-P, Note 5)
At 10MHz
B
25
-
-64
-
dB
At 30MHz
B
25
-
-54
-
dB
2V,
±
NOTES:
3. Test Level: A. Production tested; B. Typical or guaranteed limit based on characterization; C. Design Typical for information only.
4. Digital inputs are Polarity Set and DIS / DIS.
5. See Typical Performance Curves for more information.
4
HFA1149
Application Information
Optimum Feedback Resistor
Although a current feedback amplifier’s bandwidth
dependency on closed loop gain isn’t as severe as that of a
voltage feedback amplifier, there can be an appreciable
decrease in bandwidth at higher gains. This decrease may
be minimized by taking advantage of the current feedback
amplifier’s unique relationship between bandwidth and RF.
All current feedback amplifiers require a feedback resistor,
even for unity gain applications, and RF, in conjunction with
the internal compensation capacitor, sets the dominant pole
of the frequency response. Thus, the amplifier’s bandwidth is
inversely proportional to RF. The HFA1149 design is
optimized for a 250Ω RF at a gain of +2. Decreasing RF
decreases stability, resulting in excessive peaking and
overshoot (Note: Capacitive feedback will cause the same
problems due to the feedback impedance decrease at higher
frequencies). At higher gains the amplifier is more stable, so
RF can be decreased in a trade-off of stability for bandwidth.
TABLE 1. OPTIMUM FEEDBACK RESISTOR
GAIN
(ACL)
RF (Ω)
BANDWIDTH (MHz)
-1
200
375
+1
250 (+RS = 700Ω)
330
+2
250
450
+5
100
160
+10
90
70
Table 1 lists recommended RF values, and the expected
bandwidth, for various closed loop gains. For a gain of +1, a
resistor (+RS) in series with +IN is required to reduce gain
peaking and increase stability
Output Disable Function
The HFA1149 incorporates an output disable function that is
useful for reducing power dissipation or for multiplexing
signals onto a common analog bus. When disabled, the
inverting input and the output become high impedances
(however, the feedback network for gains other than +1 still
present a load to ground from the output), the supply current
reduces by 68%, and the input to output isolation becomes
greater than 60dB. The amplifier is disabled by driving the
DIS / DIS input to its active state.
The DIS / DIS input is TTL compatible, and unlike most
competitive devices, the TTL compatibility can be
maintained when the HFA1149 is operated at supplies other
than ±5V (see the “Threshold Set input” section below).
An internal resistive bias network ensures that the DIS / DIS
pin is pulled high if it is undriven on the PCB.
Polarity Set Input
A novel feature of the HFA1149 is the polarity
programmability of the disable control pin (DIS / DIS).
Depending on the state of the Polarity Set input (pin 5), the
designer can define the active state to be high or low for the
DIS / DIS input (see the “HFA1149 Disable Functionality”
table on the front page). With this feature, a 2:1 multiplexer
can be created by defining one amplifier’s disable control as
active low (Polarity Set = High or floating), and the other
amplifier’s control as active high (Polarity Set = Low). Note
that if the Polarity Set pin is left floating, an internal pull-up
resistor pulls the pin high, and the HFA1149 becomes a
drop-in replacement for any standard ±5V supply op amp
with output disable (e.g., CLC410, CLC411, CLC430,
HA-5020, HFA1145, AD810). Likewise, if the disable and
polarity set pins are both floated, the HFA1149 works just
like a standard op amp (i.e., the output is always enabled).
Threshold Set Input for TTL Compatibility
The HFA1149 derives an internal threshold reference for the
digital circuitry as long as the power supplies are nominally
±5V. This reference is used to ensure the TTL compatibility
of the DIS / DIS and Polarity Set inputs. With symmetrical
±5V supplies the Threshold Set pin (Pin 1) must be floated to
guarantee TTL compatibility. If asymmetrical supplies (e.g.,
+10V, 0V) are utilized, and TTL compatibility is desired, the
Threshold Set pin must be connected to an external voltage
(e.g., GND for +10V, 0V operation). The following equation
should be used to determine the voltage (VTHSET) to be
applied to the Threshold Set pin:
VV THSET = 1.58 ( V DIGTH + 1.6V ) – ------ – 0.46 ( V+ ),
8
where VDIGTH is the desired switching point (typically 1.4V
for TTL compatibility) of the Polarity Set and DIS / DIS
inputs.
Figure 1 illustrates the input impedance of the Threshold Set
pin for calculating the input current at a given VTHSET.
V+
The active state of the DIS / DIS input is user programmable
via the HFA1149’s Polarity Set input (see next paragraph). If
the Polarity Set input is left floating, or is tied to a logic high
(e.g., V+), then the disable function is activated by a logic
low on the DIS / DIS input (typical of most output disable op
amps). If the Polarity Set input is connected to a logic low
(e.g., GND), then a logic high on the DIS / DIS input disables
the amplifier.
5
7kΩ
VTHSET
3kΩ
25kΩ
V-
FIGURE 1. THRESHOLD SET INPUT IMPEDANCE
HFA1149
PC Board Layout
.
BOARD SCHEMATIC
The frequency response of this amplifier depends greatly on
the care taken in designing the PC board. The use of low
inductance components such as chip resistors and chip
capacitors is strongly recommended, while a solid
ground plane is a must! Attention should be given to
decoupling the power supplies. A large value (10µF)
tantalum in parallel with a small value (0.1µF) chip capacitor
works well in most cases.
Terminated microstrip signal lines are recommended at the
input and output of the device. Capacitance directly on the
output must be minimized, or isolated as discussed in the
next section.
Care must also be taken to minimize the capacitance to
ground seen by the amplifier’s inverting input (-IN). The
larger this capacitance, the worse the gain peaking, resulting
in pulse overshoot and possible instability. Thus, it is
recommended that the ground plane be removed under
traces connected to -IN, and connections to -IN should be
kept as short as possible.
Driving Capacitive Loads
Capacitive loads, such as an A/D input, or an improperly
terminated transmission line will degrade the amplifier’s
phase margin resulting in frequency response peaking and
possible oscillations. In most cases, the oscillation can be
avoided by placing a resistor (RS) in series with the output
prior to the capacitance.
510Ω
510Ω
50Ω
VH
1
8
2
7
0.1µF
10µF
+5V
50Ω
IN
10µF
3
6
4
5
0.1µF
OUT
VL
GND
GND
-5V
TOP LAYOUT
VH
1
+IN
OUT V+
VL VGND
BOTTOM LAYOUT
RS and CL form a low pass network at the output, thus
limiting system bandwidth well below the amplifier
bandwidth. By decreasing RS as CL increases, the
maximum bandwidth is obtained without sacrificing stability.
In spite of this, bandwidth still decreases as the load
capacitance increases.
Evaluation Board
The performance of the HFA1149 may be evaluated using
the HFA11XX Evaluation Board (part number
HFA11XXEVAL). Please contact your local sales office for
information. When evaluating this amplifier, the two 510Ω
gain setting resistors on the evaluation board should be
changed to 250Ω.
The layout and schematic of the board are shown in Figure 2.
NOTE: The SOIC version may be evaluated in the DIP board by
using a SOIC-to-DIP adapter such as Aries Electronics Part Number
08-350000-10.
6
FIGURE 2. EVALUATION BOARD SCHEMATIC AND LAYOUT
HFA1149
Typical Performance Curves
VSUPPLY = ±5V, TA = 25oC, RF = Value From the Optimum Feedback Resistor Table,
RL = 100Ω, Unless Otherwise Specified
2.0
200
AV = +2
150
1.5
100
1.0
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (mV)
AV = +2
50
0
-50
0.5
0
-0.5
-100
-1.0
-150
-1.5
-2.0
-200
TIME (5ns/DIV.)
TIME (5ns/DIV.)
FIGURE 4. LARGE SIGNAL PULSE RESPONSE
FIGURE 3. SMALL SIGNAL PULSE RESPONSE
2.0
200
AV = +1
150
1.5
100
1.0
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (mV)
AV = +1
50
0
-50
0.5
0
-0.5
-100
-1.0
-150
-1.5
-2.0
-200
TIME (5ns/DIV.)
TIME (5ns/DIV.)
FIGURE 5. SMALL SIGNAL PULSE RESPONSE
FIGURE 6. LARGE SIGNAL PULSE RESPONSE
200
2.0
AV = -1
150
1.5
100
1.0
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (mV)
AV = -1
50
0
-50
0.5
0
-0.5
-100
-1.0
-150
-1.5
-2.0
-200
TIME (5ns/DIV.)
FIGURE 7. SMALL SIGNAL PULSE RESPONSE
7
TIME (5ns/DIV.)
FIGURE 8. LARGE SIGNAL PULSE RESPONSE
HFA1149
Typical Performance Curves
VSUPPLY = ±5V, TA = 25oC, RF = Value From the Optimum Feedback Resistor Table,
RL = 100Ω, Unless Otherwise Specified (Continued)
2.0
200
1.5
AV = +5
50
AV = +10
AV = +10
0
-50
AV = +5
1.0
0.5
AV = +10
0
AV = +10
-0.5
-100
-1.0
-150
-1.5
-200
AV = +5
AV = +5
-2.0
TIME (5ns/DIV.)
TIME (5ns/DIV.)
FIGURE 10. LARGE SIGNAL PULSE RESPONSE
GAIN (dB)
FIGURE 9. SMALL SIGNAL PULSE RESPONSE
DISABLE
800mV/DIV.
(0.4V TO 2.4V)
3
VOUT = 200mVP-P
AV = +1
GAIN
0
-3
AV = +1
0
PHASE
AV = -1
90
AV = +1
OUTPUT
400mV/DIV.
180
0
AV = -1
AV = +2, VIN = 0.5V
0.3
1
10
TIME (10ns/DIV.)
100
270
700
FREQUENCY (MHz)
FIGURE 11. OUTPUT ENABLE AND DISABLE RESPONSE
FIGURE 12. FREQUENCY RESPONSE
510
3
VOUT = 200mVP-P
AV = +2
GAIN
480
AV = +2
AV = +10
-3
AV = +5
PHASE
AV = +2
0
90
AV = +10
180
AV = +5
0.3
1
10
100
FREQUENCY (MHz)
FIGURE 13. FREQUENCY RESPONSE
8
270
700
BANDWIDTH (MHz)
0
PHASE (DEGREES)
NORMALIZED GAIN (dB)
0
NORMALIZED PHASE (DEGREES)
100
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (mV)
150
450
420
AV = -1
390
360
AV = +1
330
300
-75
-50
-25
0
25
50
75
100
TEMPERATURE (oC)
FIGURE 14. -3dB BANDWIDTH vs TEMPERATURE
125
HFA1149
Typical Performance Curves
VSUPPLY = ±5V, TA = 25oC, RF = Value From the Optimum Feedback Resistor Table,
RL = 100Ω, Unless Otherwise Specified (Continued)
116
VOUT = 200mVP-P
( VIOI ) )
-0.1
-0.2
AZOL (dB, 20 LOG
NORMALIZED GAIN (dB)
106
AV = +1
0
-0.3
-0.4
-0.5
AV = +2
-0.6
-0.7
1
10
100
96
86
76
66
0
56
45
46
90
36
135
26
180
0.01
500
0.1
0.3
1
3
6 10
30
100
PHASE (DEGREES)
0.1
500
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 15. GAIN FLATNESS
FIGURE 16. OPEN LOOP TRANSIMPEDANCE
-30
-20
AV = +1
AV = +1
100MHz
-30
-40
100MHz
DISTORTION (dBc)
DISTORTION (dBc)
-40
-50
50MHz
-60
20MHz
10MHz
-70
-50
50MHz
-60
-70
20MHz
10MHz
-80
-80
-90
-100
-90
-6
-3
0
3
6
OUTPUT POWER (dBm)
9
12
-6
-3
0
FIGURE 17. 2nd HARMONIC DISTORTION vs POUT
6
9
12
FIGURE 18. 3rd HARMONIC DISTORTION vs POUT
-30
-30
AV = +2
AV = +2
-40
-40
100MHz
100MHz
DISTORTION (dBc)
DISTORTION (dBc)
3
OUTPUT POWER (dBm)
-50
50MHz
-60
10MHz
-70
-50
50MHz
-60
20MHz
-70
20MHz
10MHz
-80
-80
-90
-90
-6
-3
0
3
6
9
OUTPUT POWER (dBm)
12
FIGURE 19. 2nd HARMONIC DISTORTION vs POUT
9
15
-6
-3
0
3
6
9
OUTPUT POWER (dBm)
12
FIGURE 20. 3rd HARMONIC DISTORTION vs POUT
15
HFA1149
Typical Performance Curves
VSUPPLY = ±5V, TA = 25oC, RF = Value From the Optimum Feedback Resistor Table,
RL = 100Ω, Unless Otherwise Specified (Continued)
-20
-20
VOUT = 2VP-P
VOUT = 2VP-P
-30
-30
-40
DISTORTION (dBc)
DISTORTION (dBc)
AV = +1
-50
AV = +2, -1
-60
-40
AV = -1
-50
AV = +2
-60
AV = +1
-70
-70
AV = +1
-80
0
10
20
30
40
50
60
70
FREQUENCY (MHz)
80
90
-80
100
0
20
30
40
50
60
70
80
90
100
FREQUENCY (MHz)
FIGURE 21. 2nd HARMONIC DISTORTION vs FREQUENCY
FIGURE 22. 3rd HARMONIC DISTORTION vs FREQUENCY
AV = +2
AV = +2
VIN = 1VP-P
-30
-40
1K
OFF ISOLATION (dB)
OUTPUT RESISTANCE (Ω)
10
100
10
1
0.1
0.01
-50
-60
-70
-80
-90
-100
0.3
1
10
100
1000
0.5
1
10
FREQUENCY (MHz)
FIGURE 23. CLOSED LOOP OUTPUT RESISTANCE
FIGURE 24. OFF ISOLATION
3.6
14
+VOUT (RL = 100Ω)
13.5
|-VOUT| (RL = 100Ω)
OUTPUT VOLTAGE (V)
3.2
3.0 +VOUT (RL = 50Ω)
+VOUT (RL = 50Ω)
2.8
2.6
|-VOUT| (RL = 100Ω)
2.4
2.2
|-VOUT| (RL = 50Ω)
2.0
12.5
12
11.5
11
10.5
10
9.5
1.8
1.6
-75
13
SUPPLY CURRENT (mA)
3.4
100
FREQUENCY (MHz)
9
8.5
-50
-25
25
0
50
75
100
TEMPERATURE (°C)
FIGURE 25. OUTPUT VOLTAGE vs TEMPERATURE
10
125
4
4.5
5
5.5
6
6.5
7
7.5
SUPPLY VOLTAGE (±V)
FIGURE 26. SUPPLY CURRENT vs SUPPLY VOLTAGE
8
HFA1149
Typical Performance Curves
VSUPPLY = ±5V, TA = 25oC, RF = Value From the Optimum Feedback Resistor Table,
RL = 100Ω, Unless Otherwise Specified (Continued)
17
100
100
16
VS = ±8V
12
11
10
VS = ±5V
9
8
7
VS = ±4V
6
INIINI+
10
10
ENI
INI+
5
4
-75
1
1
-50
-25
0
25
50
75
100
0.1
125
1
10
FREQUENCY (kHz)
TEMPERATURE (oC)
FIGURE 27. SUPPLY CURRENT vs TEMPERATURE
FIGURE 28. INPUT NOISE CHARACTERISTICS
AV = +2
VOUT = 2V
0.1
0.05
0.025
0
-0.025
-0.05
-0.1
10
20
30
40
50
60
70
80
TIME (ns)
FIGURE 29. SETTLING RESPONSE
11
100
90
100
NOISE CURRENT (pA/√Hz)
NOISE VOLTAGE (nV/√Hz)
14
13
SETTLING ERROR (%)
SUPPLY CURRENT (mA)
15
HFA1149
Die Characteristics
DIE DIMENSIONS
GLASSIVATION
59 mils x 80 mils x 19 mils
1500µm x 2020µm x 483µm
Type: Nitride
Thickness: 4kÅ ±0.5kÅ
METALLIZATION
TRANSISTOR COUNT
Type: Metal 1: AICu(2%)/TiW
Type: Metal 2: AICu(2%)
Thickness: Metal 1: 8kÅ ±0.4kÅ
Thickness: Metal 2: 16kÅ ±0.8kÅ
130
SUBSTRATE POTENTIAL (POWERED UP)
Floating (Recommend Connection to V-)
Metallization Mask Layout
HFA1149
NC
THRESHOLD SET
DIS / DIS
NC
V+
-IN
OUT
NC
POLARITY SET
+IN
12
V-
NC
NC
HFA1149
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
N
INDEX
AREA
H
0.25(0.010) M
B M
E
INCHES
-B-
1
2
SYMBOL
3
L
SEATING PLANE
-A-
h x 45o
A
D
-C-
e
α
A1
B
0.25(0.010) M
C A M
MAX
MIN
MAX
NOTES
A
0.0532
0.0688
1.35
1.75
-
A1
0.0040
0.0098
0.10
0.25
-
B
0.013
0.020
0.33
0.51
9
C
0.0075
0.0098
0.19
0.25
-
D
0.1890
0.1968
4.80
5.00
3
E
0.1497
0.1574
3.80
4.00
4
e
C
0.10(0.004)
B S
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
MILLIMETERS
MIN
0.050 BSC
1.27 BSC
0.2284
0.2440
h
0.0099
0.0196
0.25
0.50
5
L
0.016
0.050
0.40
1.27
6
8o
0o
N
α
5.80
-
H
8
0o
6.20
-
8
7
8o
Rev. 0 12/93
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13
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