Intersil HI2555 1-bit, ad/da converter for audio application Datasheet

HI2555, CXD2555
®
NOT RE
September 1997
EW
ED FOR N
C O M ME N D
1-Bit, AD/DA Converter
For Audio Application
DESIGNS
Features
Description
• Two-Channel AD/DA Converters and Their Respective
Digital Filters for Decimation and Oversampling Into a
Single Chip
The HI2555, CXD2555 is a 1-bit stereo AD/DA converter
featuring a 2nd-order DA system noise shaper. This LSI has
also built-in digital filters and provides good cost performance.
• Peripheral Analog Circuits for AD Converter Greatly
Reduces External Elements
Functions
• Data Can Be Input/Output at Rate of 1 x fS with a BuiltIn Digital Filter
• Distortion (Typ)
- ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.01%
- DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.008% (-3dB)
• Simple Connection of Multiple HI2555, CXD2555s
Enable Multi-Channel System
• S/N Ratio (Typ)
- ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86dB
- DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96dB
• The 32-Slot Serial Data Interface Enables Independent
Selection of Data Frontward Packing/Rearward
Packing and MSB First/LSB First
• Ripple in the Digital Filter Pass Band . . . . . . . ±0.05dB
• The Master Clock is Applicable to Four Sources
• Attenuation in the Digital Filter Stop Band . . . . . . . .-45dB
• 256fS, 512fS, 768fS, and 1024fS
Ordering Information
PART
NUMBER
TEMP.
RANGE ( oC)
PACKAGE
PKG. NO.
• The Sampling Frequency May be Adjusted to Low fS
Frequencies Such as 16kHz or 8kHz, in Addition to
Normal Ones of 48kHz, 44.1kHz, and 32Hz
HI2555JCQ
-20 to 75
48 Ld MPQF
Q48.12x12-S
CXD2555Q
-20 to 75
48 Ld MPQF
Q48.12x12-S
• Various Frequency Divider Clocks Can Be Output for
LSIs Chips Connected
Pinout
DASL0
WO
DASL1
DVDD
SUB
NC
NC
AIN1
AVDD1
AVSS1
AOUT1+
AVSS3
HI2555, CXD2555 (48 LEAD MQFP)
TOP VIEW
AVDD3
1
48 47 46 45 44 43 42 41 40 39 38 37
36
AOUT1-
2
3
35
34
XSL1
4
5
33
32
31
MLSL
MASL
DVSS
30
29
SOUT
10
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
4-301
XSL0
SIN
BCK
LRCK
MS
DVDD
CLR
TEST
DVSS
XMCK2
26
11
25
12
13 14 15 16 17 18 19 20 21 22 23 24
AOUT2+
AVDD4
28
27
NC
AOUT2-
8
9
SUB
NC
XVSS
AVSS4
AVDD2
XTLO
6
7
AVSS2
AIN2
XCLK
XVDD
XTLI
AVSS4
AVSS3
UCLK
XSL2
File Number
4121.1
HI2555, CXD2555
XSL2
XSL1
XSL0
XTL0
XTL1
XCLK
UCLK
Block Diagram
36
35
34
8
7
5
4
CLOCK GENERATOR/ TIMING CIRCUIT
16
MAF1
ADC1
45 AIN1
MAF2
ADC2
16 AIN2
16
SOUT 30
LRCK 27
S
BCK 28
S
→P
←P
16
DIGITAL FILTER
(OVER SAMPLING
DECIMATION)
2
16
AOUT1(-)
DAC1
48 AOUT1(+)
SIN 29
11 AOUT2(-)
16
DAC2
16
32
33
MASL
MLSL
RAM
13 AOUT2(+)
10
ROM
Pin Descriptions
PIN NO.
SYMBOL
I/O
DESCRIPTION
1
AV DD 3
-
Analog power supply for Channel-1 DA converter.
2
AOUT1(–)
O
Analog opposite-phase output of Channel-1 DA converter
3
AVSS 3
-
Analog GND for Channel-1 DA converter.
4
UCLK
O
Outputs a 1/2 frequency divider of the clock input form the oscillator pin XTLI (Pin 7). User
clock output for externally connected ICs.
5
XCLK
O
256 fS clock output. this provides the master clock for ICs operating in the slave mode when
multiple CXD255Qs are connected. (When XSL2 = Low)
6
XV DD
-
Digital power supply for the master clock.
7
XTLI
I
Crystal oscillator circuit input. Connects the crystal oscillator selected by the crystal selection
pins XSLO to 2 (Pins 34, 35, and 36). Used to input the master clock from external.
8
XTLO
O
Crystal oscillator circuit output. Connects the crystal oscillator selected by the crystal selection
pins XSLO to 2 (Pins 34, 35, and 36).
9
XVSS
-
Digital GND for the master clock.
10
AVSS 4
-
Analog GND for Channel-2 DA converter.
11
AOUT2(-)
O
Analog opposite-phase output for Channel-2 DA converter.
12
AV DD 4
-
Analog power supply for Channel-2 DA converter.
12
AOUT2 (+)
O
Analog in-phase output for Channel-2 DA converter.
14
AVSS 4
-
Analog GND for Channel-2 DA converter.
15
AVSS 2
-
Analog GND for Channel-2 AD converter.
16
AIN2
I
Analog input for Channel-2 AD converter.
4-302
HI2555, CXD2555
Pin Descriptions
(Continued)
PIN NO.
SYMBOL
I/O
17
AV DD 2
-
DESCRIPTION
Analog power supply for Channel-2 AD converter.
18
NC
-
19
SUB
-
20
NC
-
21
DVSS
-
Digital GND.
22
XMCK2
O
IC measurement. Low is output normally.
23
TEST
I
Test pin. Normally fixed to Low. Equipped with a pull-down resistor.
24
CLR
I
System clear input. Normally High; cleared when Low. Equipped with a pull-up resistor.
25
DVDD
-
Digital power supply.
26
MS
I
Master/slave mode switching input. Master mode when High; slave mode when Low.
Equipped with a pull-up resistor.
27
LRCK
I/O
Serial I/O sampling frequency clock. Output i master mode (Pin 26 = High); input in slave mode
(Pin 26 = Low). Transfers Channel-1 data when high, and Channel-2 data when Low.
28
BCK
I/O
Serial bit transfer clock (64 fS) for serial input data SIN and serial output data SOUT. Output
in master mode (Pin 26 = High); input in slave mode (Pin 26 = Low). Serial input data is retrieved at the rising edge; serial output data is transferred at the falling edge.
29
SIN
I
Two channels per sampling serial data input. Data format is represented by 2’s complements,
and consists of 32-bit slots.
30
SOUT
O
Two channels per sampling serial data input. Data format is represented by 2’s complements,
and consists of 32-bit slots.
Connected to the IC internal circuit board (same electric potential as power supply). Connect
to GND on the printed circuit board via a capacitor.
31
DVSS
-
Digital GND.
32
MASL
I
Selects whether 16-bit serial data is place din the first 16-bit or the second 16-bit slots of the
serial I/O 32-bit slots. Forward packing when High; rearward packing when Low.
33
MLSL
I
Selects whether 16-bit serial data is input/output at LSB-first or MSB-first. MSB-first when
High; LSB-first when Low.
34
XSL0
I
Crystal selection. Selects the clock frequency to be input from XTLI (Pin 7) using three bits,
XSL 0 to 2.
35
XSL1
I
Crystal selection. Selects the clock frequency to be input from XTLI (Pin 7) using three bits,
XSL 0 to 2.
36
XSL2
I
Crystal selection. Selects the clock frequency to be input from XTLI (Pin 7) using three bits,
XSL 0 to 2.
37
DASL0
I
IC measurement. Normally fixed to High.
38
DASL1
I
IC measurement. Normally fixed to Low.
39
WO
I
Synchronization window open input. Window masked when High; window open when Low
(forced synchronization). Equipped with a pull-up resistor.
40
DVDD
-
Digital power supply
41
NC
-
42
NC
-
43
SUB
-
44
AV DD 1
-
Analog power supply for Channel-1 AD converter.
45
AIN1
I
Analog input for Channel-1 AD converter.
46
AVSS 1
-
Analog GND for Channel-1 AD converter.
47
AVSS 3
-
Analog GND for Channel-1 DA converter.
48
AOUT1(+)
O
Analog in-phase output for Channel-1 DA converter.
Connected to the IC internal circuit board (same electric potential as power supply). Connect
to GND on the printed circuit board via a capacitor.
4-303
HI2555, CXD2555
Absolute Maximum Ratings
TA = 25oC
Thermal Information
Supply Voltage (V DD). . . . . . . . . . . . . . . . . . . . . . . .VSS -0.5V to 7V
Input Voltage (V 1). . . . . . . . . . . . . . . . . . . . VSS -0.5V to V DD +0.5V
Output Voltage (V 0) . . . . . . . . . . . . . . . . . . VSS -0.5V to V DD +0.5V
Operating Temperature (TOPR) . . . . . . . . . . . . . . . . . -20oC to 75oC
Storage Temperature (TSTG) . . . . . . . . . . . . . . . . . . -55oC to 150oC
Recommended Operating Conditions
ITEM
MIN
Supply Voltage (Note 1) (VDD) . . . . . . . . . . . +4.75
Ambient Temperature (TA) . . . . . . . . . . . . . . -20oC
Sampling Frequency (Note 2) (fS) . . . . . . . . 30kHz
TYP
+5.0
-
MAX
+5.25V
75oC
50kHz
NOTES:
ITEM
MIN
TYP
MAX
Input Pin (CIN). . . . . . . . . . . . . . . . . . . . . . .
9pF
Output Pin (COUT . . . . . . . . . . . . . . . . . . . .
11pF
Bi-Directional Pin (CI/O) . . . . . . . . . . . . . . .
11pF
Measurement Conditions . . . . . . . . . . . . . VDD = VI = 0V, f = 1MHz
1. The analog power supplies for AD converters (Pins 17 and 44) must be turned on simultaneously with or before other power supplies.
turning on these power supplies after any other power supply may cause the device to fall into latch-up condition. This precaution, however, does not apply when turning off the power supplies.
2. Although the device can operate with low fS frequencies such as fS = 8kHz or 16kHz, its analog characteristics deteriorate to extent. When
used at only these low frequencies, the CXD2570Q is recommended that is pin-compatible with the CXD2555Q.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
DC Electrical Specifications (AVDD1 = AVDD 2 = AVDD 3 = AVDD 4 = XVDD = 5.0V ± 10%,
AVSS 1 = AVSS 2 = AVSS 3 = AVSS 4 = XVSS = DVSS = 0V, TA = -20oC to 75oC)
PARAMETER
Input Voltage
Output Voltage
Input Leakage Current
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
APPLICABLE
PIN
V
(Note 4)
VIHC
0.7 VDD
-
-
VILC
-
-
0.3 VDD
VIN
Analog Input
VSS
-
VDD
V
(Note 5)
VOH1
IOH = -2mA
VDD -0.5
-
0.4
V
(Note 6)
V
(Note 7)
V
(Note 8)
V
(Note 9)
VOL1
IOL = 4mA
0
-
0.4
VOH2
IOH = -4mA
VDD -0.5
-
VDD
VOL2
IOL = 4mA
0
-
0.4
VOH3
IOH = 12mA
VDD/2
-
V
VOL3
IOL = 16mA
0
-
VDD/2
VOH4
IOH = -2mA
VDD -0.8
-
VDD
VOL4
IOL = 4mA
0
-
0.4
IL11
-10
-
10
µA
(Note 10)
IL12
-40
-
40
µA
(Note 11)
IL13
-20
-50
-120
µA
(Note 12)
IL14
20
50
120
µA
(Note 13)
Output Leakage Current
ILZ
Feedback Resistance
RFB
VIN = VSS or VDD
Supply Current
IDD
(Note 3)
-40
-
40
µA
(Note 14)
250k
1M
2.5M
Ω
(Note 15)
-
57
75
mA
NOTES:
3. This includes current consumption at load resistance (R L = 3.9kΩ).
4. When all input pins except AIN1 and AIN2, and bi-directional pins (BCK, LRCK) are input.
5. AIN1 and AIN2.
6. XCLK, XMCK2, and SOUT.
7. AOUT1 (+), AOUT 1 (-), AOUT2 (+), AOUT2 (-), and UCLK.
8. XTLO.
9. When bi-directional pins (BCK, LRCK) are output.
10. All input pins except AIN1 and AIN2.
11. When bi-directional pins (BCK, LRCK) are input.
12. MS, WO, and CLR.
13. TEST.
14. SOUT, AOUT1 (+), AOUT1 (-), AOUT2 (+), AOUT2 (-), and UCLK.
15. Resistance between XTLO and XTLI.
4-304
HI2555, CXD2555
AC Electrical Specifications
AVDD1 = AVDD 2 = AVDD 3 = AVDD 4 = XVDD = 5.0V ± 10%,
AVSS 1 = AVSS 2 = AVSS 3 = AVSS 4 = XVSS = DVSS = 0V, TA = -20oC to 75oC
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
MAX
UNITS
SIN Setup Time
tsus
10
-
ns
SIN Hold Time
ths
15
-
ns
LRCK Setup Time
tsul
Slave Mode
10
-
ns
LRCK Hold Time
thl
Slave Mode
15
-
ns
LRCK Delay Time
tdl
Master Mode CL = 130pF
-40
30
ns
SOUT Delay Time
tds
CL = 60pF
9
65
ns
SOUT Data Reset Time
tzd
7
42
ns
SOUT Data Erase Time
tdz
6
40
ns
XTLI Pulse Width
twl
40
60
ns
MAX
UNIT
Analog Specifications
fS = 48kHz, 256fS
(XSL0 = XSL1 = XSL2 = L)
AVDD1 = AVDD 2 = AVDD 3 = AVDD 4 = XVDD = 5.0V ± 10%,
AVSS 1 = AVSS 2 = AVSS 3 = AVSS 4 = XVSS = DVSS = 0V, TA = -20oC to 75oC
PARAMETER
TEST CONDITIONS
MIN
TYP
Overall Characteristics of ADC + DAC Connection: The following conditions apply unless otherwise specified: Input waveform = 1kHz
sine wave, 1.4VRMS (= 0dB) XTAI = 33.8688MHz (= 768fS, fS = 44.1kHz) CLR = MS = WO = Open (= 5V) SOUT and SIN directly coupled
S/N
A-Weighting Filter
THD + N
20kHz LPF
Dynamic Range
1kHz, - 60dB, 20kHz LPF
Channel Separation
20kHz, 0dB
Gain Difference Between Channels
80
86
-
dB
-
0.010
0.018
%
80
85
-
dB
-
96
-
dB
-
0.1
-
dB
Gain
RL = 3.9kΩ
-3
0
+3
dB
Input Level
RIN = 0Ω
-
0.286
-
VRMS
RIN = 4.7kΩ
-
1.4
-
VRMS
DC Offset (ADC Output)
-
069F
-
Hex
ADC Input Impedance
-
1.2
-
kΩ
MAX
UNIT
Analog Specifications AVDD1 = AVDD 2 = AVDD 3 = AVDD 4 = XVDD = 5.0V ± 10%,
AVSS 1 = AVSS 2 = AVSS 3 = AVSS 4 = XVSS = DVSS = 0V, TA = -20oC to 75oC
PARAMETER
TEST CONDITIONS
MIN
TYP
DAC Specifications in Single Unit: The following conditions apply unless otherwise specified: Input data = 1kHz sine wave,full
scale (= 0dB), XTAI = 33.8688MHz (= 768fS, fS = 44.1kHz), CLR = MS = WO = Open (= 5V), MS = GND
S/N
A-Weighting Filter
THD + N
20kHz LPF
Dynamic Range
1kHz, - 60dB, 20kHz LPF
Channel Separation
20kHz, 0dB
Gain Difference Between Channels
Output Level
RL = 3.9kΩ
4-305
92
96
-
dB
-
0.008
0.012
%
85
89
-
dB
-
100
-
dB
-
0.05
-
dB
1.80
1.93
2.10
VRMS
HI2555, CXD2555
Test Circuits
10µF 4.7K
IN
+
+
AIN 1/2
100K
FIGURE 34. ADC INPUT SECTION
820pF
+5V
130K
AOUT 1/2 (-)
0.015µF
+
RL
47pF
4.7K
+5V
RL
AOUT 1/2 (+)
130K
-
4.7K
4.7K
+
820pF
RL = 3.9kΩ
+
RL
4.7K
4.7K
RL
47pF
FIGURE 35. DAC OUTPUT SECTION
4-306
4.7K
4.7K
OUT
+
1800pF
82pF
HI2555, CXD2555
Timing Diagram
tzd
tds
tdz
SOUT
BCK
tsus
ths
SIN
LRCK
(SLAVE MODE)
thl
tsul
BCK
tdl
LRCK
(MASTER MODE)
twl
XTLI
FIGURE 36.
Description of Functions
Serial Data Interface
TABLE 2.
(Related Pins) LRCK, BCK, SOUT, SIN, MASL, MLSL
MLSL
The serial data format is common for both SIN (DA converter
input) and SOUT (AD converter output), consisting of two
channels per sampling serial data represented by 2’s complement. Each channel is divided into 32-bit slots, of which
16 bits are handled as data.
MASL is used to select whether the 16 bits of valid data is
placed in the first or the second half of the 32-bit slots.
TABLE 1.
MASL
H
Forward Packing
L
Rearward Packing
Similarly, MLSL is used to select whether the serial data is
arranged at LSB first or MSB first.
TABLE 2.
MLSL
H
MSB first
4-307
L
LSB first
HI2555, CXD2555
Crystal Oscillator Frequency Selection
(fS = 32kHz to 48kHz)
Master Mode/Slave Mode
(Related Pins) MS, LRCK, BCK
When using the XCS2555Q in multiple units or in a pair with
DA converters such as the CXD2558M, one of these
CXD2555Qs should be in the master mode to serve as the
source of clocks LRCK and BCK. The other CXD2555Qs are
used in the slave mode, with their clocks LRCK and BCK
supplied by the master CXD2555Q.
TABLE 3.
MS
MODE
LRCK AND BCK I/O
H
Master Mode
Output
L
Slave Mode
Input
(Related Pins) XTLI, XTLO, XSLO, XSL1, XSL2, UNCLK,
XCLK
By setting a combination of XSLO and XSL1, with XSL2
fixed Low, the frequency of the external crystal oscillator
connected to XTLI and XTLO can be selected. In this case,
XCLK outputs a clock whose frequency is always 256 times
fS, and UCLK outputs a clock that is half the crystal oscillator
frequency.
When supplying the master clock fro some other external
source, not a crystal oscillator, use XTLI for this clock input
and leave XTLO open.
TABLE 4.
XSL2
XSL1
XSL0
CRYSTAL OSCILLATOR FREQUENCY
XCLK
UCLK
L
L
L
256fS
256fS
128fS
L
L
H
512fS
256fS
256fS
L
H
L
768fS
256fS
384fS
L
H
H
1024fS
256fS
512fS
OUTPUT
INPUT
MS CXD2555Q
(MASTER MODE)
OUTPUT
BCK
INPUT
LRCK
H
INPUT
INPUT
LRCK
CXD2555Q MS
(SLAVE MODE)
L
BCK
LRCK
CXD2558M
BCK
FIGURE 37. CONNECTION EXAMPLE
Crystal Oscillator Frequency Selection
(fS = 8kHz to 24kHz)
(Related Pins) XTLI, XTLO, XSLO, XSL1, XSL2, UNCLK,
XCLK
With XSL2 fixed High, the device can be operated with lowfS frequencies which may be 1/2 or 1/4 the normal fS
frequency. In this case, the frequency of the crystal oscillator
can be selected by setting a combination of XSL0 and XSL1
accordingly.
UCLK
L
XSL2
H
XSL1 CXD2555Q
H
XSL0
XTL1
XCLK
512fS
256fS
XTL0
TO EXTERNAL IC,
SUCH AS DSP
TO CXD2555Q IN
SLAVE MODE
1024fS
FIGURE 38. CONNECTION EXAMPLE
AD Converter Input Level
Given the constants shown in the Test Circuit on page 7, the
AD converter input level V IN (operational amplifier input IN)
is such that 4V P-P (1.4VRMS) is equivalent to the full-scale
output. Also, the large-amplitude inputs are possible by
varying the AD converter input resistance value (RIN). Use
the equation shown below to calculate this resistance value.
The AD converter generates full-scale outputs for inputs
equal to or greater than the values thus obtained.
Example: When input level = 1.4VRMS (4V P-P)
RIN = 420 • VIN [RMS] - 1200 [Ω]
4-308
RIN = 4200 • 1.4 - 1200 = 4680
→ 4700 [Ω]
CXD2555Q
10µF 10µF
VIN
RIN
AIN
+
100K
FIGURE 39.
TABLE 5.
XSL2
XSL1
XSL0
CRYSTAL OSCILLATOR
FREQUENCY (NOTE 16)
XCLK
UCLK
FREQUENCY DIVISION
RATIO RELATIVE TO
NORMAL f S FREQUENCY
EXAMPLE OF 32kHz
NORMAL FREQUENCY
fS = 16kHz
H
L
L
512fS
512fS
256fS
1/2
H
L
H
1024fS
1024fS
512fS
1/4
fS = 8kHz
H
H
L
1024fS
512fS
512fS
1/2
fS = 16kHz
H
H
H
2048fS
1024fS
1024fS
1/4
fS = 8kHz
NOTE:
16. When the normal frequency is assumed to be 32kHz, its derived frequency is 16kHz when divided by 2, or 8kHz when divided by 4. When
divided in the same way, the low-fS frequencies for 44.1kHz are 22.05kHz and 11.025kHz, and for 48kHz, they are 24kHz and 12kHz.
4-309
Serial Data Interface Timing
HI2555, CXD2555
4-310
Application Circuit Master Mode (MS = High)
HI2555, CXD2555
4-311
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