Intersil HI3-7151J-5 10-bit, high speed, a/d converter with track and hold Datasheet

®
December 1997
R
N OT
M
ECO
FOR
ED
D
N
ME
NE
N
ESIG
WD
HI-7151
S
10-Bit, High Speed, A/D Converter
with Track and Hold
Features
Description
• Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . 10µs
The Intersil HI-7151 is a high speed 10-bit A/D converter
which uses a 2-Step Flash algorithm to achieve throughput
rates of 100kHz. A unique switched capacitor technique
allows a new input voltage to be sampled while a conversion
is taking place.
• Continuous Throughput Rate . . . . . . . . . . . . . . . 100kHz
• No Offset or Gain Adjustments Necessary
• Internal Track and Hold Amplifier
A Track and Hold amplifier is included on the chip, consisting
of two high speed amplifiers and an internal hold capacitor.
• Analog and Reference Inputs Fully Buffered
• µP Compatible Byte Organized Outputs
• Low Power Consumption . . . . . . . . . . . . . . . . . . 150mW
• Uses a Single 2.5V Reference for ±2.5 V Input Range
Applications
Microprocessor bus interfacing is simplified by the use of
standard Chip Select, Read, and Write control signals. The
digital three-state outputs are byte organized for interfacing
the either 8- or 16-bit systems. An Over-Range pin, together
with the MSB, can be used to indicate an out-of-range
condition.
The HI-7151 operates with ±5V supplies. A single +2.5V
reference is required to provide a bipolar input range from
-2.5V to +2.5V.
• µP Controlled Data Acquisition Systems
• DSP
- Avionics
- Sonar
Internal high speed CMOS buffers at both the analog and
reference inputs simplify external drive requirements.
Ordering Information
• Process Control
- Automotive Transducer Sensing
- Industrial
PART
NUMBER
• Robotics
LINEARITY
(MAX. DLE)
TEMP.
RANGE (oC)
HI3-7151J-5
±1 LSB
0 to 75
28 Ld PDIP
HI3-7151K-5
±1/2 LSB
0 to 75
28 Ld PDIP
PACKAGE
• Digital Communications
HI3-7151A-9
±1 LSB
0 to 85
28 Ld PDIP
• Image Processing
HI3-7151B-9
±1/2 LSB
0 to 85
28 Ld PDIP
HI1-7151S-2
±1 LSB
-55 to 125
28 Ld CERDIP
HI1-7151T-2
±1/2 LSB
-55 to 125
28 Ld CERDIP
Pinout
HI-7151
(PDIP, CERDIP)
TOP VIEW
GND 1
V- 2
28 V+
27 OVR
VREF 3
26 D9
AG 4
25 D8
VIN 5
24 D7
SET 6
23 D6
BUSY 7
22 D5
CLK 8
21 D4
HOLD 9
20 D3
WR 10
19 D2
CS 11
18 D1
RD 12
17 D0
SMODE 13
16 HBE
DG 14
15 BUS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
1
File Number
3099.1
HI-7151
Functional Diagram
VREF
3
REF
AMP
REF
INVERT
(+)
5
17
D0
(-)
AG
(ANALOG GROUND) 4
VIN
(ANALOG INPUT)
(33)
TWO
STEP
FLASH
RESISTOR
LADDER
LATCHES
AND
OUTPUT
BUFFERS
DATA
OUTPUTS
26
27
INPUT
BUFFER
AMP
7
(1)
BUS
CTRL
15
16
D9
OVR
BUSY
BUS
HBE
TRACK
HOLD
AMP
9
V+
VGND
12
28
2
1
POWER
SUPPLY
DISTRIBUTION
10
CONTROL
LOGIC
11
13
DG
14
(DIGITAL GROUND)
8
6
2
HOLD
RD
WR
CS
SMODE
CLK
SET
HI-7151
Pin Descriptions
PIN
NAME
1
GND
Ground return for comparators (0V).
2
V-
Negative supply voltage input (-5V).
3
VREF
4
AG
Analog ground reference (0V).
5
VIN
Analog Input Voltage.
6
SET
Connect to V+ for proper operation.
7
BUSY
8
CLK
9
HOLD
10
WR
Write input. With CS low, starts conversion when pulsed low; continuous conversions when kept low.
11
CS
Chip select input. Active low.
12
RD
Read input. With CS low, enables output buffers when pulsed low; outputs updated at end of conversion when kept low.
13
DESCRIPTION
Reference voltage input (+2.5V).
Output High-Conversion complete. Output Low - Conversion in progress. Output floats when chip is not selected (RD
and CS both high).
Clock input.
Indicates start of conversion. Active low.
SMODE Slow memory mode input. Active high.
14
DG
Digital ground (0V).
15
BUS
Bus select input. High = all outputs enabled together D0 - D9, OVR. Low = outputs enabled by HBE.
16
HBE
Byte select (HBE/LBE) input for 8-bit bus. Input high-High byte select, D8-D9, OVR Input low-low byte select, D0-D7.
17
D0
Bit 0 (Least significant, LSB).
18
D1
Bit 1.
19
D2
Bit 2.
20
D3‘
Bit 3.
21
D4
Bit 4.
22
D5
Bit 5.
23
D6
Bit 6.
24
D7
Bit 7.
25
D8
Bit 8 (Most Significant).
26
D9
Bit 9 (Sign).
27
OVR
28
V+
Low
Byte
Output Data Bits
(High = True)
High
Byte
Out of Range flag. Valid at end of conversion when output exceeds full scale.
Positive supply voltage input (+5V).
3
HI-7151
Absolute Maximum Ratings (Note 1)
Thermal Information
Supply Voltage
V+ to Gnd (DG/AG/GND) . . . . . . . . . . . . . . . . -0.3V < V+ < +5.7V
V- to Gnd (DG/AG/GND). . . . . . . . . . . . . . . . . .-5.7V < V- < +0.3V
Analog Input Pins . . . . . . . . . . . . . . . . . V- -0.3V < VINA < V+ +0.3V
Digital I/O Pins . . . . . . . . . . . . . . . . . . .DG - 0.3V < VI/O < V+ +0.3V
Thermal Resistance (Typical)
θJA ( oC/W) θJC (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . .
__
N/A
CERDIP Package . . . . . . . . . . . . . . . .
__
__
Maximum Power Dissipation (Note 2). . . . . . . . . . . . . . . . . <500mW
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . . 300oC
Operating Conditions
Temperature Range
HI3-7151X-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to 75oC
HI3-7151X-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Input voltages may exceed the supply voltage provided the inputs current is limited to ±1mA.
2. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board (derate above 75oC at -10mW/oC).
Electrical Specifications
PARAMETER
V+ = +5V, V- = -5V, VREF = 2.5V, fCLK = 300kHz, 50% Duty Cycle, Unless Otherwise Specified (Note 4)
SYMBOL
(NOTE 3)
TEMPERATURE
J, A GRADE
K, B GRADE
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
TA = -25oC
10
-
-
10
-
-
Bits
TMIN to TMAX
ACCURACY
Resolution (Note 5) (With
no missing codes)
Integral Linearity Error
Differential Linearity Error
Bipolar Offset Error
Unadjusted Gain Error
RES
ILE
DLE
VOS
eG+ and
eG-
10
-
-
10
-
-
Bits
TA = 25oC
-
±0.5
±1.0
-
±0.3
±-0.5
LSB
TMIN to TMAX
-
±0.75
±1.0
-
±0.5
±0.75
LSB
TA = 25oC
-
-
±1.0
-
-
±0.5
LSB
TMIN to TMAX
-
-
±1.0
-
-
±0.75
LSB
TA = 25oC
-
±1.0
±2.5
-
±0.6
±1.5
LSB
TMIN to TMAX
-
±1.5
±3.0
-
±1.0
±2.0
LSB
TA = 25oC
-
±1.0
±2.5
-
±0.6
±1.5
LSB
TMIN to TMAX
-
±1.5
±3.0
-
±1.0
±2.0
LSB
NOTE:
3. TMIN to TMAX: See Ordering Information Table.
DC Electrical Specifications V+ = 5V, V- = -5V, VREF = 2.5V, TA = 25oC, fCLK = 300kHz, 50% Duty Cycle,
Unless Otherwise Specified
PARAMETER
SYMBOL
(NOTE 4)
CONDITIONS
25oC
0oC to 75oC
-40oC to 85oC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
-VREF
-
VREF
-VREF
VREF
-VREF
VREF
V
ANALOG INPUT
Analog Input Range
VIR
Analog INput Bias Current
IBI
-
0.01
100
-
100
-
100
nA
Analog Input Capacitance
(Note 5)
CVIN
-
8
20
-
-
-
-
pF
2.2
2.5
2.6
2.2
2.6
2.2
2.6
V
VIN = 0V
REFERENCE INPUT
Reference Input Range
(Note 6)
VRR
Reference Input Bias Current
IBR
-
0.01
100
-
100
-
100
nA
Reference Input Capacitance
(Note 5)
CVR
-
7
20
-
-
-
-
pF
VREF = 2.5V
4
HI-7151
DC Electrical Specifications V+ = 5V, V- = -5V, VREF = 2.5V, TA = 25oC, fCLK = 300kHz, 50% Duty Cycle,
Unless Otherwise Specified (Continued)
PARAMETER
SYMBOL
(NOTE 4)
CONDITIONS
25oC
0oC to 75oC
-40oC to 85oC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
TRACK AND HOLD (See Text)
Slew Rate
SR
-
9
-
-
-
-
-
V/µs
Bandwidth
BW
-
1.5
-
-
-
-
-
MHz
Aperture Time
-
30
-
-
-
-
-
ns
Aperture Uncertainty
-
2
-
-
-
-
-
ns
-
-80
-
-
-
-
-
dB
-
1.5
-
-
-
-
-
µs
fIN = 100kHz
Feedthrough in HOLD
Acquisition Time
LOGIC INPUTS
Input High Voltage
VIH
2.0
-
-
2.0
-
2.0
-
V
Input Low Voltage
VIL
-
-
0.8
-
0.8
-
0.8
V
Logic Input Current
IIL
-
0.05
1
-
1
-
1
µA
-
5
17
-
-
-
-
pF
Input Capacitance (Note 5)
VIN = 0V, V+
CIN
LOGIC OUTPUTS
Output High Voltage
VOH
IOH = -200µA
2.4
-
-
2.4
-
2.4
-
V
Output Low Voltage
VOL
IOL = 1.6mA
-
-
0.4
-
0.4
-
0.4
V
Output Leakage Current
IOL
RD = V+, VOUT = V+
-
0.04
1
-
10
-
10
µA
RD = V+, VOUT = 0V
-1
-0.01
-
-10
-
-10
-
µA
High-Z State
-
7
15
-
-
-
-
pF
4.5
5.0
5.5
4.5
5.5
4.5
5.5
V
-4.5
-5.0
-5.5
-4.5
-5.5
-4.5
-5.5
V
V+ = 5V, V- = -4.75V,
-5.25V
-
±0.1
±0.05
-
±0.6
-
±0.6
LSB
V- = -5V, V+ = 4.75V,
5.25V
-
±0.1
±0.5
-
±0.6
-
±0.6
LSB
V+ = 5V, V- = -4.75V,
-5.25V
-
±0.1
±0.5
-
±0.6
-
±0.6
LSB
V- = -5V, V+ = 4.75V,
5.25V
-
±0.1
±0.5
-
±0.6
-
±0.6
LSB
V+ = 5V ±10%
V- = -5V ±10%
VIN = 0V, Digital
Outputs are
Unloaded
-
20
30
-
30
-
30
mA
-
-10
-15
-
-15
-
-15
mA
-
-8
-15
-
-15
-
-15
mA
-
-2
-3
-
-3
-
-3
mA
-
0.02
10
-
10
-
10
µA
Output Capacitance (Note 5)
COUT
POWER SUPPLY VOLTAGE RANGE
(Note 7)
V+
(Note 7)
V-
Function Operation
Only
POWER SUPPLY REJECTION
V+, V- Gain Coefficient
V+, V- Offset Coefficient
eGVS
VOSVS
SUPPLY CURRENTS
V+ Supply Current
I+
V- Supply Current
I-
GND Current
IGND
DG Current
IDG
AG Current
IAG
NOTES:
4. FSR (Full Scale Range) = 2 X V REF (5V at VREF = 2.5V). LSB (Least Significant Bit) = FSR/1024 (4.88mV at VREF = 2.5V)
5. Parameter not tested. Parameter guaranteed by design, simulation, or characterization.
6. Only VOS and GAIN ERROR functionality tested at 2.2V and 2.6V.
7. Guaranteed by functionality test.
5
HI-7151
AC Electrical Specifications V+ = 5V ±10%, V- = -5V ±10%, VREF = 2.5V, TA = 25oC, fCLK = 300kHz, 50% Duty Cycle,
CL = 100pF (including stray for D0 - D9, OVR, HOLD, BUSY), Unless Otherwise Specified (Note 11)
25oC
0oC to 75oC
-40oC to 85oC
SYMBOL
NOTES
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
D
5
45
50
55
45
55
45
55
%
tSPS
9
-
-
3tck
-
3tck
-
3tck
µs
9
60
-
10
60
10
60
10
µs
tCONV
5, 8
-
-
4tck
+0.9
-
4tck
+0.9
-
4tck
+0.9
µs
tCYC
9
-
-
fCLK/3
-
fCLK/3
-
fCLK/3/
3
sps
tCK
-
-
1/fCLK
-
-
-
-
-
CLOCK to HOLD Rise Delay
tCKHR
5
150
290
500
140
525
120
525
ns
WR Pulse Width
tWRL
5, 8, 10
200
113
tck/2
225
tck/2
225
tck/2
ns
WR to HOLD Delay
tHOLD
5, 8
-
80
170
-
200
-
200
ns
tBD
5, 8
-
40
200
-
230
-
230
ns
WR to RD Active
tWRD
5, 8
100
-
-
100
-
100
-
ns
CLOCK to HOLD Fall Delay
tCKHF
5, 9
50
125
250
40
275
25
275
ns
HOLD to DATA change
tDATA
5, 9
100
200
400
90
550
70
550
ns
RD LO to Active
tRD
5, 13
-
75
150
-
190
-
190
ns
RD HI to Inactive
tRX
5, 14
-
25
60
-
80
-
80
ns
HBE to DATA
tAD
5
-
70
150
-
165
-
165
ns
CS to DATA
tCD
5
-
95
180
-
210
-
210
ns
RD to BUSY
tBUSY
5
-
35
200
-
200
-
200
ns
Rise Time
tr
5, 12
-
50
100
-
125
-
125
ns
Fall Time
tf
5, 12
-
45
100
-
120
-
120
ns
PARAMETER
Clock Input Duty Cycle
Continuous Conversion Time
Slow Memory Mode Conversion
Time
Continuous Throughput
CLOCK Period
Busy to Data
NOTES:
8. Slow memory mode timing.
9. Fast memory or DMA mode of operation, except the first conversion which is equal to tCONV .
10. Maximum specification to prevent multiple triggering with WR.
11. All input drive signals are specified with tr = tf ≤ 20ns and shall swing from VIL -0.4V to V IH +0.4V for all timing specifications. A signal is
considered to change state as it crosses a 1.4V threshold (except tRD and tRX).
12. tr and tf load is CL = 100pF (including stray capacitance) to DG and is measured from the 10 - 90% point.
13. tRD is the time required for the data output level to change by 10% in response to RD crossing a voltage level of 1.4V. High-Z to VOH is
measured with RL = 2.5kΩ and C L = 100pF (including stray) to DG. High-Z to VOL is measured with RL = 2.5kΩ to V+ and CL = 100pF
(including stray) to DG.
14. trx is the time required for the data output level to change by 10% in response to RD crossing a voltage level of 1.4V. VOH to High-Z is
measured with RL = 2.5kΩ and C L = 10pF (including stray) to DG. VOL to High-Z is measured with RL = 2.5 kΩ to V+ and CL = 10pF
(including stray) to DG.
6
HI-7151
Timing Diagrams
SMODE = +V, BUS = V+, HBE = V+ OR DG
0
1
tCK
2
3
4
5
CLOCK
CS
WR
HOLD TRACK N
tWRL
tCKHR
HOLD N
TRACK N+1
tHOLD
INTERNAL
DATA
RD
BUSY
N DATA
tWRD
tBUSY
tBD
D0-D9, OVR
DATA
N DATA
tCONV
FIGURE 1A. SLOW MEMORY MODE (16-BIT DATA BUS)
7
6
7
HI-7151
Timing Diagrams
(Continued)
SMODE = DG, BUS = DG
0
1
2
3
4
5
6
7
CLOCK
tCD
CS
WR
HOLD
tSPS
(WR MAY BE WIRED LOW)
TRACK N
tCKHF
tHOLD
HOLD N
tCKHR
HOLD N+1
TRACK N+1
HOLD N+2
TRACK N+2
TRACK N+3
tDATA
INTERNAL
DATA
N+1 DATA
N DATA
RD
HBE
(HBE/LBE)
tRD
D0-D9, OVR
DATA
tAD
HIGH
BYTE
BUSY
tRX
LOW
BYTE
N DATA
HIGH
BYTE
LOW
BYTE
N+1 DATA
FIGURE 1B. FAST MEMORY MODE (8-BIT DATA BUS)
SMODE = +V: RD, WR, AND CS = DG
0
1
2
3
4
5
6
7
CLOCK
HOLD
INTERNAL
DATA
TRACK N
HOLD N
TRACK N+1
HOLD N+1
TRACK N+2
HOLD N+2
N-1 DATA
N DATA
N+1 DATA
N-1 DATA
N DATA
N+1 DATA
BUSY
D0-D9, OVR
DATA
FIGURE 1C. DMA MODE
8
HI-7151
5 TO 32
DECODER
(+VREF)
AZ
VREF
3
AZ
33
AZ
+
REF(+)
AMP
17
AZ
1R
AZ
32
AZ
AG
4
AZ
1R
2
AZ
REF(+)
AMP
SCAZ
32 TO 5
ENCODER
OUTPUT
BUFFERS
LATCHES
AND
OUTPUT
BUFFERS
1
LATCH
BUS
CTRL
SCAZ
(AG)
VIN
5
(ANALOG INPUT)
+
+
TRACK
BUFFER
AMP
CH
HOLD
AMP
SCAZ
32C
V+
VGND
CONTROL
LOGIC
+
(-VREF )
(AG)
16
10
C
-
HOLD
15
12
SCAZ
-
26
9
SCAZ
28
SWITCHED
CAP
AMP
POWER
SUPPLY
DISTRIBUTION
2
1
DG
14
(DIGITAL GROUND)
FIGURE 2. DETAILED BLOCK DIAGRAM
9
DO
DATA
OUTPUTS
27
7
LATCH
AZ
AZ
(-VREF)
LATCH
AZ
AZ
+
LATCH
11
13
8
6
D9
OVR
BUSY
BUS
HBE
HOLD
RD
WR
CS
SMODE
CLK
SET
HI-7151
Detailed Description
The 5-bit result of the first flash conversion is latched into the
upper five bits of double buffered latches. It is also converted
back into an analog signal by choosing the ladder voltage
which is closest to but less than the input voltage. The
selected voltage (VTAP) is then subtracted from the input
voltage. This residue is amplified by a factor of 32 and
referenced to the negative reference voltage (VSCA = (VIN VTAP) X 32 + VREF -). This subtraction and amplification
operation is performed by a Switched Capacitor Amplifier
(SCA). The output of the SCA falls between the positive and
negative reference voltages and can therefore be digitized
by the original 5-bit flash converter (second flash
conversion).
The HI-7151 is a high speed 10-bit A/D converter which
achieves throughput rates of 100kHz by use of a Two Step
Flash algorithm. A pipelined operation has been achieved
through the use of switched capacitor techniques which
allow the device to sample a new input voltage while a
conversion is taking place. The HI-7151 requires a single
reference input of +2.5V, which is internally inverted to 2.5V, thereby allowing an input range of -2.5V to +2.5V. 10
bits including sign are two’s complement coded. The analog
and reference inputs are internally buffered by high speed
CMOS buffers, which greatly simplifies the external analog
drive requirements for the device.
The 5-bit result of the second flash conversion is latched into
the lower five bits of double buffered latches. At the end of a
conversion, 10 bits of data plus an Out of Range bit are
latched into the second level of latches and can then be put
on the digital output pins.
A/D Section
The HI-7151 uses a conversion algorithm which is generally
called a “Two Step Flash” algorithm. This algorithm enables
very fast conversion rates without the penalty of high power
dissipation or high cost. A detailed functional diagram is
presented in Figure 2.
The conversion takes place in three clock cycles and is
illustrated in Figure 3. When the conversion begins, the track
and hold goes into its hold mode for 1 clock cycle. During the
first half clock cycle the comparator array is in its auto-zero
mode and it samples the input voltage. During the second
half clock cycle, the comparators make a comparison
between the input voltage and the ladder voltages. At the
beginning of the third half clock cycle, the first most
significant 5-bit result becomes available. During the first
clock cycle, the SCA was sampling the input voltage. After
the first flash result becomes available and a ladder tap
voltage has been selected the SCA amplifies the residue
between the input and ladder tap voltages. During the next
three half clock cycles, while the SCA output is settling to its
required accuracy, the comparators go into their auto-zero
mode and sample this voltage. During the sixth half clock
cycle, the comparators perform another comparison whose
5-bit result becomes available on the next clock edge.
The input voltage is first converted into a 5-bit result (plus
Out of Range information) by the flash converter. This flash
converter consists of an array of 33 auto-zeroed comparators which perform a comparison between the input voltage
and subdivisions of the reference voltage. These subdivisions of the reference voltage are formed by forcing the reference voltage and its negative on the two ends of a string of
32 resistors.
The reference input to the HI-7151 is buffered by a high
speed CMOS amplifier which is used to drive one end of the
resistor string. Another high speed amplifier configured in
the inverting unity gain mode inverts the reference voltage
with respect to analog ground and forces in onto the other
end of the resistor string. Both reference amplifiers are offset
trimmed at the factory in order to increase the accuracy of
the HI-7151 and to simplify its usage.
T CONVERSION
CLOCK
TRACK & HOLD
COMPARATOR
AUTO-ZERO
(AZ)
SCA AUTO-ZERO
(SCAZ)
T + 1 CONVERSION
1
2
3
4
HOLD VIN(T)
SAMPLE
VIN (T)
CONVERT
UPPER
5 BITS
SAMPLE VIN (T)
5
6
TRACK VIN(T + 1)
SAMPLE RESIDUAL
AMPLIFY RESIDUAL
INTERNAL DATA
10-BITS + OVR
HOLD VIN(T + 1)
CONVERT
LOWER
5 BITS
SAMPLE
VIN(T + 1)
SAMPLE VIN (T + 1)
VIN(T) DATA
FIGURE 3. INTERNAL ADC TIMING DIAGRAM
10
HI-7151
TABLE 1. A/D OUTPUT CODE TABLE
ANALOG INPUT
LSB = 2 (VREF) / 1024
OVR
SIGN 9
MSB 8
7
6
5
4
3
2
1
LSB 0
2.500V to V+ (+OVR)
1
0
0
0
0
0
0
0
0
0
0
+VREF - 1 LSB
2.49512V (+Full Scale)
0
0
1
1
1
1
1
1
1
1
1
+1 LSB
0.00488V
0
0
0
0
0
0
0
0
0
0
1
0.000V
0
0
0
0
0
0
0
0
0
0
0
-1 LSB
-0.00488V
0
1
1
1
1
1
1
1
1
1
1
-VREF
-2.500V (-Full Scale)
0
1
0
0
0
0
0
0
0
0
0
-2.50488V to V- (-OVR)
1
1
0
0
0
0
0
0
0
0
0
≥ +VREF
0
≤ -VREF - 1 LSB
VREF = 2.500V
OUTPUT DATA
Track and Hold Analog Input
All of the internal amplifiers are offset trimmed at the factory
to give improved accuracy and to minimize the number of
external components. If necessary, offset error can be
adjusted either at an external interface buffer or by using
digital post correction.
A Track and Hold amplifier has been fully integrated on the
front end of the A/D converter. Because of the sampling
nature of this A/D converter, the input is required to stay
constant only during the first clock cycle. Therefore, the
Track and Hold (T/H) amplifier “holds” the input voltage only
during the first clock cycle and it acquires the input voltage
for the next conversion during the remaining two clock
cycles. The high input impedance of the T/H input amplifier
simplifies analog interfacing. Input signals up to ±VREF can
be directly connected to the A/D without buffering. The A/D
output code table is shown in Table 1.
Reference Input
The reference input to the HI-7151 is buffered by a high
speed CMOS amplifier. The reference input range is 2.2V to
2.6V.
Power Requirements
The timing signals for the Track and Hold amplifier are
generated internally, and are also provided externally
(HOLD) for synchronization purposes. The T/H amplifier
consists of two high speed CMOS amplifiers and an internal
hold capacitor. Its typical slew rate and bandwidth are 9V/µs
and 1.5MHz respectively. It is configured to give a very small
hold pedestal without the use of an external hold capacitor.
The hold pedestal is typically less than 100µV.
Power to the chip should be applied in the following order:
V-, V+, and VREF . In applications where V+ is supplied prior
to V-, the positive supply current will be approximately 2
times its nominal value until V- is applied (this is not a
latchup condition).
Initialization
Acquisition of the analog input signal is the time required by
the T/H for its output to reach its final value within a specified
error band. This time is a function of the logic delay time, op
amp slewing time, and settling time. The T/H is in the track
mode for 2 clock cycles (6.7µs at CLK = 300kHz) but the output typically settles to within 1/4 LSB in 1.5µs.
In fast memory and DMA modes (after proper power, VREF ,
and clock) up to 6 clock cycles are required for circuit initialization. After circuit initialization, valid data will be available
in 3 clock cycles.
Aperture delay time is the time required for the T/H switch to
open following the internal hold command. This is the delay
with respect to falling edge of WR and the internal hold
command. It is equal to Thold (type) - 50ns (typ) which is
typically 30ns.
The HI-7151 can be interfaced to microprocessors through
the use of standard Write, Read, Chip Select, and HBE
control pins. The digital outputs are two’s complement
coded, three-state gated, and byte organized for bus
interface with 8- and 16-bit systems. The digital outputs (D0 D9, OVR, and BUSY) may be accessed under control of
BUS, byte enable input HBE, chip select, and read inputs for
a simple parallel bus interface. The microprocessor can read
the current data in the output latches in typically 75ns/byte
(trd). An over range pin (OVR) together with the MSB (D9)
pin set to either a logic 0 or 1 will indicate a positive or
negative over-range condition respectively. All digital output
buffers are capable of driving one TTL load.
Microprocessor Interface
Aperture uncertainty (jitter) is a range of variation in the
aperture time. The greater the aperture time the larger the
uncertainty in the analog voltage being converted. If the
aperture time is nulled out by advancing the hold command
(WR) or the signal is repetitively sampled, aperture uncertainty becomes the major source of time error. The aperture
uncertainty for the T/H is typically 2ns which sets the maximum input bandwidth to 77.7kHz for 1 LSB resolution.
fMAX = 1/(π X 2n X ta),
where n = resolution in bits,
ta = aperture uncertainty
The HI-7151 can be interfaced to a microprocessor using
one of three modes: slow memory, fast memory, and DMA
mode.
11
HI-7151
Slow Memory Mode
TABLE 3. FAST MEMORY MODE I/O TRUTH TABLE
(SMODE = DG)
In slow memory mode, the conversion will be initiated by the
microprocessor by selecting the chip (CS) and pulsing WR
low. This mode is selected by hardwiring the SMODE pin to
V+. This mode is intended for use with microprocessors
(such as the 8086) which can be forced into a WAIT state.
For example, in configuration where the BUSY output is tied
to the 8086 READY input, an attempt to read the data before
the conversion is complete will force the processor into a
WAIT state until BUSY goes high, at which time the data at
the output is valid. This resembles a 10µs access time RAM.
It allows the processor to initiate a conversion, WAIT, and
READ data with a single READ instruction. When the 8-bit
bus operation is selected, high and low byte data may be
accessed in either order. An I/O truth table is presented in
Table 2 for the slow memory mode of operation.
TABLE 2. SLOW MEMORY MODE I/O TRUTH TABLE
(SMODE = V+)
CS
WR
RD
0
0
X
X
X
Initiates a Conversion
1
X
X
X
X
Disables All Chip Commands
0
X
0
1
X
D0 - D9 and OVR Enabled
0
X
0
0
0
Low Byte Enabled: D0 - D7.
0
X
0
0
1
High Byte Enabled: D8 - D9,
OVR
X
X
1
X
X
Disables All Outputs
(High Impedance)
BUS HBE
CS
WR
RD
X
0
X
X
X
Continuous Conversion, WR
May Be Tied to DG
1
X
X
X
X
Disables Only The RD
Command
0
X
0
1
X
D0 - D9 & OVR Enabled
0
X
0
0
1
High Byte Enabled: D8 - D9,
OVR (Enable 1st)
0
X
0
0
0
Low Byte Enabled: D0 - D7
(Must Enable 2nd)
X
X
1
X
X
Disables All Outputs
(High Impedance)
BUS HBE
FUNCTION
NOTE: X = Don’t Care
DMA Mode
FUNCTION
This mode is a complete hardware mode where the HI-7151
continuously converts. The user implements hardware to
store the results in memory, bypassing the microprocessor.
This mode is recognized by the chip when SMODE is
hardwired to V+ and CS, RD, WR are hardwired to DG.
When 8-bit bus operation is selected, high and low byte data
may be accessed in either order. BUSY is continuously low
when accessed with a read command in this mode. An I/O
truth table is presented in Table 4 for the DMA mode of
operation.
TABLE 4. DMA MODE I/O TRUTH TABLE
(SMODE = V+, CS = WR, RD = DG)
NOTE: X = Don’t Care
Fast Memory Mode
The fast memory mode of operation is selected by tying the
SMODE and WR pins to DG. In this mode, the chip performs
continuous conversions and only CS and RD are required to
read the data. Whenever the SMODE pin is low, WR is
independent of CS in starting a conversion cycle. During the
first conversion cycle, HOLD follows WR going low.
BUS
HBE
FUNCTION
1
X
D0 - D9 and OVR Enabled
0
0
Low Byte Enabled: D0 - D7
0
1
High Byte Enabled: D8 - D9, OVR
NOTE: X = Don’t Care
Optimizing System Performance
Data can be read a byte at a time or all 11 bits at once. The
internal logic disables the output latches from being updated
during a read after the high byte data is accessed. It will
continue to be disabled until after the low byte data is
accessed. THEREFORE, WHEN 8-BIT BUS OPERATION
IS SELECTED, THE DATA MUST BE ACCESSED HIGH
BYTE FIRST, LOW BYTE NEXT. If the low byte is accessed
first followed by high byte, the results from the next conversion cycle will be lost because the updating of the output
latch is disabled. BUSY is continuously low when accessed
with a read command in this mode. An I/O truth table is presented in Table 3 for the fast memory mode of operation.
The HI-7151 has three ground pins (AG, DG, GND) for
improved system accuracy. Proper grounding and bypassing
is illustrated in Figure 4. The AG pin is a ground pin that
does not carry any current and is used internally as a reference ground. The reference input and analog input should
be referenced to the analog ground (AG) pin. The digital
inputs and outputs should be referenced to the digital ground
(DG) pin. The GND pin is a return point for the supply current
of the comparator array. The comparator array is designed
such that this current is approximately constant at all times
and does not vary with input voltage. By virtue of the
switched capacitor nature of the comparators, it is necessary
to hold GND firmly at zero volts at all times. Therefore, the
system ground star connection should be located as close to
this pin as possible.
The data can be defined in time by monitoring the HOLD pin.
The conversion data can be read after HOLD has gone low.
12
HI-7151
Figure 8 illustrates an application where the HI-7151 is used
with an analog multiplexer to form a multi-channel data
acquisition system. Either slow memory or fast memory
modes of operation can be selected. Fast memory mode
should be selected for maximum throughput. Multiplexer
channel acquisition should occur approximately 500ns after
HOLD goes high. This allows 2 clocks minus 0.5µs for the
input to settle. With a 300kHz clock the input has up to 6.2µs
to settle.
As in any analog system, good supply bypassing is
necessary in order to achieve optimum system performance
(minimize conversion errors). The power supplies should be
bypassed with at least a 20µF tantalum and 0.1µF ceramic
capacitors to GND. The reference input should be bypassed
with a 0.1µF ceramic capacitor to AG. The capacitor leads
should be as short as possible.
The pins on the HI-7151 are arranged such that the analog
pins are well isolated from the digital pins. In spite of this
arrangement, there is always pin to pin coupling. Therefore
the analog inputs to the device should not be driven from
very high output impedance sources. PC board layout
should screen the analog and reference inputs with AG.
Using a soldier mask is good practice and helps reduce
leakage due to moisture contamination on the PC board.
An intelligent system which performs a scale factor
adjustment under software control with the addition of a
programmable gain block between the multiplexer and
HI-7151 is illustrated in Figure 9. The microprocessor first
performs a conversion and then checks the over-range
status (OVR) bit. If the OVR bit is high, the microprocessor
addresses a precision gain circuit for scale factor adjustment
and initiates another conversion. The microprocessor must
keep track of the selected scale factor.
Applications
Typical applications are illustrated in Figures 5 through 7 for
the slow memory, fast memory, and DMA modes of
operation. The output data is configured for 16-bit bus operation of these three applications. By tying BUS and DG and
connecting the HBE input to the system address decoder,
the output data can be configured for 8-bit bus systems.
The accuracy of the programmable gain amplifier should be
better than 0.05%. For optimum system performance, op
amp frequency response, settling time, and charge injection
of the analog switch must be considered.
Figure 10 illustrates the HI-7151 interfaced to FIFO
memories for use in DMA applications.
20µF
0.1µF
+
+
2.5V
P.S.
-5V
P.S.
-
-
+
HI-7151
0.1µF
1 GND
20µF
2 V-
0.1µF
ANALOG INPUT
V+
V+ 28
OVR 27
3 VREF
D9 26
4 AG
D8 25
5 VIN
D7 24
6 SET
D6 23
7 BUSY
D5 22
8 CLK
D4 21
9 HOLD
D3 20
10 WR
D2 19
11 CS
D1 18
12 RD
D0 17
13 SMODE
HBE 16
14 DG
BUS 15
FIGURE 4. GROUND AND POWER SUPPLY DECOUPLING
13
5V
P.S.
HI-7151
HI-7151
2 V-
-5V
+5V
V+ 28
OVR 27
3 VREF
D9 26
0V
4 AG
D8 25
ANALOG INPUT
5 VIN
D7 24
6 SET
D6 23
7 BUSY
D5 22
8 CLK
D4 21
9 HOLD
D3 20
+2.56V
V+
300kHz CLOCK
10 WR
D2 19
11 CS
D1 18
12 RD
D0 17
13 SMODE
HBE 16
14 DG
BUS 15
CS
WR
HOLD TRACK N
HOLD N
TRACK N+1
INTERNAL
DATA
N DATA
RD
BUSY
D0-D9, OVR
DATA
N DATA
FIGURE 5. SLOW MEMORY MODE APPLICATION
14
16-BIT DATA BUS
ADDRESS BUS
READY
WR LINE
RD LINE
1 GND
HI-7151
HI-7151
OVR 27
3 VREF
D9 26
0V
4 AG
D8 25
ANALOG INPUT
5 VIN
D7 24
6 SET
D6 23
7 BUSY
D5 22
8 CLK
D4 21
9 HOLD
D3 20
+2.56V
V+
300kHz CLOCK
10 WR
D2 19
11 CS
D1 18
12 RD
D0 17
13 SMODE
HBE 16
14 DG
BUS 15
DATA
CS
WR
HOLD
+5V
V+ 28
16-BIT DATA BUS
2 V-
-5V
ADDRESS BUS
RD LINE
1 GND
(WR MAY BE WIRED LOW)
TRACK N
HOLD N
HOLD N+1
TRACK N+1
INTERNAL
DATA
TRACK N+2
N DATA
HOLD N+2
N+1 DATA
RD
D0-D9, OVR
DATA
N DATA
BUSY
FIGURE 6. FAST MEMORY MODE APPLICATION
15
TRACK N+3
N+1 DATA
HI-7151
HI-7151
+5V
1 GND
OVR 27
3 VREF
D9 26
0V
4 AG
D8 25
ANALOG INPUT
5 VIN
D7 24
6 SET
D6 23
7 BUSY
D5 22
8 CLK
D4 21
9 HOLD
D3 20
+2.56V
V+
300kHz CLOCK
V+
TRACK N
HOLD
V+ 28
2 V-
HOLD N
INTERNAL
DATA
D0-D9, OVR
10 WR
D2 19
11 CS
D1 18
12 RD
D0 17
13 SMODE
HBE 16
14 DG
BUS 15
TRACK N+1
16-BIT DATA BUS
-5V
HOLD N+1
N-1 DATA
TRACK N+2
HOLD N+2
N DATA
N+1 DATA
10µs
FIGURE 7. DMA MODE APPLICATION
ADDRESS BUS
ADDRESS
DECODER
ANALOG
INPUTS
S1
S2
S3
S4
S5
S6
S7
S8
HBE
VIN
WR
DG528
MUX
ADDRESS
DECODER
DG
BUS
V+
VDG
RS SYSTEM
RESET
A0-A2, EN
+2.56V
+5V
-5V
RD
VREF
AG
SIGNAL
GROUND
CS
V+
HI-7151
ADC
(SLOW MEMORY MODE)
WR
SMOD
HOLD
MICROPROCESSOR
V+
BUSY
VDG
CLK
GND
SET
D0-D7
D8-D9, OVR
8-BIT DATA BUS
FIGURE 8. MULTI-CHANNEL DATA ACQUISITION SYSTEM
16
300kHz
CLOCK
V+
ADDRESS BUS
ADDRESS
DECODER
ANALOG
INPUTS
S1
S2
S3
S4
S5
S6
S7
S8
D
DG528
MUX
V+
VDG
HBE
BUS
CS
WR
ADDRESS
DECODER
DG
VIN
PROGRAMMBLE
GAIN AMP
+2.56V
RD
VREF
AG
SIGNAL
GROUND
V+
+5V
RS SYSTEM
RESET
CS
HI-7151
ADC
(SLOW MEMORY MODE)
SMOD
HOLD
DG
CLK
GND
SET
D0-D2, EN
MICROPROCESSOR
V+
BUSY
V-
-5V
WR
D0-D7
300kHz
CLOCK
V+
D8-D9, OVR
8-BIT DATA BUS
FIGURE 9. MULTI-CHANNEL DATA ACQUISITION SYSTEM WITH PROGRAMMABLE GAIN
V+
ANALOG INPUT
+2.56V
VREF
AG
SIGNAL
GROUND
+5V
-5V
BUS
HBE
SMODE
D8-D9, OVR
VIN
V+
VDG
GND
HI-7151
ADC
SET
CLK
HOLD
V+
300kHz
BUSY
RD
WR
CS
D0-D3
64 x 4-BIT
FIFO
D4-D7
64 x 4-BIT
FIFO
D8-D9, OVR
64 x 4-BIT
FIFO
SHIFT IN
DG
FIGURE 10. DMA/FIFO DATA ACQUISITION SYSTEM
17
TO PARALLEL
DATA BUS
COMPOSITE
OUTPUT
READY
SHIFT
OUT
Similar pages