DATASHEET HI-DAC80V FN3110 Rev 2.00 March 2001 12-Bit, Low Cost, Monolithic D/A Converter The Hl-DAC80V is a monolithic direct replacement for the popular DAC80 and AD DAC80. Single chip construction along with several design innovations make the Hl-DAC80V the optimum choice for low cost, high reliability applications. Intersil’ unique Dielectric Isolation (Dl) processing reduces internal parasitics resulting in fast switching times and minimum glitch. On board span resistors are provided for good tracking over temperature, and are laser trimmed to high accuracy. Internally the Hl-DAC80V eliminates code dependent ground currents by routing current from the positive supply to the internal ground node, as determined by an auxiliary R2R ladder. This results in a cancellation of code dependent ground currents allowing virtually zero variation in current through the package common, pin 21. The Hl-DAC80V is available as a voltage output device which is guaranteed over the 0oC to 75oC temperature range. It includes a buried zener reference featuring a low temperature coefficient as well as an on board operational amplifier. The Hl-DAC80V requires only two power supplies and will operate in the range of (11.4V to 16.5V). Features • DAC 80V Alternative Source • Monolithic Construction • Fast Settling Time (Typ) . . . . . . . . . . . . . . . . . . . . . . 1.5s • Guaranteed Monotonicity • Wafer Laser Trimmed Linearity, Gain, Offset • Span Resistors On-Chip • On-Board Reference • Supply Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V Applications • High Speed A/D Converters • Precision Instrumentation • CRT Display Generation Pinout HI-DAC80V (PDIP) TOP VIEW Ordering Information PART NUMBER TEMP. RANGE (oC) HI3-DAC80V-5 FN3110 Rev 2.00 March 2001 0 to 75 PACKAGE 24 Ld PDIP PKG. NO. E24.6 (MSB) BIT 1 1 24 6.3V REF OUT BIT 2 2 23 GAIN ADJUST BIT 3 3 22 +VS BIT 4 4 21 COMMON BIT 5 5 20 Â JUNCTION BIT 6 6 19 20V RANGE BIT 7 7 18 10V RANGE BIT 8 8 17 BIPOLAR OFFSET BIT 9 9 16 REF INPUT BIT 10 10 15 VOUT BIT 11 11 14 -VS (LSB) BIT 12 12 13 NC Page 1 of 8 HI-DAC80V Functional Block Diagram BIPOLAR OFFSET REF IN OUT COMMON +VS BIT 1 IN (MSB) 20V 5K SPAN R GROUND CURRENT CANCELLATION CIRCUIT 6.3K 10V SPAN R BIT 12 IN (LSB) DIGITAL INPUT LEVEL SHIFTERS AND SWITCH DRIVERS 5K 12.6K + 2K 2K 2K 2K 2K 2K 2K 2K 2K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K SPAN JUNCTION - - + VOUT CONTROL AMP + - 12.6K GAIN ADJUST FN3110 Rev 2.00 March 2001 8K 8K 8K 8K 8K 8K 8K 8K 8K 8K 8K 8K 8K 8K -VS Page 2 of 8 HI-DAC80V Absolute Maximum Ratings Thermal Information Power Supply Inputs +VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+20V -VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20V Reference Input (Pin 16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +VS Output Drain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5mA Digital Inputs (Bits 1 to 12) . . . . . . . . . . . . . . . . . . . . . . . . -1V to +VS Thermal Resistance (Typical, Note 1) JA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Maximum Power Dissipation PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550mW Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC Die Characteristics Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bipolar-DI Transistor Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications PARAMETER TA = 25oC, VS ±12V to 15V (Note 5), Pin 16 Shorted to Pin 24, Unless Otherwise Specified TEST CONDITIONS MIN TYP MAX UNITS - - 12 Bits SYSTEM PERFORMANCE Resolution ACCURACY (Note 3) Linear Error Full Temperature - 1/4 1/2 LSB Differential Linearity Error Full Temperature - 1/2 3/4 LSB Monotonicity Full Temperature Gain Error Full Temperature (Notes 2, 4) 0.1 0.3 % FSR Offset Error Full Temperature (Note 2) 0.05 0.15 % FSR - 2.5 - V - 5 - V - 10 - V - 0 to 5 - V - 0 to 10 - V 5 - - mA - 0.05 - Guaranteed - ANALOG OUTPUT Output Ranges (See Figure 2 and Table 2) Output Current Output Resistance Short Circuit Duration To Common Continuous - DRIFT (Note 3) Full Temperature - - 20 ppm/oC Unipolar Full Temperature (Note 6) - 0.08 0.15 % FSR Bipolar Full Temperature (Note 6) - 0.06 0.1 % FSR With Internal Reference - 15 30 ppm/oC Without Internal Reference - 7 - ppm/oC Total Bipolar Drift (Includes Gain, Offset and Linearity Drifts) Total Error Gain FN3110 Rev 2.00 March 2001 Page 3 of 8 HI-DAC80V Electrical Specifications TA = 25oC, VS ±12V to 15V (Note 5), Pin 16 Shorted to Pin 24, Unless Otherwise Specified (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Unipolar Offset - 1 3 ppm/oC Bipolar Offset - 5 10 ppm/oC - 3 - s With 5K Feedback - 1.5 - s For 1 LSB Change - 1.5 - s 10 15 - V/s 6.250 +6.3 6.350 V Output Impedance - 1.5 - External Current - - +2.5 mA Tempco of Drift - 5 - ppm/oC CONVERSION SPEED Settling Time With 10K Feedback Full Scale Transition All Bits ON to OFF or OFF to ON to 0.01% or FSR (Note 3) Slew Rate INTERNAL REFERENCE Output Voltage DIGITAL INPUT (Note 2) Logic Levels Logic “1” TTL Compatible At +1A +2 - +5.5 V Logic “0” TTL Compatible At -100A 0 - +0.8 V +15V Supply - 0.001 0.002 % FSR / %VS -15V Supply - 0.001 0.002 % FSR / %VS POWER SUPPLY SENSITIVITY (Notes 3, 5) POWER SUPPLY CHARACTERISTICS (Note 5) Voltage Range +VS Full Temperature +11.4 +15 +16.5 V -VS Full Temperature -11.4 -15 -16.5 V Current +IS Full Temperature, VS = 15V - +12 +15 mA -IS Full Temperature, VS = 15V - -15 -20 mA NOTES: 2. Adjustable to zero using external potentiometers. 3. See Definitions. 4. FSR is “Full Scale Range: and is 20V for 10V range, 10V for 5V range, etc. 5. The HI-DAC80V will operate with supply voltages as low as 11.4V. It is recommended that output voltage range -10V to +10V not be used if the supply voltages are less than 12.5V. 6. With Gain and Offset errors adjusted to zero at 25oC. FN3110 Rev 2.00 March 2001 Page 4 of 8 HI-DAC80V Definitions of Specifications Digital Inputs The Hl-DAC80V accepts digital input codes in complementary binary, complementary offset binary, and complementary two’s complement binary. Settling Time That interval between application of a digital step input, and final entry of the analog output within a specified window about the settled value. Intersil Corporation usually specifies a unipolar 10V full scale step, to be measured from 50% of the input digital transition, and a window of 1/2 LSB about the final value. The device output is then rated according to the worst (longest settling) case: low to high, or high to low. In a 12-bit system 1/2 LSB = 0.012% of FSR. TABLE 1. ANALOG OUTPUT COMPLEMENTARY STRAIGHT BINARY COMPLEMENTARY OFFSET BINARY COMPLEMENTARY TWO’S COMPLEMENT † 000...000 + Full Scale + Full Scale -LSB 100...000 Mid Scale-1 LSB -1 LSB + Full Scale 111...111 Zero - Full Scale Zero 011...111 +1/2 Full Scale Zero - Full Scale DIGITAL INPUT MSB...LSB † Invert MSB with external inverter to obtain CTC Coding. Thermal Drift Thermal drift is based on measurements at 25oC, at high (TH) and low (TL) temperatures. Drift calculations are made for the high (TH -25oC) and low (25oC-TL) ranges, and the larger of the two values is given as a specification representing worst case drift. Gain Drift, Offset Drift, Reference Drift and Total Bipolar Drift are calculated in parts per million per oC as follows: 6 FSR C GainDrift = -------------------------------- 10 FSR 6 Offset C OffsetDrift = ------------------------------------- 10 FSR V REF C ReferenceDrift = --------------------------------------- 10 6 V REF V O C 6 TotalBipolarDrift = -------------------------------- 10 FSR NOTE: FSR = Full Scale Output Voltage - Zero Scale Output Voltage. FSR = FSR (TH) - FSR (25oC), or FSR (25oC) - FSR (TL). VO = Steady State response to any input code. FN3110 Rev 2.00 March 2001 Total Bipolar Drift (TBD) is the variation of output voltage with temperature, in the bipolar mode of operation. It represents the net effect of drift in Gain, Offset, Linearity and Reference Voltage. Total Bipolar Drift values are calculated, based on measurements as explained above. Gain and Offset need not be calibrated to zero at 25oC. The specified limits for TBD apply for any input code and for any power supply setting within the specified operating range. Accuracy Linearity Error (Short for “Integral Linearity Error.” Also, sometimes called “Integral Nonlinearity” and “Nonlinearity”.) The maximum deviation of the actual transfer characteristic from an ideal straight line. The ideal line is positioned according to end-point linearity for D/A converter products from Intersil Corporation, i.e., the line is drawn between the endpoints of the actual transfer characteristic (codes 00...0 and 11...1). Differential Linearity Error The difference between one LSB and the output voltage change corresponding to any two consecutive codes. A Differential Nonlinearity of 1 LSB or less guarantees monotonicity. Monotonicity The property of a D/A converter’s transfer function which guarantees that the output derivative will not change sign in response to a sequence of increasing (or decreasing) input codes. That is, the only output response to a code change is to remain constant, increase for Increasing code, or decrease for decreasing code. Total Error The net output error resulting from all internal effects (primarily non-ideal Gain, Offset, Linearity and Reference Voltage). Supply voltages may be set to any values within the specified operating range. Gain and offset errors must be calibrated to zero at 25oC. Then the specified limits for Total Error apply for any input code and for any temperature within the specified operating range. Power Supply Sensitivity Power Supply Sensitivity is a measure of the change in gain and offset of the D/A converter resulting from a change in -VS , or +VS supplies. It is specified under DC conditions and expressed as full scale range percent of change divided by power supply percent change. FullScaleRange 100 ------------------------------------------------------------------FSR Nominal PSS = ------------------------------------------------------------------V S 100 ---------------------------------V S (Nominal) Glitch A glitch on the output of a D/A converter is a transient spike resulting from unequal internal ON-OFF switching times. Worst case glitches usually occur at half-scale, i.e., the major carry code transition from 011...1 to 100...0 or vice versa. For example, if turn ON is greater than OFF for 011...1 to 100...0, an intermediate state of 000...0 exists, such that, the output momentarily glitches toward zero output. Matched switching Page 5 of 8 HI-DAC80V times and fast switching will reduce glitches considerably. (Measured as one half the Product of duration and amplitude.) Output Voltage Ranges 24 Decoupling and Grounding For best accuracy and high frequency performance, the grounding and decoupling scheme shown in Figure 1 should be used. Decoupling capacitors should be connected close to the HI-DAC80V (preferably to the device pins) and should be tantalum or electrolytic bypassed with ceramic types for best high frequency noise rejection. -VS 0.01F +VS 1F 19 5k 3.9 M 20 16 12.6k R2 15 - + 23 -VS 5k TO 100k 21 CONTROL AMP 2.8M -VS 10k TO 100k 1F 5k + 6.3K R1 0.01F - 17 +VS +VS 18 0.01F FIGURE 2. HI-DAC80V 14 21 22 18 TABLE 2. RANGE CONNECTIONS 19 CONNECT 24 20 16 - 15 Unipolar Bipolar + RANGE PIN 15 PIN 17 0 to +5V 18 NC PIN 19 20 0 to +10V 18 NC NC 2.5V 18 20 20 5V 18 20 NC 10V 19 20 15 TABLE 3. GAIN AND OFFSET CALIBRATIONS FIGURE 1. UNIPOLAR CALIBRATION Step 1: Offset Turn all bits OFF (11 . . . 1) Adjust R2 for 0V out Step 2: Gain Turn all bits ON (00 . . . 0) Adjust R1 for FS - 1 LSB That is: 4.9988 for 0 to +5V range 9.9976 for 0 to +10V range Reference Supply An internal 6.3V reference is provided on board the HI-DAC80V. The voltage (pin 24) is accurate to 0.8% and must be connected to the reference input (pin 16) for specified operation. This reference may be used externally, provided current drain is limited to 2.5mA. An external buffer amplifier is recommended if this reference is to be used to drive other system components. Otherwise, variations in the load driven by the reference will result in gain variations of the HI-DAC80V. All gain adjustments should be made under constant load conditions. BIPOLAR CALIBRATION Step 1: Offset Turn all bits OFF (11 . . . 1) Adjust R2 for Negative FS That is: -10V for 10V range -5V for 5V range -2.5V for 2.5V range Step 2: Gain Turn all bits ON (00 . . . 0) Adjust R1 for Positive FS - 1 LSB That is: +9.9951V for 10V Range +4.9976V for 5V Range +2.4988V for 2.5V Range This Bipolar procedure adjusts the output range end points. The maximum error at zero (half scale) will not exceed the Linearity Error. See the “Accuracy” Specifications. FN3110 Rev 2.00 March 2001 Page 6 of 8 HI-DAC80V Die Characteristics DIE DIMENSIONS TIE SUBSTRATE TO 108 mils x 163 mils Ground METALLIZATION PASSIVATION Type: Al Thickness: 16kÅ 2kÅ Type: Nitride over Silox Nitride Thickness: 3.5kÅ 0.5kÅ Silox Thickness: 12kÅ 1.5kÅ Metallization Mask Layout HI-DAC80V BIT 3 BIT 2 BIT 1 (MSB) 6.3V REF OUT GAIN ADJUST +VS COMMON BIT 4 SUMMING JUNCTION BIT 5 20V SPAN BIT 6 10V SPAN BIT 7 BIPOLAR OFFSET BIT 8 BIT 9 REF IN BIT 10 BIT 11 FN3110 Rev 2.00 March 2001 BIT 12 -VS VOUT Page 7 of 8 HI-DAC80V Dual-In-Line Plastic Packages (PDIP) E24.6 (JEDEC MS-011-AA ISSUE B) N 24 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 SYMBOL -B- -C- SEATING PLANE A2 e B1 D1 A1 eC B 0.010 (0.25) M C A B S MAX - 0.250 - - 0.39 A2 0.125 0.195 3.18 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.030 0.070 0.77 1.77 8 eA C 0.008 0.015 0.204 0.381 - D 1.150 1.290 D1 0.005 - C eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 6.35 NOTES 0.015 A L D1 MIN A E BASE PLANE MAX A1 -AD MILLIMETERS MIN 29.3 - 4 4 32.7 5 - 5 0.13 E 0.600 0.625 15.24 15.87 6 E1 0.485 0.580 12.32 14.73 5 e 0.100 BSC 2.54 BSC - eA 0.600 BSC 15.24 BSC 6 eB - 0.700 - 17.78 7 L 0.115 0.200 2.93 5.08 4 N 24 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 24 9 Rev. 0 12/93 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). © Copyright Intersil Americas LLC 2001. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN3110 Rev 2.00 March 2001 Page 8 of 8