HM-6504/883 4096 x 1 CMOS RAM March 1997 Features Description • This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. The HM-6504/883 is a 4096 x 1 static CMOS RAM fabricated using self-aligned silicon gate technology. The device utilizes synchronous circuitry to achieve high performance and low power operation. • Low Power Standby . . . . . . . . . . . . . . . . . . . 125µW Max • Low Power Operation . . . . . . . . . . . . . 35mW/MHz Max • Data Retention . . . . . . . . . . . . . . . . . . . . . . . at 2.0V Min • TTL Compatible Input/Output • Three-State Output • Standard JEDEC Pinout • Fast Access Time. . . . . . . . . . . . . . . . . . 120/200ns Max On-chip latches are provided for addresses, data input and data output allowing efficient interfacing with microprocessor systems. The data output can be forced to a high impedance state for use in expanded memory arrays. Gated inputs allow lower operating current and also eliminate the need for pull up or pull down resistors. The HM-6504/883 is a fully static RAM and may be maintained in any state for an indefinite period of time. Data retention supply voltage and supply current are guaranteed over temperature. • 18 Pin Package for High Density • On-Chip Address Register • Gated Inputs - No Pull Up or Pull Down Resistors Required Ordering Information PACKAGE CERDIP TEMPERATURE RANGE -55oC to +125oC 200ns 300ns HM1-6504B/883 HM1-6504/883 PKG. NO F18.3 Pinout HM-6504/883 (CERDIP) TOP VIEW A0 1 18 VCC A1 2 17 A6 A2 3 16 A7 A3 4 15 A8 A4 5 14 A9 A5 6 13 A10 Q 7 12 A11 W 8 11 D GND 9 10 E PIN DESCRIPTION A Address Input E Chip Enable W Write Enable D Data Input Q Data Output CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 6-134 File Number 2993.1 HM-6504/883 Functional Diagram LSB A8 A7 A6 A0 A1 A2 A 6 LATCHED ADDRESS REGISTER GATED ROW DECODER A 6 L 64 x 64 MATRIX 64 G 64 G D D W D LATCH LATCH L Q A GATED COLUMN DECODER AND DATA I/O Q L E D L LATCH D L Q 6 6 A A LATCHED ADDRESS REGISTER LSB A11 A5 A4 A3 A9 A10 NOTES: 1. All lines active high-positive logic. 2. Three-state Buffers: A high → output active. 3. Control and Data Latches: L low → Q = D and Q latches on rising edge of L. 4. Address Latches: Latch on falling edge of E. 5. Gated Decoders: Gate on rising edge of G. 6-135 LATCH L Q Q A HM-6504/883 Absolute Maximum Ratings Thermal Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Resistance θJA θJC CERDIP Package . . . . . . . . . . . . . . . . 75oC/W 15oC/W Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +175oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300oC Die Characteristics Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6910 Gates CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Operating Conditions Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +0.8V Input High Voltage . . . . . . . . . . . . . . . . . . . VCC -2.0V to VCC +0.3V TABLE 1. HM-6504/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested LIMITS PARAMETER SYMBOL (NOTE 1) CONDITIONS GROUP A SUBGROUPS TEMPERATURE MIN MAX UNITS Output Low Voltage VOL VCC = 4.5V, IOL = 2mA 1, 2, 3 -55oC ≤ TA ≤ +125oC - 0.4 V Output High Voltage VOH VCC = 4.5V, IOH = -1.0mA 1, 2, 3 -55oC ≤ TA ≤ +125oC 2.4 - V II VCC = 5.5V, VI = GND or VCC 1, 2, 3 -55oC ≤ TA ≤ +125oC -1.0 +1.0 µA IOZ VCC = 5.5V, VO = GND or VCC 1, 2, 3 -55oC ≤ TA ≤ +125oC -1.0 +1.0 µA VCC = 2.0V, E = VCC, IO = 0mA 1, 2, 3 -55oC ≤ TA ≤ +125oC - 25 µA Input Leakage Current Output Leakage Current Data Retention Supply Current ICCDR Operating Supply Current ICCOP VCC = 5.5V, (Note 2), E = 1MHz, IO = 0mA 1, 2, 3 -55oC ≤ TA ≤ +125oC - 7 mA Standby Supply Current ICCSB VCC = 5.0V, E = VCC -0.3V, IO = 0mA 1, 2, 3 -55oC ≤ TA ≤ +125oC - 50 µA NOTES: 1. All voltage referenced to device GND. 2. Typical derating 1.5mA/MHz increase in ICCOP. 6-136 HM-6504/883 TABLE 2. HM-6504/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested LIMITS PARAMETER SYMBOL (NOTES 1, 2) CONDITIONS GROUP A SUBGROUPS TEMPERATURE HM-6504S/883 HM-6504B/883 HM-6504/883 MIN MAX MIN MAX MIN MAX UNITS - 120 - 200 - 300 ns Chip Enable Access Time (1) TELQV VCC = 4.5 and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC Address Access Time (2) TAVQV VCC = 4.5 and 5.5V, Note 3 9, 10, 11 -55oC ≤ TA ≤ +125oC - 120 - 220 - 320 ns Chip Enable Pulse Negative Width (5) TELEH VCC = 4.5 and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 120 - 200 - 300 - ns Chip Enable Pulse Positive Width (6) TEHEL VCC = 4.5 and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 50 - 90 - 120 - ns Address Setup Time (7) TAVEL VCC = 4.5 and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 0 - 20 - 20 - ns Address Hold Time (8) TELAX VCC = 4.5 and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 40 - 50 - 50 - ns Write Enable Pulse Width (9) TWLWH VCC = 4.5 and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 20 - 60 - 80 - ns Write Enable Pulse Setup Time (10) TWLEH VCC = 4.5 and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 70 - 150 - 200 - ns Early Write Pulse Setup Time (11) TWLEL VCC = 4.5 and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 0 - 0 - 0 - ns Early Write Pulse Hold Time (13) TELWH VCC = 4.5 and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 40 - 60 - 80 - ns Data Setup Time (14) TDVWL VCC = 4.5 and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 0 - 0 - 0 - ns Early Write Data Setup Time (15) TDVEL VCC = 4.5 and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 0 - 0 - 0 - ns Data Hold Time (16) TWLDX VCC = 4.5 and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 25 - 60 - 80 - ns Early Write Data Hold Time (17) TELDX VCC = 4.5 and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 25 - 60 - 80 - ns Read or Write Cycle Time (18) TELEL VCC = 4.5 and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 170 - 290 - 420 - ns NOTES: 1. All voltages referenced to device GND. 2. Input pulse levels: 0.8V to VCC-2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1TTL gate equivalent, CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF. 3. TAVQV = TELQV + TAVEL. 6-137 HM-6504/883 TABLE 3. HM-6504/883 ELECTRICAL PERFORMANCE SPECIFICATIONS HM-6504S/883 LIMITS PARAMETER SYMBOL CONDITIONS NOTE TEMPERATURE MIN MAX UNITS Input Capacitance CI VCC = Open, f = 1MHz, All Measurements Referenced to Device Ground 1 TA = +25oC - 8 pF Output Capacitance CO VCC = Open, f = 1MHz, All Measurements Referenced to Device Ground 1 TA = +25oC - 10 pF Chip Enable Output Disable Time (3) TELQX VCC = 4.5 and 5.5V 1 -55oC ≤ TA ≤ +125oC 5 - ns Chip Enable Output Disable Time (4) TEHQZ VCC = 4.5 and 5.5V HM-6504S/883 1 -55oC ≤ TA ≤ +125oC - 50 ns VCC = 4.5 and 5.5V HM-6504B/883 1 -55oC ≤ TA ≤ +125oC - 80 ns VCC = 4.5 and 5.5V HM-6504/883 1 -55oC ≤ TA ≤ +125oC - 100 ns VCC = 4.5 and 5.5V 1 -55oC ≤ TA ≤ +125oC 0 - ns VCC = 4.5V, IO = -100µA 1 -55oC ≤ TA ≤ +125oC VCC 0.4 - V Write Enable Read Mode Setup Time (12) TWHEL High Level Output Voltage VOHL NOTE: 1. The parameters listed in Table 3 are controlled via design, or process parameters are characterized upon initial design and after major process and/or design changes. f TABLE 4. APPLICABLE SUBGROUPS CONFORMANCE GROUPS METHOD SUBGROUPS Initial Test 100%/5004 - Interim Test 100%/5004 1, 7, 9 PDA 100%/5004 1 Final Test 100%/5004 2, 3, 8A, 8B, 10, 11 Group A Samples/5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Groups C & D Samples/5005 1, 7, 9 6-138 HM-6504/883 Timing Waveforms (7) TAVEL (8) TELAX (7) TAVEL ADD VALID A NEXT ADD (6) TEHEL TELEH (5) TELEL (18) TEHEL (6) E (1) TELQV (3) TELQX HIGH Z Q (4) TEHQZ HIGH Z VALID DATA OUTPUT HIGH W TIME REFERENCE -1 0 1 2 3 4 5 FIGURE 1. READ CYCLE TRUTH TABLE INPUTS OUTPUT TIME REFERENCE E W A Q -1 H X X Z Memory Disabled H V Z Cycle Begins, Addresses are Latched 0 FUNCTION 1 L H X X Output Enabled 2 L H X V Output Valid H X V Read Accomplished X X Z Prepare for Next Cycle (Same as -1) H V Z Cycle Ends, Next Cycle Begins (Same as 0) 3 4 5 H The address information is latched in the on-chip registers on the falling edge of E (T = 0). Minimum address set up and hold time requirements must be met. After the required hold time, the addresses may change state without affecting device operation. During time (T = 1) the output becomes enabled but the data is not valid until during time (T = 2). W must remain high for the read cycle. After the output data has been read, E may return high (T = 3). This will disable the output buffer and all input, and ready the RAM for the next memory cycle (T = 4). 6-139 HM-6504/883 Timing Waveforms (Continued) (7) TAVEL (8) TELAX (7) TAVEL NEXT ADD ADD VALID A (18) TELEL (5) TELEH (6) TEHEL (6) TEHEL E (11) (13) TWLEL TELWH (11) TWLEL (17) TELDX (15) TDVEL W (15) TDVEL D NEXT DATA DATA VALID HIGH-Z HIGH-Z Q TIME REFERENCE -1 0 1 2 3 4 FIGURE 2. EARLY WRITE CYCLE TRUTH TABLE INPUTS OUTPUT TIME REFERENCE E W A D Q -1 H X X X Z Memory Disabled L V V Z Cycle Begins, Addresses are Latched X X X Z Write in Progress Internally X X X Z Write Completed X X X Z Prepare for Next Cycle (Same as -1) L V V Z Cycle Ends, Next Cycle Begins (Same as 0) 0 1 L 2 3 4 H The early write cycle is the only cycle where the output is guaranteed not to become active. On the falling edge of E (T = 0), the addresses, the write signal, and the data input are latched in on-chip registers. The logic value of W at the time E falls determines the state of the output buffer for that cycle. Since W is low when E falls, the output buffer is latched into the high impedance state and will remain in that FUNCTION state until E returns high (T = 2). For this cycle, the data input is latched by E going low; therefore, data set up and hold times should be referenced to E. When E (T = 2) returns to the high state, the output buffer and all inputs are disabled and all signals are unlatched. The device is now ready for the next cycle. 6-140 HM-6504/883 Timing Waveforms (Continued) (7) TAVEL (8) TELAX (7) TAVEL ADD VALID A NEXT ADD (18) TELEL (5) TELEH (6) TEHEL E (9) TWLWH (6) TEHEL (10) TWLEH W (16) TWLDX (14) TDVWL DATA VALID D (4) TEHQZ (3) TELQX HIGH Z HIGH Z Q TIME REFERENCE -1 0 1 2 3 4 5 FIGURE 3. LATE WRITE CYCLE TRUTH TABLE INPUTS OUTPUTS TIME REFERENCE E W A D Q -1 H X X X Z Memory Disabled H V X Z Cycle Begins, Addresses are Latched X V X Write Begins, Data is Latched H X X X Write In Progress Internally H X X X Write Completed X X X Z Prepare for Next Cycle (Same as -1) H V X Z Cycle Ends, Next Cycle Begins (Same as 0) 0 1 L 2 L 3 4 5 H The late write cycle is a cross between the early write cycle and the read-modify-write cycle. Recall that in the early write, the output is guaranteed to remain high impedance, and in the read-modify-write, the output is guaranteed valid at access time. The late write is FUNCTION between these two cases. With this cycle the output may become active, and may become valid data, or may remain active but undefined. Valid data is written into the RAM if data setup, data hold, write setup and write pulse widths are observed. 6-141 HM-6504/883 Test Load Circuit DUT (NOTE 1) CL + - IOH 1.5V IOL EQUIVALENT CIRCUIT NOTE: 1. Test head capacitance includes stray and jig capacitance. Burn-In Circuit HM-6504/883 CERDIP VCC C1 F3 1 A0 VCC 18 F4 2 A1 A6 17 F9 F5 3 A2 A7 16 F10 F6 4 A3 A8 15 F11 F7 5 A4 A9 14 F12 F8 6 A5 A10 13 F13 F2 7 Q A11 12 F14 F1 8 W D 11 F2 9 GND E 10 F0 NOTES: All resistors 47kΩ ±5%. F0 = 100kHz ±10%. F1 = F0 ÷ 2, F2 = F1 ÷ 2, F3 = F2 ÷ 2 . . . F12 = F11 ÷ 2. VCC = 5.5V ±0.5V. VIH = 4.5V ±10%. VIL = -0.2V to +0.4V. C1 = 0.01µF Min. 6-142 HM-6504/883 Die Characteristics DIE DIMENSIONS: 136 x 169 x 19 ±1mils WORST CASE CURRENT DENSITY: 1.79 x 105 A/cm2 METALLIZATION: Type: Si - Al Thickness: 11kÅ ±2kÅ LEAD TEMPERATURE (10s soldering): ≤ 300oC GLASSIVATION: Type: SiO2 Thickness: 8kÅ ±1kÅ Metallization Mask Layout HM-6504/883 A1 A0 VCC A6 A2 A7 A3 A8 A4 A9 A10 A5 A11 Q W GND E D NOTE: 1. Pin numbers correspond to DIP Package only. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 6-143