HM-65162 TM 2K x 8 Asynchronous CMOS Static RAM March 1997 Features Description • Fast Access Time . . . . . . . . . . . . . . . . . . . 70/90ns Max The HM-65162 is a CMOS 2048 x 8 Static Random Access Memory manufactured using the Intersil Advanced SAJI V process. The device utilizes asynchronous circuit design for fast cycle time and ease of use. The pinout is the JEDEC 24 pin DIP, and 32 pad 8-bit wide standard which allows easy memory board layouts flexible to accommodate a variety of industry standard PROMs, RAMs, ROMs and EPROMs. The HM-65162 is ideally suited for use in microprocessor based systems with its 8-bit word length organization. The convenient output enable also simplifies the bus interface by allowing the data outputs to be controlled independent of the chip enable. Gated inputs lower operating current and also eliminate the need for pull-up or pull-down resistors. • Low Standby Current. . . . . . . . . . . . . . . . . . . . 50µA Max • Low Operating Current . . . . . . . . . . . . . . . . . 70mA Max • Data Retention at 2.0V . . . . . . . . . . . . . . . . . . . 20µA Max • TTL Compatible Inputs and Outputs • JEDEC Approved Pinout (2716, 6116 Type) • No Clocks or Strobes Required • Equal Cycle and Access Time • Single 5V Supply • Gated Inputs • No Pull-Up or Pull-Down Resistors Required Ordering Information PACKAGE TEMP. RANGE 70ns/20µA (NOTE 1) 90ns/40µA (NOTE 1) 90ns/300µA (NOTE 1) PKG. NO. -40oC to +85oC HM1-65162B-9 JAN# -55oC to +125oC 29110BJA 29104BJA SMD# -55oC to +125oC 8403606JA 8403602JA 8403603JA F24.6 -40oC to +85oC HM4-65162B-9 HM4-65162-9 HM4-65162C-9 J32.A -55oC to 125oC 8403606ZA 8403602ZA 8403603ZA J32.A CERDIP CLCC SMD# HM1-65162-9 HM1-65162C-9 F24.6 - F24.6 NOTE: 1. Access time/data retention supply current. Pinouts HM-65162 (CLCC) TOP VIEW NC NC NC VCC NC NC PIN A7 HM-65162 (CERDIP) TOP VIEW 4 3 2 1 32 31 30 NC 5 29 A8 3 22 A9 A5 6 28 A9 A4 4 21 W 7 27 NC A3 5 20 G A4 A2 6 19 A10 A3 8 26 W A1 7 18 E A2 9 25 G A0 8 17 DQ7 A1 10 24 A10 DQ0 9 16 DQ6 A0 11 23 E DQ1 10 15 DQ5 NC 12 22 DQ7 DQ2 11 14 DQ4 13 21 DQ6 GND 12 13 DQ3 17 18 19 20 GND 14 15 16 DQ2 DQ0 DQ5 A6 A5 DQ4 23 A8 NC 24 VCC 2 DQ3 1 A6 DQ1 A7 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved 1 A0 - A10 E VSS/GND DQ0 - DQ7 DESCRIPTION No Connect Address Input Chip Enable/Power Down Ground Data In/Data Out VCC Power (+5V) W Write Enable G Output Enable FN3000.1 HM-65162 Functional Diagram A1 A A2 A3 A4 A5 A6 A7 ROW ADDRESS BUFFER 7 ROW DECODER 128 128 X 128 MEMORY ARRAY A 7 1 OF 8 128 E 4 4 A G 8 COLUMN DECODER AND DATA INPUT / OUTPUT (X8) A COLUMN ADDRESS BUFFER W A0 2 A8 A9 A10 DQ0 THRU DQ7 HM-65162 Absolute Maximum Ratings Thermal Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to V CC +0.3V Typical Derating Factor . . . . . . . . . . 05mA/MHz Increase in ICCOP ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Resistance θJA (oC/W) θJC (oC/W) CERDIP Package . . . . . . . . . . . . . . . . 48 8 CLCC Package . . . . . . . . . . . . . . . . . . 66 12 Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . +175oC Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . +300oC Operating Conditions Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range HM-65162S-9, HM-65162B-9, HM-65162-9, HM65162C-9. . . . . . . . . . . . . . . . . . -40oC to +85oC Die Characteristics Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26000 Gates CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. DC Electrical Specifications VCC = 5V ±10%; TA = -40oC to +85oC (HM-65162S-9, HM-65162B-9, HM-65162-9, HM-65162C-9) LIMITS SYMBOL ICCSB1 PARAMETER Standby Supply Current MIN MAX UNITS - 50 µA HM-65162B-9, IO = 0mA, E = VCC - 0.3V, VCC = 5.5V TEST CONDITIONS - 100 µA HM-65162S-9, HM65162-9, IO = 0mA, E = VCC - 0.3V, VCC = 5.5V - 900 µA HM-65162C-9, IO = 0mA, E = VCC - 0.3V, VCC = 5.5V ICCSB Standby Supply Current - 8 mA E = 2.2V, IO = 0mA, VCC = 5.5V ICCEN Enabled Supply Current - 70 mA E = 0.8V, IO = 0mA, VCC = 5.5V ICCOP Operating Supply Current (Note 1) - 70 mA E = 0.8V, IO = 0mA, f = 1MHz, VCC = 5.5V ICCDR Data Retention Supply Current - 20 µA HM-65162B-9, IO = 0mA, VCC = 2.0V, E = VCC - 0.3V - 40 µA HM-65162S-9, HM-65162-9, IO = 0mA, VCC = 2.0V, E = VCC - 0.3V - 300 µA HM-65162C-9, IO = 0mA, VCC = 2.0V, E = VCC - 0.3V 2.0 - V VCCDR Data Retention Supply Voltage Input Leakage Current -1.0 +1.0 µA VI = VCC or GND, VCC = 5.5V IIOZ Input/Output Leakage Current -1.0 +1.0 µA VIO = VCC or GND, VCC = 5.5V VIL Input Low Voltage -0.3 0.8 V VCC = 4.5V VIH Input High Voltage 2.2 VCC +0.3 V VCC = 5.5V II VOL Output Low Voltage - 0.4 V IO = 4.0mA, VCC = 4.5V VOH1 Output High Voltage 2.4 - V IO = -1.0mA, VCC = 4.5V VOH2 Output High Voltage (Note 2) VCC -0.4 - V IO = -100µA, V CC = 4.5V Capacitance TA = +25oC SYMBOL CI CIO MAX UNITS Input Capacitance (Note 2) PARAMETER 10 pF Input/Output Capacitance (Note 2) 12 pF NOTES: 1. Typical derating 5mA/MHz increase in ICCOP. 2. Tested at initial design and after major design changes. 3 TEST CONDITIONS f = 1MHz, All measurements are referenced to device GND HM-65162 AC Electrical Specifications VCC = 5V ±10%, TA = -40oC to +85oC (HM-65162S-9, HM-65162B-9, HM65162-9, HM-65162C-9) LIMITS HM-65162S-9 SYMBOL PARAMETER MIN HM-65162B-9 MAX MIN HM-65162-9 MAX MIN HM-65162C-9 MAX MIN MAX UNITS CONDITIONS READ CYCLE (1) TAVAX Read Cycle Time 55 - 70 - 90 - 90 - ns (Notes 1, 3) (2) TAVQV Address Access Time - 55 - 70 - 90 - 90 ns (Notes 1, 3, 4) (3) TELQV Chip Enable Access Time - 55 - 70 - 90 - 90 ns (Notes 1, 3) (4) TELQX Chip Enable Output Enable Time 5 - 5 - 5 - 5 - ns (Notes 2, 3) (5) TGLQV Output Enable Access Time - 35 - 50 - 65 - 65 ns (Notes 1, 3) (6) TGLQX Output Enable Output Enable Time 5 - 5 - 5 - 5 - ns (Notes 2, 3) (7) TEHQZ Chip Enable Output Disable Time - 35 - 35 - 50 - 50 ns (Notes 2, 3) (8) TGHQZ Output Enable Output Disable Time - 30 - 35 - 40 - 40 ns (Notes 2, 3) (9) TAVQX Output Hold From Address Change 5 - 5 - 5 - 5 - ns (Notes 1, 3) (10) TAVAX Write Cycle Time 55 - 70 - 90 - 90 - ns (Notes 1, 3) (11) TELWH Chip Selection to End of Write 45 - 45 - 55 - 55 - ns (Notes 1, 3) WRITE CYCLE (12) TAVWL Address Setup Time 5 - 10 - 10 - 10 - ns (Notes 1, 3) (13) TWLWH Write Enable Pulse Width 40 - 40 - 55 - 55 - ns (Notes 1, 3) (14) TWHAX Write Enable Read Setup Time 10 - 10 - 10 - 10 - ns (Notes 1, 3) (15) TGHQZ Output Enable Output Disable Time - 30 - 35 - 40 - 40 ns (Notes 2, 3) (16) TWLQZ Write Enable Output Disable Time - 30 - 40 - 50 - 50 ns (Notes 2, 3) (17) TDVWH Data Setup Time 25 - 30 - 30 - 30 - ns (Notes 1, 3) (18) TWHDX Data Hold Time 10 - 10 - 15 - 15 - ns (Notes 1, 3) (19) TWHQX Write Enable Output Enable Time 0 - 0 - 0 - 0 - ns (Notes 1, 3) (20) TWLEH Write Enable Pulse Setup Time 45 - 40 - 55 - 55 - ns (Notes 1, 3) (21) TDVEH Chip Enable Data Setup Time 25 - 30 - 30 - 30 - ns (Notes 1, 3) (22) TAVWH Address Valid to End of Write 45 - 50 - 65 - 65 - ns (Notes 1, 3) NOTES: 1. Input pulse levels: 0 to 3.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate equivalent and CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF. 2. Tested at initial design and after major design changes. 3. V CC = 4.5 and 5.5V. 4. TAVQV = TELQV + TAVEL. 4 HM-65162 Timing Waveforms (1) TAVAX (2) TAVQV ADDRESS (8) TGHQZ G (5) TGLQV E (7) TEHQZ (6) TGLQX (3) TELQV (9) TAVQX Q (4) TELQX NOTE: 1. W is high for a Read Cycle. FIGURE 1. READ CYCLE Addresses must remain stable for the duration of the read cycle. To read, G and E must be ≤ VIL and W ≥ VIH. The output buffers can be controlled independently by G while E is low. To execute consecutive read cycles, E may be tied low continuously until all desired locations are accessed. (10) TAVAX ADDRESS (14) TWHAX (11) TELWH E (12) TAVWL (13) TWLWH (20) TWLEH W (16) TWLQZ (19) TWHQX Q (21) TDVEH D (17) TDVWH (18) TWHDX (22) TAVWH NOTE: 1. G is low throughout Write Cycle. FIGURE 2. WRITE CYCLE I To write, addresses must be stable, E low and W falling low for a period no shorter than TWLWH. Data in is referenced with the rising edge of W, (TDVWH and TWHDX). While addresses are changing, W must be high. When W falls low, the I/O pins are still in the output state for a period of TWLQZ and input data of the opposite phase to the outputs must not be applied, (Bus contention). If E transitions low simultaneously with the W line transitioning low, or after the W transition, the output will remain in a high impedance state. G is held continuously low. 5 HM-65162 Timing Waveforms (Continued) (10) TAVAX ADDRESS (22) TAVWH G (11) TELWH (14) TWHAX E (12) TAVWL (13) TWLWH W TGHQZ (15) Q (21) TDVEH D (17) TDVWH (18) TWHDX FIGURE 3. WRITE CYCLE II In this write cycle G has control of the output after a period, TGHQZ. G switching the output to a high impedance state allows data in to be applied without bus contention after Low Voltage Data Retention Intersil CMOS RAMs are designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules ensure data retention: 2. On RAMs which have selects or output enables (e.g., S, G), one of the selects or output enables should be held in the deselected state to keep the RAM outputs high impedance, minimizing power dissipation. 1. Chip Enable (E) must be held high during data retention; within VCC -0.3V to VCC +0.3V. 3. Inputs which are to be held high (e.g., E) must be kept between VCC +0.3V and 70% of VCC during the power up and down transitions. 4. The RAM can begin operation > 55ns after VCC reaches the minimum operating voltage (4.5V). DATA RETENTION TIMING VCC 4.5V VCC ≥ 02.0V 4.5V >55ns E VCC -0.3V TO VCC +0.3V FIGURE 4. DATA RETENTION TIMING 6 HM-65162 Typical Performance Curve -3 -4 VCC = 2.0V -5 LOG (ICC/(1A)) -6 -7 -8 -9 -10 -11 -12 -55 -35 -15 5 25 45 65 85 105 125 TA (oC) FIGURE 5. TYPICAL ICCDR vs TA All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. 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