Hitachi HM624100HJP-10 4m high speed sram (1-mword x 4-bit) Datasheet

HM624100H Series
4M High Speed SRAM (1-Mword × 4-bit)
ADE-203-789D (Z)
Rev. 1.0
Sep. 15, 1998
Description
The HM624100H is a 4-Mbit high speed static RAM organized 1-Mword × 4-bit. It has realized high speed
access time by employing CMOS process (4-transistor + 2-poly resistor memory cell) and high speed circuit
designing technology. It is most appropriate for the application which requires high speed and high density
memory, such as cache and buffer memory in system. The HM624100H is packaged in 400-mil 32-pin SOJ
for high density surface mounting.
Features
• Single 5.0 V supply : 5.0 V ± 10 %
• Access time 10/12/15 ns (max)
• Completely static memory
 No clock or timing strobe required
• Equal access and cycle times
• Directly TTL compatible
 All inputs and outputs
• Operating current : 200/180/160 mA (max)
• TTL standby current : 70/60/50 mA (max)
• CMOS standby ccurrent : 5 mA (max)
: 1.2 mA (max) (L-version)
• Data retension current : 0.8 mA (max) (L-version)
• Data retension voltage : 2.0 V (min) (L-version)
• Center VCC and VSS type pinout
HM624100H Series
Ordering Information
Type No.
Access time
Package
HM624100HJP-10
HM624100HJP-12
HM624100HJP-15
10 ns
12 ns
15 ns
400-mil 32-pin plastic SOJ (CP-32DB)
HM624100HLJP-10
HM624100HLJP-12
HM624100HLJP-15
10 ns
12 ns
15 ns
Pin Arrangement
HM624100HJP/HLJP Series
A0
A1
A2
A3
A4
CS
I/O1
VCC
VSS
I/O2
WE
A5
A6
A7
A8
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
(Top view)
2
A19
A18
A17
A16
A15
OE
I/O4
VSS
VCC
I/O3
A14
A13
A12
A11
A10
NC
HM624100H Series
Pin Description
Pin name
Function
A0 to A19
Address input
I/O1 to I/O4
Data input/output
CS
Chip select
OE
Output enable
WE
Write enable
VCC
Power supply
VSS
Ground
NC
No connection
Block Diagram
(LSB)
A1
A17
A7
A11
A16
A2
A6
A5
(MSB)
Internal
voltage
generater
Memory matrix
256 rows × 16 columns ×
256 blocks × 4 bit
(4,194,304 bits)
Row
decoder
VCC
VSS
CS
Column I/O
I/O1
.
.
.
I/O4
Input
data
control
Column decoder
CS
A10 A8 A9 A19 A12 A13 A14 A0 A18 A15 A3 A4
(LSB)
WE
CS
(MSB)
OE
CS
3
HM624100H Series
Operation Table
CS
OE
WE
Mode
VCC current
I/O
Ref. cycle
H
×
×
Standby
I SB , I SB1
High-Z
—
L
H
H
Output disable
I CC
High-Z
—
L
L
H
Read
I CC
Dout
Read cycle (1) to (3)
L
H
L
Write
I CC
Din
Write cycle (1)
L
L
Write
I CC
Din
Write cycle (2)
Parameter
Symbol
Value
Supply voltage relative to VSS
VCC
–0.5 to +7.0
L
Note:
×: H or L
Absolute Maximum Ratings
Unit
V
1
2
Voltage on any pin relative to V SS
VT
–0.5* to V CC+0.5*
V
Power dissipation
PT
1.0
W
Operating temperature
Topr
0 to +70
°C
Storage temperature
Tstg
–55 to +125
°C
Storage temperature under bias
Tbias
–10 to +85
°C
Notes: 1. VT (min) = –2.0 V for pulse width (under shoot) ≤ 8 ns
2. VT (max) = VCC + 2.0 V for pulse width (over shoot) ≤ 8 ns
Recommended DC Operating Conditions (Ta = 0 to +70°C)
Parameter
Symbol
Supply voltage
Input voltage
Min
Typ
Max
Unit
VCC*
3
4.5
5.0
5.5
V
VSS *
4
0
0
0
VIH
VIL
Notes: 1.
2.
3.
4.
4
2.2
1
–0.5*
V
2
—
VCC + 0.5*
V
—
0.8
V
VIL (min) = –2.0 V for pulse width (under shoot) ≤ 8 ns
VIH (max) = VCC + 2.0 V for pulse width (over shoot) ≤ 8 ns
The supply voltage with all V CC pins must be on the same level.
The supply voltage with all VSS pins must be on the same level.
HM624100H Series
DC Characteristics (Ta = 0 to +70°C, VCC = 5.0 V ± 10 %, VSS = 0V)
Parameter
Symbol Min
Typ*1
Max
Unit
Test conditions
Input leakage current
IILII
—
—
2
µA
Vin = VSS to V CC
Output leakage current
IILO I
—
—
2
µA
Vin = VSS to V CC
10 ns cycle I CC
—
—
200
mA
Min cycle
CS = VIL, lout = 0 mA
Other inputs = VIH/VIL
12 ns cycle I CC
—
—
180
15 ns cycle I CC
—
—
160
10 ns cycle I SB
—
—
70
mA
Min cycle, CS = VIH,
Other inputs = VIH/VIL
12 ns cycle I SB
—
—
60
15 ns cycle I SB
—
—
50
—
0.1
5
mA
f = 0 MHz
VCC ≥ CS ≥ VCC - 0.2 V,
(1) 0 V ≤ Vin ≤ 0.2 V or
(2) VCC ≥ Vin ≥ VCC - 0.2 V
—* 2
0.1*2
1.2*2
VOL
—
—
0.4
V
I OL = 8 mA
VOH
2.4
—
—
V
I OH = –4 mA
Operation power
supply current
Standby power supply
current
I SB1
Output voltage
Notes: 1. Typical values are at VCC = 5.0 V, Ta = +25°C and not guaranteed.
2. This characteristics is guaranteed only for L-version.
Capacitance (Ta = +25°C, f = 1.0 MHz)
Parameter
1
Input capacitance*
Input/output capacitance*
Note:
1
Symbol
Min
Typ
Max
Unit
Test conditions
Cin
—
—
6
pF
Vin = 0 V
CI/O
—
—
8
pF
VI/O = 0 V
1. This parameter is sampled and not 100% tested.
5
HM624100H Series
AC Characteristics (Ta = 0 to +70°C, VCC = 5.0 V ± 10 %, unless otherwise noted.)
Test Conditions
•
•
•
•
Input pulse levels: 3.0 V/0.0 V
Input rise and fall time: 3 ns
Input and output timing reference levels: 1.5 V
Output load: See figures (Including scope and jig)
5V
480Ω
Dout Zo=50 Ω
Dout
RL=50 Ω
255Ω
1.5 V
Output load (A)
5 pF
Output load (B)
(for tCLZ, tOLZ, tCHZ, tOHZ, tWHZ, and tOW)
Read Cycle
HM624100H
-10
-12
-15
Parameter
Symbol Min
Max
Min
Max
Min
Max
Unit Notes
Read cycle time
t RC
10
—
12
—
15
—
ns
Address access time
t AA
—
10
—
12
—
15
ns
Chip select access time
t ACS
—
10
—
12
—
15
ns
Output enable to outpput valid
t OE
—
5
—
6
—
7
ns
Output hold from address change
t OH
3
—
3
—
3
—
ns
Chip select to output in low-Z
t CLZ
3
—
3
—
3
—
ns
1
Output enable to output in low-Z
t OLZ
0
—
0
—
0
—
ns
1
Chip deselect to output in high-Z
t CHZ
—
5
—
6
—
7
ns
1
Output disable to output in high-Z
t OHZ
—
5
—
6
—
7
ns
1
6
HM624100H Series
Write Cycle
HM624100H
-10
-12
-15
Parameter
Symbol Min
Max
Min
Max
Min
Max
Unit Notes
Write cycle time
t WC
10
—
12
—
15
—
ns
Address valid to end of write
t AW
7
—
8
—
10
—
ns
Chip select to end of write
t CW
7
—
8
—
10
—
ns
9
Write pulse width
t WP
7
—
8
—
10
—
ns
8
Address setup time
t AS
0
—
0
—
0
—
ns
6
Write recovery time
t WR
0
—
0
—
0
—
ns
7
Data to write time overlap
t DW
5
—
6
—
7
—
ns
Data hold from write time
t DH
0
—
0
—
0
—
ns
Write disable to output in low-Z
t OW
3
—
3
—
3
—
ns
1
Output disable to output in high-Z
t OHZ
—
5
—
6
—
7
ns
1
Write enable to output in high-Z
t WHZ
—
5
—
6
—
7
ns
1
Note:
1. Transition is measured ±200 mV from steady voltage with Load (B). This parameter is sampled
and not 100% tested.
2. Address should be valid prior to or coincident with CS transition low.
3. WE and/or CS must be high during address transition time.
4. if CS and OE are low during this period, I/O pins are in the output state. Then, the data input
signals of opposite phase to the outputs must not be applied to them.
5. If the CS low transition occurs simultaneously with the WE low transition or after the WE transition,
output remains a high impedance state.
6. t AS is measured from the latest address transition to the later of CS or WE going low.
7. t WR is measured from the earlier of CS or WE going high to the first address transition.
8. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition
among CS going low and WE going low. A write ends at the earliest transition among CS going
high and WE going high. tWP is measured from the beginnig of write to the end of write.
9. t CW is measured from the later of CS going low to the the end of write.
7
HM624100H Series
Timing Waveforms
Read Timing Waveform (1) (WE = VIH)
tRC
Address
Valid address
tOH
tAA
tACS
tCHZ
CS
tOE
tOHZ
OE
tOLZ
tCLZ
Dout
High Impedance
Valid data
Read Timing Waveform (2) (WE = VIH, CS = VIL , OE = VIL )
tRC
Address
Valid address
tAA
tOH
tOH
Dout
8
Valid data
HM624100H Series
Read Timing Waveform (3) (WE = VIH, CS = VIL , OE = VIL )*2
tRC
CS
tACS
tCHZ
tCLZ
Dout
High
Impedance
Valid data
High
Impedance
Write Timing Waveform (1) (WE Controlled)
tWC
Valid address
Address
tWR
tAW
OE
tCW
CS*3
tAS
tWP
WE*3
tOHZ
High impedance*5
Dout
tDW
Din
*4
tDH
Valid data
*4
9
HM624100H Series
Write Timing Waveform (2) (CS Controlled)
tWC
Valid address
Address
tWR
tCW
CS *3
tAW
tWP
WE *3
tAS
tWHZ
tOW
High impedance*5
Dout
tDW
Din
10
*4
tDH
Valid data
*4
HM624100H Series
Low VCC Data Retention Characteristics (Ta = 0 to +70°C)
This characteristics is guaranteed only for L-version.
Parameter
Symbol
Min
Typ*1
Max
Unit
Test conditions
VCC for data retention
VDR
2.0
—
—
V
VCC ≥ CS ≥ VCC – 0.2 V
(1) 0 V ≤ Vin ≤ 0.2 V or
(2) VCC ≥ Vin ≥ VCC – 0.2 V
Data retention current
I CCDR
—
50
800
µA
VCC = 3 V, VCC ≥ CS ≥ VCC – 0.2 V
(1) 0 V ≤ Vin ≤ 0.2 V or
(2) VCC ≥ Vin ≥ VCC – 0.2 V
Chip deselect to data
retention time
t CDR
0
—
—
ns
See retention waveform
Operation recovery time
tR
5
—
—
ms
Note:
1. Typical values are at VCC = 3.0 V, Ta = +25˚C, and not guaranteed.
Low V CC Data Retention Timing Waveform
tCDR
Data retention mode
tR
VCC
3.0 V
VDR
2.2 V
CS
0V
VCC ≥ CS ≥ VCC – 0.2 V
11
HM624100H Series
Package Dimensions
HM624100HJP/HLJP Series (CP-32DB)
Unit: mm
3.50 ± 0.26
1.30 Max
0.43 ± 0.10
0.41 ± 0.08
1.27
0.10
Dimension including the plating thickness
Base material dimension
12
2.85 ± 0.12
16
0.74
0.80 +0.25
–0.17
1
11.18 ± 0.13
17
10.16 ± 0.13
32
20.71
21.08 Max
9.40 ± 0.25
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
CP-32DB
Conforms
Conforms
1.2 g
HM624100H Series
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual
property rights, in connection with use of the information contained in this document.
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received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of
bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic,
safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for
maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and
other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the
guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or
failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the
equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage
due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
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Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
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Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.
13
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