Hanbit HMD32M32M16EG-5 128mbyte (32mx32) 72-pin edo mode 4k ref. simm design 5v Datasheet

HANBiT
HMD32M32M16EG
128Mbyte (32Mx32) 72-pin EDO Mode 4K Ref. SIMM Design 5V
Part No. HMD32M32M16EG
GENERAL DESCRIPTION
The HMD32M32M16EG is a 16M x 32bit dynamic RAM high-density memory module. The module consists of sixteen
CMOS 16M x 4bit DRAMs in 32-pin TSOPII packages mounted on a 72-pin, double-sided, FR-4-printed circuit board. A
0.1uF decoupling capacitor is mounted on the printed circuit board for each DRAM components. The module is a Single
In-line Memory Module with edge connections and is intended for mounting in to 72-pin edge connector sockets. All
module components may be powered from a single 5V DC power supply and all inputs and outputs are TTL-compatible.
PIN ASSIGNMENT
FEATURES
wPart Identification
HMD32M32M16EG— 4K Cycles/64ms Ref. Gold
w Access times : 50, 60ns
w High-density 128MByte design
w Single + 5V ±0.5V power supply
w JEDEC standard pinout
w EDO mode operation
w TTL compatible inputs and outputs
w FR4-PCB design
OPTIONS
MARKING
w Timing
50ns access
60ns access
-5
-6
w Packages
72-pin SIMM
M
PERFORMANCE RANGE
SPEED
tRAC
tCAC
tRC
-45
45ns
12ns
74ns
-5
50ns
13ns
84ns
-6
60ns
15ns
104ns
PRESENCE DETECT PINS
Pin
50ns
60ns
PD1
NC
NC
PD2
Vss
Vss
PD3
Vss
NC
PD4
Vss
NC
URL:www.hbe.co.kr
REV.1.0 (August. 2002)
PIN
SYMBOL
PIN
SYMBOL
PIN
SYMBOL
1
Vss
25
DQ22
49
DQ8
2
DQ0
26
DQ7
50
DQ24
3
DQ16
27
DQ23
51
DQ9
4
DQ1
28
A7
52
DQ25
5
DQ17
29
A11
53
DQ10
6
DQ2
30
Vcc
54
DQ26
7
DQ18
31
A8
55
DQ11
8
DQ3
32
A9
56
DQ27
9
DQ19
33
/RAS3
57
DQ12
10
Vcc
34
/RAS2
58
DQ28
11
NC
35
NC
59
Vcc
12
A0
36
NC
60
DQ29
13
A1
37
NC
61
DQ13
14
A2
38
NC
62
DQ30
15
A3
39
Vss
63
DQ14
16
A4
40
/CAS0
64
DQ31
17
A5
41
/CAS2
65
DQ15
18
A6
42
/CAS3
66
NC
19
A10
43
/CAS1
67
PD1
20
DQ4
44
/RAS0
68
PD2
21
DQ20
45
/RAS1
69
PD3
22
DQ5
46
NC
70
PD4
23
DQ21
47
/WE
71
NC
24
DQ6
48
NC
72
Vss
72PIN SIMM TOP VIEW
HANBiT Electronics Co.,Ltd.
-1-
HANBiT
HMD32M32M16EG
FUNCTIONAL BLOCK DIAGRAM
/CAS0
/RAS0
/CAS
/RAS
U1
/OE
/WE A0 -A11
/CAS
/RAS
/OE
/WE
DQ1
DQ2
DQ3
DQ4
DQ1
DQ2
U2
DQ3
A0 -A11 DQ4
DQ0-DQ3
DQ4-DQ7
DQ1
DQ2
DQ3
DQ4
DQ1
DQ2
DQ3
DQ4
U5
/WE
U6
/WE
/CAS
/RAS
/OE
A0-A11
/CAS0
/RAS1
/CAS
/RAS
/OE
A0 -A11
DQ8-DQ11
/CAS1
/CAS
/RAS
/OE
/WE
U3
A0 -A11
DQ1
DQ2
DQ3
DQ4
DQ1
DQ2
DQ3
DQ4
U7
/WE
/CAS
/RAS
/OE
A0 -A11
/CAS1
DQ12-DQ15
/CAS
/RAS
/OE
/WE
DQ1
DQ2
U4
DQ3
A0 -A11 DQ4
/WE
DQ1
DQ2
U9
DQ3
A0 -A11 DQ4
/WE
DQ1
DQ2
U10
DQ3
A0 -A11 DQ4
/WE
DQ1
DQ2
U11
DQ3
A0 -A11 DQ4
/WE
DQ1
DQ2
U12
DQ3
A0 -A11 DQ4
DQ1
DQ2
DQ3
DQ4
U8
/WE
/CAS
/RAS
/OE
A0 -A11
DQ16-DQ19
/CAS2
/RAS2
/CAS
/RAS
/OE
DQ1
DQ2
DQ3
DQ4
U13
/WE
/CAS
/RAS
/OE
A0 -A11
/CAS2
/RAS3
DQ20-DQ23
/CAS
/RAS
/OE
/CAS3
DQ1
DQ2
DQ3
DQ4
U14
/WE
/CAS
/RAS
/OE
A0 -A11
DQ24-DQ27
/CAS
/RAS
/OE
DQ1
DQ2
DQ3
DQ4
U15
/WE
/CAS
/RAS
/OE
A0 -A11
/CAS3
DQ28-DQ31
/CAS
/RAS
/OE
DQ1
DQ2
DQ3
DQ4
U16
/WE
/CAS
/RAS
/OE
A0 -A11
/WE
A0-A11
Vcc
Vss
URL:www.hbe.co.kr
REV.1.0 (August. 2002)
0.1uF Capacitor
for each DRAM
To all DRAMs
HANBiT Electronics Co.,Ltd.
-2-
HANBiT
HMD32M32M16EG
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
VIN ,OUT
-1V to 7.0V
Voltage on Vcc Supply Relative to Vss
Vcc
-1V to 7.0V
Power Dissipation
PD
16W
TSTG
-55oC to 150oC
Voltage on Any Pin Relative to Vss
Storage Temperature
Short Circuit Output Current
IOS
50mA
w Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be
restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
( Voltage reference to VSS, TA=0 to 70 o C )
PARAMETER
SYMBOL
MIN
TYP.
MAX
UNIT
Supply Voltage
Vcc
4.5
5.0
5.5
V
Ground
Vss
0
0
0
V
Input High Voltage
VIH
2.4
-
Vcc+1
V
Input Low Voltage
VIL
-1.0
-
0.8
V
DC AND OPERATING CHARACTERISTICS
SYMBOL
SPEED
MIN
MAX
UNITS
-5
-
976
mA
-6
-
896
mA
Don’t care
-
32
mA
-5
-
976
mA
-6
-
896
mA
-5
-
896
mA
-6
-
816
mA
ICC5
Don’t care
-
16
mA
ICC6
-5
-
976
mA
-6
-
896
mA
Il(L)
-10
10
µA
IO(L)
-5
5
µA
ICC1
ICC2
ICC3
ICC4
VOH
2.4
-
V
VOL
-
0.4
V
ICC1 : Operating Current * (/RAS , /CAS , Address cycling @t RC=min.)
ICC2 : Standby Current ( /RAS=/CAS=VIH )
ICC3 : /RAS Only Refresh Current * ( /CAS=V IH, /RAS, Address cycling @tRC=min )
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REV.1.0 (August. 2002)
HANBiT Electronics Co.,Ltd.
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HANBiT
HMD32M32M16EG
ICC4 : Fast Page Mode Current * (/RAS=VIL, /CAS, Address cycling @tPC=min )
ICC5 : Standby Current (/RAS=/CAS=Vcc-0.2V )
ICC6 : /CAS-Before-/RAS Refresh Current * (/RAS and /CAS cycling @t RC=min )
IIL : Input Leakage Current (Any input 0V ≤ VIN ≤ 6.5V, all other pins not under test = 0V)
IOL : Output Leakage Current (Data out is disabled, 0V ≤ VOUT ≤ 5.5V
VOH : Output High Voltage Level (IOH= -5mA )
VOL : Output Low Voltage Level (IOL = 4.2mA )
* NOTE: ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the
output open. ICC is specified as an average current. In ICC1 and ICC3, address cad be changed maximum once
while /RAS=VIL. In ICC4, address can be changed maximum once within one page mode cycle.
CAPACITANCE
o
( TA=25 C, Vcc = 5V, f = 1Mz )
DESCRIPTION
SYMBOL
MIN
MAX
UNITS
Input Capacitance (A0-A11)
CIN1
-
90
pF
Input Capacitance (/W)
C IN2
-
122
pF
Input Capacitance (/RAS0)
CIN3
-
38
pF
Input Capacitance (/CAS0-/CAS3)
CIN4
-
38
pF
Input/Output Capacitance (DQ0-31)
CDQ1
-
17
pF
AC CHARACTERISTICS
o
( 0 C ≤ TA ≤ 70oC , Vcc = 5V±10%, See notes 1,2.)
-5
PARAMETER
SYMBOL
MIN
-6
MAX
MIN
MA
UNIT
X
Random read or write cycle time
tRC
Access time from /RAS
tRAC
50
60
ns
Access time from /CAS
tCAC
13
15
ns
Access time from column address
tAA
25
30
ns
/CAS to output in Low-Z
tCLZ
3
Output buffer turn-off delay
tOFF
3
13
3
15
ns
Transition time (rise and fall)
tT
1
50
1
50
ns
/RAS precharge time
tRP
30
/RAS pulse width
tRAS
50
/RAS hold time
tRSH
13
15
ns
/CAS hold time
tCSH
38
45
ns
/CAS pulse width
tCAS
8
10K
10
10K
ns
/RAS to /CAS delay time
tRCD
20
37
20
45
ns
/RAS to column address delay time
tRAD
15
25
15
30
ns
/CAS to /RAS precharge time
tCRP
5
URL:www.hbe.co.kr
REV.1.0 (August. 2002)
84
104
ns
3
ns
40
10K
60
5
ns
10K
ns
ns
HANBiT Electronics Co.,Ltd.
-4-
HANBiT
HMD32M32M16EG
Row address set-up time
tASR
0
0
ns
Row address hold time
tRAH
10
10
ns
Column address set-up time
tASC
0
0
ns
Column Address to /RAS lead time
tRAL
25
30
ns
Read command set-up time
tRCS
0
0
ns
Read command hold referenced to /CAS
tRCH
0
0
ns
Read command hold referenced to /RAS
tRRH
0
0
ns
Write command hold time
tWCH
10
10
ns
Write command hold referenced to /RAS
tWCR
50
55
ns
Write command pulse width
tWP
10
10
ns
Write command to /RAS lead time
tRWL
13
15
ns
Write command to /CAS lead time
tCWL
8
10
ns
Data-in set-up time
tDS
0
0
ns
Data-in hold time
tDH
8
10
ns
Refresh period
tREF
Write command set-up time
tWCS
0
0
ns
/CAS setup time (C-B-R refresh)
tCSR
5
5
ns
/CAS hold time (C-B-R refresh)
tCHR
10
10
ns
/RAS precharge to /CAS hold time
tRPC
5
5
ns
64
64
ns
NOTES
1.An initial pause of 200µs is required after power-up followed by any 8 /RAS-only or /CAS-before-/RAS refresh cycles
before proper device operation is achieved.
2.VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between
VIH(min) and VIL(max) and are assumed to be 5ns for all inputs.
3.Measured with a load equivalent to 2TTL loads and 100pF
4.Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD
is greater than the specified tRCD(max) limit, then access time is controlled exclusively by t CAC.
5.Assumes that tRCD ≥ tRCD(max)
6. tAR, tWCR, tDHR are referenced to tRAD(max)
7.This parameter defines the time at which the output achieves the open circuit condition and is not referenced to V OH
or VOL.
8. tWCS, tRWD, tCWD anf tAWD are non restrictive operating parameter.
They are included in the data sheet as electrical characteristic only. If t WCS ≥ tWCS(min) the cycle is an early write
cycle and the data out pin will remain high impedance for the duration of the cycle.
9. Either tRCH or tRRH must be satisfied for a read cycle.
10. These parameters are referenced to the /CAS leading edge in early write cycles and to the /W leading edge in readwrite cycles.
11. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference
point only. If tRAD is greater than the specified tRAD(max) limit. then access time is controlled by tAA.
URL:www.hbe.co.kr
REV.1.0 (August. 2002)
HANBiT Electronics Co.,Ltd.
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HANBiT
HMD32M32M16EG
AC CHARACTERISTICS
o
( 0 C ≤ TA ≤ 70oC , Vcc = 5V±10%)
-5
PARAMETER
-6
SYMBOL
MIN
MAX
MIN
UNIT
NOTE
11
MAX
Hyper page mode cycle time
tHPC
20
25
ns
/CAS precharge time (Hyper page cycle)
tCP
8
10
ns
/RAS pulse width (Hyper page cycle)
tRASP
50
/RAS hold time from /CAS precharge
tRHCP
30
35
ns
/W to RAS precharge time (C-B-R refresh)
tWRP
10
10
ns
/W to RAS hold time (C-B-R refresh)
tWRH
10
10
ns
Output data hold time
tDOH
5
5
ns
Output buffer turn off delay from /RAS
tREZ
3
13
3
15
ns
6,12
Output buffer turn off delay from W
tWEZ
3
13
3
15
ns
6
/W to data delay
tWED
15
15
ns
/W puls width
tWPE
5
5
ns
200K
60
200K
ns
NOTES
1. An initial pause of 200us is required after power-up followed by any 8 /RAS-only or /CAS-before-/RAS refresh
cycles before proper device operation is achieved.
2. Input voltage levels are Vih/Vil. VIH(min) and VIL(max) are reference levels for measuring timing of input signals.
Transition times are measured between VIH(min) and VIL(max) and are assumed to be 5ns for all inputs.
3. Measured with a load equivalent to 1 TTL loads and 100pF.
4. Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference
point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC.
5. Assumes that tRCD ≥ tRCD(max).
6. This parameter defines the time at which the output achieves the open circuit and is not referenced for V OH or VOL.
7. tWCS is non-restrictive operating parameter. It is included in the data sheet as electrical characteristics only. If
tWCS ≥ tWCS(min), the cycle is an early write cycle and the data out pin will remain high impedance for the duration
of the cycle.
8. Either tRCH or tRRH must be satisfied for a read cycle.
9. These parameters are referenced to the /CAS leading edge in early write cycles.
10. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as reference point
only. If tRAD is greater than the specified tRAD(max) limit access time is controlled by tAA.
11. tASC ≥6ns, Assume t T=2.0ns.
12. If /RAS goes high before /CAS high going, the open circuit condition of the output is achieved by /CAS high going.
If /CAS goes high before /RAS high going , the open circuit condition of the output is achieved by /RAS going.
.
URL:www.hbe.co.kr
REV.1.0 (August. 2002)
HANBiT Electronics Co.,Ltd.
-6-
HANBiT
HMD32M32M16EG
PACKAGING INFORMATION
2.54 mm MAX
0.25mm MAX
Gold: 1.04±0.10 mm
Solder: 0.914±0.10 mm
1.27 mm
1.27±0.08
(Solder & Gold Plating)
ORDERING INFORMATION
Part Number
Density
Org.
Package
HMD32M32M16EG-5
128MByte
x 32
72 Pin-SIMM
HMD32M32M16EG-6
128MByte
x 32
72 Pin-SIMM
URL:www.hbe.co.kr
REV.1.0 (August. 2002)
Component
Vcc
MODE
SPEED
16EA
5V
EDO
50ns
16EA
5V
EDO
60ns
Number
HANBiT Electronics Co.,Ltd.
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