Hanbit HMD32M64D8A-F10L Synchronous dram module 64mbyte (8mx72bit),dimm based on 32mx8, 4banks, 8k ref., 3.3v Datasheet

HANBit
HSD32M64D8A
Synchronous DRAM Module 64Mbyte (8Mx72bit),DIMM based on
32Mx8, 4Banks, 8K Ref., 3.3V
Part No. HSD32M64D8A
GENERAL DESCRIPTION
The HSD32M64D8A is a 32M x 64 bit Synchronous Dynamic RAM high density memory module. The module consists
of eight
CMOS 8M x 8 bit with 4banks Synchronous DRAMs in TSOP-II 400mil packages on a 168-pin glass-epoxy
substrate. Two 0.33uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The
HSD32M64D8A is a DIMM(Dual in line Memory Module) and is intended for mounting into 168-pin edge connector sockets.
Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high
bandwidth, high performance memory system applications All module components may be powered from a single 3.3V DC
power supply and all inputs and outputs are LVTTL-compatible.
FEATURES
• Part Identification
HSD32M64D8A-F/10L : 100MHz (CL=3)
HSD32M64D8A-F/10 : 100MHz (CL=2)
HSD32M64D8A-F/13 : 133MHz (CL=3)
HSD32M64D8A-F/12 : 125MHz (CL=3)
F means Auto & Self refresh with Low-Power (3.3V)
• Burst mode operation
• Auto & self refresh capability (8192 Cycles/64ms)
• LVTTL compatible inputs and outputs
• Single 3.3V ±0.3V power supply
• MRS cycle with address key programs
- Latency (Access from column address)
- Burst length (1, 2, 4, 8 & Full page)
- Data scramble (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock
• The used device is 8M x 8bit x 4Banks SDRAM
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REV.1.0 (August.2002)
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HSD32M64D8A
PIN ASSIGNMENT
PIN
Symbol
PIN
Symbol
PIN
Symbol
PIN
Symbol
PIN
Symbol
PIN
Symbol
1
Vss
29
DQM1
57
DQ18
85
Vss
113
DQM5
141
DQ50
2
DQ0
30
/CS0
58
DQ19
86
DQ32
114
NC
142
DQ51
3
DQ1
31
NC
59
Vcc
87
DQ33
115
/RAS
143
Vcc
4
DQ2
32
Vss
60
DQ20
88
DQ34
116
Vss
144
DQ52
5
DQ3
33
A0
61
NC
89
DQ35
117
A1
145
NC
6
Vcc
34
A2
62
NC
90
Vcc
118
A3
146
NC
7
DQ4
35
A4
63
NC
91
DQ36
119
A5
147
NC
8
DQ5
36
A6
64
Vss
92
DQ37
120
A7
148
Vss
9
DQ6
37
A8
65
DQ21
93
DQ38
121
A9
149
DQ53
10
DQ7
38
A10
66
DQ22
94
DQ39
122
BA0
150
DQ54
11
DQ8
39
BA1
67
DQ23
95
DQ40
123
A11
151
DQ55
12
Vss
40
Vcc
68
Vss
96
Vss
124
Vcc
152
Vss
13
DQ9
41
Vcc
69
DQ24
97
DQ41
125
CLK1
153
DQ56
14
DQ10
42
CLK0
70
DQ25
98
DQ42
126
A12
154
DQ57
15
DQ11
43
Vss
71
DQ26
99
DQ43
127
Vss
155
DQ58
16
DQ12
44
NC
72
DQ27
100
DQ44
128
CKE0
156
DQ59
17
DQ13
45
/CS2
73
Vcc
101
DQ45
129
NC
157
Vcc
18
Vcc
46
DQM2
74
DQ28
102
Vcc
130
DQM6
158
DQ60
19
DQ14
47
DQM3
75
DQ29
103
DQ46
131
DQM7
159
DQ61
20
DQ15
48
NC
76
DQ30
104
DQ47
132
NC
160
DQ62
21
CB0
49
Vcc
77
DQ31
105
CB4
133
Vcc
161
DQ63
22
CB1
50
NC
78
Vss
106
CB5
134
NC
162
Vss
23
Vss
51
NC
79
CLK2
107
Vss
135
NC
163
CLK3
24
NC
52
CB2
80
NC
108
NC
136
CB6
164
NC
25
NC
53
CB3
81
WP
109
NC
137
CB7
165
SA0
26
Vcc
54
Vss
82
SDA
110
Vcc
138
Vss
166
SA1
27
/WE
55
DQ16
83
SCL
111
/CAS
139
DQ48
167
SA2
28
DQM0
56
DQ17
84
Vcc
112
DQM4
140
DQ49
168
Vcc
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HSD32M64D8A
FUNCTIONAL BLOCK DIAGRAM
DQ0-63
CKE0
/CAS
CKE
CAS
/RAS
RAS
/CS0
CE
U1
WE
CKE
CAS
U6
RAS
/CS2
CE
WE
CKE
CAS
WE
CKE
CAS
WE
CKE
CAS
WE
CKE
CAS
WE
CKE
CAS
WE
CKE
CAS
A0-A12
U9
RAS
CE
A0-A12
U4
RAS
CE
A0-A12
U8
RAS
CE
A0-A12
U3
RAS
CE
A0-A12
U7
RAS
CE
A0-A12
U2
RAS
CE
A0-A12
WE
A0-A12
CLK
DQ0-7
CLKA
DQM0
DQM0
BA0-1
CLKB
CLK
DQ16-23
DQM2
DQM2
BA0-1
CLK
DQ32-39
DQM4
DQM4
BA0-1
CLK
DQ48-55
DQM6
DQM6
BA0-1
CLK
DQ8-15
DQM1
DQM1
BA0-1
CLK
DQ24-31
DQM3
DQM3
BA0-1
CLK
DQ40-47
DQM5
DQM5
BA0-1
CLK
DQ56-63
DQM7
DQM7
BA0-1
/WE
A0 - A12
BA0-1
Vcc
Two 0.1uF Capacitors
per each SDRAM
Vss
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HSD32M64D8A
PIN FUNCTION DESCRIPTION
Pin
Name
Input Function
CLK
System clock
Active on the positive going edge to sample all inputs.
/CE
Chip enable
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
CKE
Clock enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE should be enabled 1CLK+tSS prior to valid command.
A0 ~ A12
Address
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA12, Column address : CA0 ~ CA9
BA0 ~ BA1
Bank select address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
/RAS
Row address strobe
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
/CAS
/WE
Column
address
Latches column addresses on the positive going edge of the CLK with CAS low.
strobe
Enables column access.
Write enable
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
DQM0 ~ 7
Data
input/output
Makes data output Hi-Z, tSHZ after the clock and masks the output.
mask
Blocks data input when DQM active. (Byte masking)
DQ0 ~ 63
Data input/output
Data inputs/outputs are multiplexed on the same pins.
Vcc/Vss
Power
Power and ground for the input buffers and the core logic.
supply/ground
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
VIN ,OUT
-1V to 4.6V
Voltage on Vcc Supply Relative to Vss
Vcc
-1V to 4.6V
Power Dissipation
PD
8W
TSTG
-55oC to 150oC
Voltage on Any Pin Relative to Vss
Storage Temperature
Short Circuit Output Current
IOS
400mA
Notes:
Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be
restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
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HSD32M64D8A
DC OPERATING CONDITIONS
(Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70° C) )
PARAMETER
SYMBOL
MIN
TYP.
MAX
UNIT
NOTE
Supply Voltage
Vcc
3.0
3.3
3.6
V
Input High Voltage
VIH
2.0
3.0
Vcc+0.3
V
1
Input Low Voltage
VIL
-0.3
0
0.8
V
2
Output High Voltage
VOH
2.4
-
-
V
IOH = -2mA
Output Low Voltage
VOL
-
-
0.4
V
IOL = 2mA
Input leakage current
I LI
-10
10
uA
Notes :
1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.
3. Any input 0V ≤ VIN ≤ VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
3
CAPACITANCE
(VCC = 3.3V, TA = 23° C, f = 1MHz, VREF =1.4V ± 200 mV)
DESCRIPTION
SYMBOL
MIN
MAX
UNITS
Clock
CCLK
2.5
4.0
pF
Address
CADD
2.5
5.0
pF
/RAS, /CAS, /WE, /CS, CKE, DQM
C IN
2.5
5.0
pF
DQ (DQ0 ~ DQ15)
COUT
4.0
6.5
pF
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70° C)
TEST
PARAMETER
VERSION
SYMBOL
CONDITION
-13
-12
-10
-10L
120
120
110
110
UNIT
NOTE
mA
1
Burst length = 1
Operating current
(One bank active)
ICC1
tRC ≥ tRC(min)
IO = 0mA
Precharge standby current in
ICC2P
power-down mode
ICC2PS
CKE ≤ VIL(max)
2
mA
2
mA
tCC=10ns
CKE & CLK ≤ VIL(max)
tCC=∞
CKE ≥ VIH(min)
ICC2N
CS* ≥ VIH(min),
tCC=10ns
16
Input signals are changed
Precharge standby current in
one time during 20ns
non power-down mode
mA
CKE ≥ VIH(min)
ICC2NS
CLK ≤ VIL(max),
tCC=∞
14
Input signals are stable
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Active
HSD32M64D8A
standby
current
power-down mode
in
CKE ≤ VIL(max), tCC=10ns
ICC3P
ICC3PS
6
CKE&CLK ≤ VIL(max)
mA
6
tCC=∞
CKE≥VIH(min),
Active standby current in
CS*≥VIH(min),
ICC3N
tCC=10ns
30
Input signals are changed
non power-down mode
one time during 20ns
(One bank active)
CKE≥VIH(min)
ICC3NS
CLK ≤VIL(max),
mA
tCC=∞
25
Input signals are stable
IO = 0 mA
Operating current
Page burst
ICC4
(Burst mode)
140
140
115
115
mA
1
210
210
200
200
mA
2
4Banks Activated
tCCD = 2CLKs
Refresh current
ICC5
Self refresh current
ICC6
tRC ≥ tRC(min)
CKE ≤ 0.2V
5
mA
2
mA
Notes :
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Unless otherwise noticed, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ).
AC OPERATING TEST CONDITIONS
(vcc = 3.3V ± 0.3V, TA = 0 to 70° C)
PARAMETER
Value
UNIT
2.4/0.4
V
1.4
V
tr/tf = 1/1
ns
1.4
V
AC Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
See Fig. 2
+3.3V
1200Ω
Vtt=1.4V
DOUT
870Ω
50pF*
50Ω
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
(Fig. 1) DC output load circuit
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REV.1.0 (August.2002)
DOUT
Z0=50Ω
50pF
(Fig. 2) AC output load circuit
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HSD32M64D8A
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
VERSION
PARAMETER
SYMBOL
-13
-12
-10
-10L
UNIT
NOTE
Row active to row active delay
tRRD(min)
15
16
20
20
ns
1
RAS to CAS delay
tRP(min)
20
20
20
20
ns
1
Row precharge time
tRP(min)
20
20
20
20
ns
1
tRAS(min)
45
48
50
50
ns
1
Row active time
tRAS(max)
Row cycle time
100
tRC(min)
65
ns
68
70
70
ns
1
Last data in to row precharge
tRDL(min)
2
CLK
2.5
Last data in to Active delay
tDAL(min)
2 CLK + 20 ns
-
5
Last data in to new col. address delay
tCDL(min)
1
CLK
2
Last data in to burst stop
tBDL(min)
1
CLK
2
Col. address to col. address delay
tCCD(min)
1
CLK
3
ea
4
CAS latency=3
2
Number of valid output data
CAS latency=2
-
1
Notes :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and
then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. For -8/H/L, tRDL=1CLK and tDAL=1CLK+20ns is also supported .
(Recommand : tRDL=2CLK and tDAL=2CLK & 20ns.)
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted)
-13
PARAMETER
MIN
CAS
latency=3
CAS
latency=2
CLK to valid
CAS
output delay
latency=3
CAS
latency=2
Output data
CAS
hold time
latency=3
CAS
latency=2
CLK high pulse width
-12
-10
-10L
SYMBOL
CLK cycle time
MAX
7.5
tCC
MIN
MAX
8
1000
-
MIN
MAX
10
1000
-
MIN
UNIT
NOTE
ns
1
ns
1,2
ns
2
MAX
10
1000
10
1000
12
5.4
6
6
6
-
-
6
7
tSAC
2.7
3
3
3
-
-
3
3
tCH
2.5
3
3
3
ns
3
tCL
2.5
3
3
3
ns
3
Input setup time
tSS
1.5
2
2
2
ns
3
Input hold time
tSH
0.8
1
1
1
ns
3
CLK low pulse width
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tOH
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HANBit Electronics Co.,Ltd.
HANBit
HSD32M64D8A
CLK to output in Low-Z
CLK to output
CAS
in Hi-Z
latency=3
CAS
tSLZ
1
1
1
1
ns
3
2
5.4
6
6
6
ns
-
-
6
7
ns
tSHZ
latency=2
Notes :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered, ie., [(tr + tf)/2-1]ns should be added to
the parameter.
SIMPLIFIED TRUTH TABLE
CKE
n-1
COMMAND
Register
Mode register set
Auto refresh
Refresh
Entry
Self
refres
Exit
h
Bank active & row addr.
Read &
column
address
Write &
column
address
Auto
H
/C
S
/R
A
S
/C
A
S
/W
E
D
Q
M
X
L
L
L
L
X
OP code
L
L
L
H
X
X
L
H
H
H
H
X
X
X
X
X
H
L
BA
0,1
L
H
H
X
L
L
H
H
X
V
H
X
L
H
L
H
X
V
precharge
disable
Auto
H
CKE
n
precharge
Auto
H
X
L
H
L
L
X
precharge
X
L
L
H
L
X
H
X
L
L
H
L
X
Entry
H
L
Exit
L
H
Entry
H
L
Bank selection
e
All banks
Clock suspend or
active power down
Precharge
power
down mode
Exit
DQM
No operation command
3
3
3
3
Column
H
(A0 ~ A9)
L
Address
4,5
L
H
H
X
X
X
L
V
V
V
X
X
X
X
H
X
X
X
L
H
H
H
H
X
X
X
L
V
V
V
H
H
X
X
H
X
X
X
L
H
H
H
X
X
V
L
X
H
6
X
X
X
X
X
X
V
X
X
X
low)
Notes :
1. OP Code : Operand code
A0 ~ A12 & BA0 ~ BA1 : Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
-8-
4
4,5
(V=Valid, X=Don't care, H=Logic high, L=Logic
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4
(A0 ~ A9)
H
H
Precharg
1,2
Address
V
disable
Burst Stop
NOTE
Column
precharge
disable
A11,A12,
A9~A0
Row address
L
disable
Auto
A10/
AP
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HANBit
HSD32M64D8A
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected.
If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
TIMING DIAGRAMS
Please refer to attached timing diagram chart (II)
PACKAGING INFORMATION
Unit : mm
Front View
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HSD32M64D8A
ORDERING INFORMATION
Part Number
Density
Org.
Package
Ref.
Vcc
MODE
HMD32M64D8A-13
256Byte
32M x 64
168 Pin-DIMM
8K
3.3V
SDRAM
HMD32M64D8A-12
256Byte
32M x 64
168 Pin-DIMM
8K
3.3V
SDRAM
HMD32M64D8A-10L
256Byte
32M x 64
168 Pin-DIMM
8K
3.3V
SDRAM
HMD32M64D8A-10
256Byte
32M x 64
168 Pin-DIMM
8K
3.3V
SDRAM
HMD32M64D8A-F13
256Byte
32M x 64
168 Pin-DIMM
8K
3.3V
SDRAM
HMD32M64D8A-F12
256Byte
32M x 64
168 Pin-DIMM
8K
3.3V
SDRAM
HMD32M64D8A-F10L
256Byte
32M x 64
168 Pin-DIMM
8K
3.3V
SDRAM
HMD32M64D8A-F10
256Byte
32M x 64
168 Pin-DIMM
8K
3.3V
SDRAM
MAX.frq
CL3
133MHz
CL3
125MHz
CL3
100MHz
CL2
100MHz
CL3
133MHz
CL3
125MHz
CL3
100MHz
CL2
100MHz
F means Auto & Self refresh with Low-Power (3.3V)
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