Hanbit HMN1M8DV Non-volatile sram module 8mbit (1024k x 8bit) 36pin-dip, 3.3v Datasheet

HANBit
HMN1M8DV
Non-Volatile SRAM MODULE 8Mbit (1024k x 8bit) 36Pin – DIP, 3.3V
Part No. HMN1M8DV
GENERAL DESCRIPTION
The HMN1M8DV Nonvolatile SRAM is a 8,388,608-bit static RAM organized as 1,048,576 bytes by 8 bits.
The HMN1M8DV has a self-contained lithium energy source provide reliable non-volatility coupled with the unlimited write
cycles of standard SRAM and integral control circuitry which constantly monitors the single 3.3V supply for an out-oftolerance condition. When such a condition occurs, the lithium energy source is automatically switched on to sustain the
memory until after VCC returns valid and write protection is unconditionally enabled to prevent garbled data. In addition the
SRAM is unconditionally write-protected to prevent an inadvertent write operation. At this time the integral energy source is
switched on to sustain the memory until after VCC returns valid.
The HMN1M8DV uses extremely low standby current CMOS SRAM’s, coupled with small lithium coin cells to provide nonvolatility without long write-cycle times and the write-cycle limitations associated with EEPROM.
FEATURES
w Access time : 70, 85, 120, 150 ns
PIN ASSIGNMENT
w High-density design : 8Mbit Design
w Battery internally isolated until power is applied
w Industry-standard 36-pin 1,024K x 8 pinout
NC
NC
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
w Unlimited write cycles
w Data retention in the absence of VCC
w 10-years minimum data retention in absence of power
w Automatic write-protection during power-up/power-down
cycles
w Data is automatically protected during power loss
OPTIONS
MARKING
w Timing
70 ns
- 70
85 ns
- 85
120 ns
-100
150 ns
-150
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17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
VCC
A19
NC
A15
A17
/WE
A13
A8
A9
A11
/OE
A10
/CE
DQ7
DQ6
DQ5
DQ4
DQ3
36-pin Encapsulated Package
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HANBit
HMN1M8DV
FUNCTIONAL DESCRIPTION
The HMN1M8DV executes a read cycle whenever /WE is inactive(high) and /CE is active(low). The address specified by
the address inputs(A0-A19) defines which of the 1,048,576 bytes of data is accessed. Valid data will be available to the
eight data output drivers within tACC (access time) after the last address input signal is stable.
When power is valid, the HMN1M8DV operates as a standard CMOS SRAM. During power-down and power-up cycles,
the HMN1M8DV acts as a nonvolatile memory, automatically protecting and preserving the memory contents.
The HMN1M8DV is in the write mode whenever the /WE and /CE signals are in the active (low) state after address inputs
are stable. The later occurring falling edge of /CE or /WE will determine the start of the write cycle. The write cycle is
terminated by the earlier rising edge of /CE or /WE. All address inputs must be kept valid throughout the write cycle. /WE
must return to the high state for a minimum recovery time (tWR) before another cycle can be initiated. The /OE control
signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output bus been enabled
(/CE and /OE active) then /WE will disable the outputs in tODW from its falling edge.
The HMN1M8DV provides full functional capability for Vcc greater than 3.0 V and write protects by 2.8 V nominal. Powerdown/power-up control circuitry constantly monitors the Vcc supply for a power-fail-detect threshold VPFD. When VCC falls
below the VPFD threshold, the SRAM automatically write-protects the data. All inputs to the RAM become “don’t care” and
all outputs are high impedance. As Vcc falls below approximately 2.5V, the power switching circuit connects the lithium
energy soure to RAM to retain data. During power-up, when Vcc rises above approximately 2.5 volts, the power switching
circuit connects external Vcc to the RAM and disconnects the lithium energy source. Normal RAM operation can resume
after Vcc exceeds 3.0 volts.
BLOCK DIAGRAM
/OE
/WE
PIN DESCRIPTION
A19
/CE : Chip Enable
DQ0-DQ7
VSS : Ground
DQ0-DQ7 : Data In / Data Out
Power
/CE
A0-A19 : Address Input
A0-A19
2 x 512K x 8
SRAM
Block
/CE CON
Power – Fail
Control
/WE : Write Enable
VCC
/OE : Output Enable
VCC: Power (+5V)
Lithium
Cell
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HMN1M8DV
TRUTH TABLE
MODE
/OE
/CE
/WE
I/O OPERATION
POWER
Not selected
X
Output disable
H
H
X
High Z
Standby
L
H
High Z
Active
Read
L
L
H
DOUT
Active
Write
X
L
L
DIN
Active
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
VCC
-0.5V to Vcc+0.5
VT
-0.3V to 4.6V
Operating temperature
TOPR
0 to 70°C
Storage temperature
TSTG
-65°C to 150°C
TSOLDER
260°C
DC voltage applied on VCC relative to VSS
DC Voltage applied on any pin excluding VCC relative to
VSS
Soldering temperature
CONDITIONS
VT≤ VCC+0.3
For 10 second
NOTE: Permanent device damage may occur if Absolute Maximum Ratings are exceeded.
Functional operation should be restricted to the Recommended DC Operating Conditions detailed in this data sheet.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS ( TA= TOPR )
PARAMETER
SYMBOL
MIN
TYPICAL
MAX
Supply Voltage
VCC
3.0V
3.3V
3.6V
Ground
VSS
0
0
0
Input high voltage
VIH
2.2
-
VCC+0.3
Input low voltage
VIL
-0.3
-
0.6V
NOTE: Typical values indicate operation at TA = 25℃
CAPACITANCE (TA=25℃ , f=1MHz, VCC=3.3V)
DESCRIPTION
Input Capacitance
Input/Output Capacitance
CONDITIONS
SYMBOL
MAX
MIN
UNIT
Input voltage = 0V
CIN
8
-
pF
Output voltage = 0V
CI/O
10
-
pF
1. Only sampled, not 100% tested
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HMN1M8DV
DC ELECTRICAL CHARACTERISTICS (TA= TOPR, VCCmin £ VCC≤ VCCmax )
PARAMETER
CONDITIONS
Input Leakage Current
VIN=VSS to VCC
Output Leakage Current
/CE=VIH or /OE=VIH
or /WE=VIL
SYMBOL
MIN
TYP.
MAX
UNIT
ILI
-
-
± 3.0
mA
ILO
-
-
± 3.0
mA
Output high voltage
IOH=-1.0mA
VOH
2.4
-
-
V
Output low voltage
IOL= 2.0mA
VOL
-
-
0.4
V
VPFD
2.8
2.9
3.0
V
ISB
-
-
0.6
㎃
ISB1
-
-
30
mA
ICC
-
12
㎃
VSO
-
-
V
Threshold
Power-fail Deselect Voltage
Select
Voltage
(THS = VSS )
Standby supply current
/CE=2.2v
/CE≥ VCC-0.2V,
0V≤ VIN≤ 0.2V,
Standby supply current
or VIN≥ VCC-0.2V
Operating
Power
supply
current
/CE=VIL, II/O=0㎃ ,
VIN = VIL or VIH, Read
Supply switch-over voltage
2.5
CHARACTERISTICS (Test Conditions)
+5V
PARAMETER
Input pulse levels
VALUE
0.4 to 2.2V
Input rise and fall times
5 ns
Input and output timing reference
levels
5V
( unless otherwise specified)
1)
Output load (CL =30pF+1TTL)
1)
(CL =100pF+1TTL)
+5V
See Figures
1.9KΩ
DOUT
100㎊
1KΩ
1.9KΩ
DOUT
5㎊
1KΩ
Figure 1.
Figure 2.
Output Load A
Output Load B
Note : Including scope and jig capacitance
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HMN1M8DV
READ CYCLE (TA= TOPR, VCCmin £ VCC≤ VCCmax )
PARAMETER
SYMBOL
Read Cycle Time
tRC
Address Access Time
tACC
Chip enable access time
Output enable to Output valid
CONDITIONS
-70
-85
-120
-150
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
70
-
85
-
120
-
150
-
ns
Output load A
-
70
-
85
-
120
-
150
ns
tACE
Output load A
-
70
-
85
-
120
-
150
ns
tOE
Output load A
-
35
-
45
-
60
-
70
ns
Chip enable to output in low Z
tCLZ
Output load B
5
-
5
-
5
-
10
-
ns
Output enable to output in low Z
tOLZ
Output load B
5
-
0
-
0
-
5
-
ns
Chip disable to output in high Z
tCHZ
Output load B
0
25
0
35
0
45
0
60
ns
Output disable to output high Z
tOHZ
Output load B
0
25
0
25
0
35
0
50
ns
Output hold from address change
tOH
Output load A
10
-
10
-
10
-
10
-
ns
WRITE CYCLE (TA= TOPR, Vccmin £ Vcc ≤ Vccmax )
PARAMETER
SYMBOL
Write Cycle Time
tWC
Chip enable to end of write
tCW
Address setup time
CONDITIONS
-70
-85
-120
-150
UNI
MIN
MAX
MIN
MAX
MIN
MAX
Min
Max
T
70
-
85
-
120
-
150
-
ns
Note 1
65
-
75
-
100
-
100
-
ns
tAS
Note 2
0
-
0
-
0
-
0
-
ns
Address valid to end of write
tAW
Note 1
65
-
75
-
100
-
90
-
ns
Write pulse width
tWP
Note 1
55
-
65
-
85
-
90
-
ns
Write recovery time (write cycle 1)
tWR1
Note 3
5
-
5
-
5
-
5
-
ns
Write recovery time (write cycle 2)
tWR2
Note 3
15
-
15
-
15
-
15
-
ns
Data valid to end of write
tDW
30
-
35
-
45
-
50
-
ns
Data hold time (write cycle 1)
tDH1
Note 4
0
-
0
-
0
-
0
-
ns
Data hold time (write cycle 2)
tDH2
Note 4
10
-
10
-
10
-
0
-
ns
Write enabled to output in high Z
tWZ
Note 5
0
25
0
30
0
40
0
50
ns
Output active from end of write
tOW
Note 5
5
-
0
-
0
-
5
-
ns
NOTE: 1. A write ends at the earlier transition of /CE going high and /WE going high.
2. A write occurs during the overlap of allow /CE and a low /WE. A write begins at the later transition of /CE
going low and /WE going low.
3. Either tWR1 or tWR2 must be met.
4. Either tDH1 or tDH2 must be met.
5. If /CE goes low simultaneously with /WE going low or after /WE going low, the outputs remain in highimpedance state.
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HMN1M8DV
POWER-DOWN/POWER-UP CYCLE
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP.
MAX
UNIT
VPFD(max) to VPFD(min) VCC Fail Time
tF
300
-
-
ms
VPFD(max) to VSS VCC Fail Time
tFB
150
-
-
ms
VPFD(max) to VPFD(min) VCC Rise Time
tR
10
-
-
ms
250
ms
Delay after Vcc slews down
Write Protect Time
tWPT
past VPFD before SRAM is
40
Write-protected.
Chip Enable Recovery
tCER
40
-
120
ms
VSS to VPFD (min) VCC Rise Time
tRB
1
-
-
ms
TIMING WAVEFORM
- READ CYCLE NO.1 (Address Access)*1,2
tRC
Address
tACC
tOH
Previous Data Valid
DOUT
Data Valid
- READ CYCLE NO.2 (/CE Access)*1,3,4
tRC
/CE
tACE
tCHZ
tCLZ
DOUT
High-Z
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HMN1M8DV
- READ CYCLE NO.3 (/OE Access)*1,5
tRC
Address
tACC
/OE
tOE
DOUT
tOHZ
tOLZ
Data Valid
High-Z
High-Z
NOTES: 1. /WE is held high for a read cycle.
2. Device is continuously selected: /CE = /OE =VIL.
3. Address is valid prior to or coincident with /CE transition low.
4. /OE = VIL.
5. Device is continuously selected: /CE = VIL
- WRITE CYCLE NO.1 (/WE-Controlled)*1,2,3
tWC
Address
tAW
tWR1
tCW
/CE
tAS
tWP
/WE
tDW
DIN
Data-in Valid
tWZ
DOUT
Data Undefined (1)
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tDH1
7
tOW
High-Z
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HMN1M8DV
- WRITE CYCLE NO.2 (/CE-Controlled)*1,2,3,4,5
Address
tAW
tAS
tWR2
tCW
/CE
tWP
/WE
tDH2
tDW
Data-in
DIN
tWZ
DOUT
Data
NOTE:
High-Z
Undefined
1. /CE or /WE must be high during address transition.
2. Because I/O may be active (/OE low) during this period, data input signals of opposite
polarity to the outputs must not be applied.
3. If /OE is high, the I/O pins remain in a state of high impedance.
4. Either tWR1 or tWR2 must be met.
5. Either tDH1 or tDH2 must be met.
POWER-DOWN/POWER-UP TIMING
VCC
tPF
4.75
VPFD
VPFD
4.25
VSO
VSO
tFS
tPU
tCER
tDR
tWPT
/CE
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HMN1M8DV
PACKAGE DIMENSION
Dimension
Min
Max
A
2.070
2.100
B
0.710
0.740
C
0.365
0.375
D
0.015
-
E
0.008
0.013
F
0.590
0.630
G
0.017
0.023
H
0.090
0.110
I
0.080
0.110
J
0.120
0.150
J
A
H
I
G
C
D
B
E
F
All dimensions are in inches.
ODERING INFORMATION
H M N 1 M 8 DV – 70 I
Operating Temperature : I = Industrial Temp. (-40~85 °C )
Blank = Commercial Temp. (0~70°C)
Speed options : 70 = 70 ns
85 = 85ns
120 = 120ns
150 = 150ns
3.3V Dip type package
Device : 1,024K x 8 bit
Nonvolatile SRAM
HANBit Memory Module
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