Hanbit HMS1M32Z8V-15 Sram module 4mbyte(1m x 32-bit) 3.3v Datasheet

HANBit
HMS1M32M8V
HAN
SRAM MODULE 4Mbyte(1M x 32-Bit) 3.3V
BIT
Part No.
HMS1M32M8V, HMS1M32Z8V
GENERAL DESCRIPTION
The HMS1M32M8V is a high-speed static random access memory (SRAM) module containing 1,048,576 words
organized in a x32-bit configuration. The module consists of eight 1M x 4 SRAMs mounted on a 72-pin, doublesided, FR4-printed circuit board.
PD0 to PD3 identify the module’s density allowing interchangeable use of alternate density, industry- standard
modules. Eight chip enable inputs, (/CE1, /CE2, /CE3 and /CE4) are used to enable the module’s 4 bytes
independently. Output enable (/OE) and write enable(/WE) can set the memory input and output.
Data is written into the SRAM memory when write enable (/WE) and chip enable (/CE) inputs are both LOW.
Reading is accomplished when /WE remains HIGH and /CE and output enable (/OE) are LOW.
For reliability, this SRAM module is designed as multiple power and ground pin. All module components may be
powered from a single +3.3V DC power supply and all inputs and outputs are fully LVTTL-compatible.
PIN ASSIGNMENT
FEATURES
Š Part identification
- HMS1M32M8V : SIMM design
- HMS1M32Z8V : ZIP design
→ Pin-Compatible with the HMS1M32M8V
Š Fast access times : 10, 12ns and 15ns
Š High-density 4MByte design
Š High-reliability high-speed design
Š Single + 3.3V ±0.3V power supply
Š Easy memory expansion /CE and /OE functions
Š All inputs and outputs are LVTTL-compatible
Š Industry-standard pinout
Š FR4-PCB design
Š Low power Dissipation
OPTIONS
MARKING
Š Timing
10ns access
-10
12ns access
-12
15ns access
-15
/CE4
/CE3
A17
A16
/OE
Vss
DQ24
DQ16
DQ25
DQ17
DQ26
DQ18
DQ27
DQ19
A3
A10
A4
A11
A5
A12
Vcc
A13
A6
DQ20
DQ28
DQ21
DQ29
DQ22
DQ30
DQ23
DQ31
Vss
A18
A19
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
SIMM
TOP VIEW
Š Packages
72-pin SIMM
NC
NC
PD2
PD3
Vss
PD0
PD1
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
Vcc
A0
A7
A1
A8
A2
A9
DQ12
DQ4
DQ13
DQ5
DQ14
DQ6
DQ15
DQ7
Vss
/WE
A15
A14
/CE2
/CE1
M
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
PD0 = Vss
PD1 = Open
PD2 = Vss
PD3 = Open
HANBit Electronics Co.,Ltd.
HANBit
HMS1M32M8V
FUNCTIONAL BLOCK DIAGRAM
DQ0 - DQ31
A0 - A19
32
20
A0-19
A0-19
DQ 0-3
DQ 4-7
/WE
/WE
U1
/OE
U5
/OE
/CE
/CE
/CE1
A0-19
A0-19
DQ 8-11
DQ12-15
/WE
/WE
U2
/OE
U6
/OE
/CE
/CE
/CE2
A0-19
A0-19
DQ16-19
DQ20-23
/WE
/WE
U3
/OE
U7
/OE
/CE
/CE
/CE3
A0-19
A0-19
DQ24-27
/WE
/WE
/OE
/OE
DQ28-31
/WE
U4
/OE
/CE
U8
/CE
/CE4
MODE
/OE
/CE
/WE
OUTPUT
POWER
STANDBY
X
H
X
HIGH-Z
STANDBY
NOT SELECTED
H
L
H
HIGH-Z
ACTIVE
READ
L
L
H
Dout
ACTIVE
WRITE
X
L
L
Din
ACTIVE
HANBit Electronics Co.,Ltd.
HANBit
HMS1M32M8V
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
VIN,OUT
-0.5V to +4.6V
Voltage on Vcc Supply Relative to Vss
VCC
-0.5V to +4.6V
Power Dissipation
PD
8W
TSTG
-65oC to +150oC
Voltage on Any Pin Relative to Vss
Storage Temperature
Operating Temperature
TA
0oC to +70oC
Š Stresses greater than those listed under " Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated
in the operating section of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER
*
( TA=0 to 70 o C )
SYMBOL
MIN
TYP.
MAX
Supply Voltage
VCC
3.0V
3.3V
3.6V
Ground
VSS
0
0
0
Input High Voltage
VIH
2.0
-
Vcc+0.3V**
Input Low Voltage
VIL
-0.3*
-
0.8V
VIL(Min.) = -2.0V (Pulse Width ≤ 10ns) for I ≤ 20 mA
** VIH(Min.) = Vcc+2.0V (Pulse Width ≤ 10ns) for I ≤ 20 mA
DC AND OPERATING CHARACTERISTICS (1)(0oC ≤ TA ≤ 70 oC ; Vcc = 3.3V ± 0.3V )
PARAMETER
Input Leakage Current
Output Leakage Current
TEST CONDITIONS
VIN = Vss to Vcc
/CE=VIH or /OE =VIH or /WE=VIL
VOUT=Vss to VCC
SYMBO
L
MIN
MAX
UNITS
ILI
-2
2
µA
IL0
-2
2
µA
2.4
Output High Voltage
IOH = -4.0Ma
VOH
Output Low Voltage
IOL = 8.0mA
VOL
V
0.4
V
* Vcc=3.3V, Temp=25 oC
HANBit Electronics Co.,Ltd.
HANBit
HMS1M32M8V
DC AND OPERATING CHARACTERISTICS (2)
MAX
DESCRIPTION
TEST CONDITIONS
Min. Cycle, 100% Duty
/CE=VIL, VIN=VIH or VIL,
IOUT=0mA
Power Supply
Current:Operating
Power Supply
Current:Standby
SYMBOL
-12
-15
-20
UNIT
lCC
150
145
140
mA
Min. Cycle, /CE=VIH
lSB
70
70
70
mA
f=0MHZ, /CE≥VCC-0.2V,
VIN≥ VCC-0.2V or VIN≤0.2V
lSB1
20
20
20
mA
CAPACITANCE
DESCRIPTION
TEST CONDITIONS
SYMBOL
MAX
UNIT
Input /Output Capacitance
VI/O=0V
CI/O
8
pF
Input Capacitance
VIN=0V
CIN
7
pF
* NOTE : Capacitance is sampled and not 100% tested
AC CHARACTERISTICS (0oC ≤ TA ≤ 70 oC ; Vcc = 3.3V ± 0.3V, unless otherwise specified)
TEST CONDITIONS
PARAMETER
VALUE
Input Pulse Level
0 to 3V
Input Rise and Fall Time
3ns
Input and Output Timing Reference Levels
1.5V
Output Load
See below
Output Load (B)
Output Load (A)
for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ
VL=1.5V
+3.3V
50Ω
DOUT
319Ω
DOUT
Z0=50Ω
30pF
353Ω
5pF*
HANBit Electronics Co.,Ltd.
HANBit
HMS1M32M8V
READ CYCLE
-12
PARAMETER
-15
-20
SYMBOL
UNIT
MIN
MAX
12
MIN
MAX
15
MIN
MAX
Read Cycle Time
tRC
20
Address Access Time
tAA
12
15
20
ns
Chip Select to Output
tCO
12
15
20
ns
Output Enable to Output
tOE
6
7
9
ns
Output Enable to Low-Z Output
tOLZ
0
0
0
ns
Chip Enable to Low-Z Output
tLZ
3
3
3
ns
Output Disable to High-Z Output
tOHZ
0
6
0
7
0
9
ns
Chip Disable to High-Z Output
tHZ
0
6
0
7
0
9
ns
Output Hold from Address Change
tOH
3
3
3
ns
Chip Select to Power Up Time
tPU
0
0
0
ns
Chip Select to Power Down Time
tPD
12
ns
15
20
ns
WRITE CYCLE
-12
PARAMETER
-15
-20
SYMBOL
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
Write Cycle Time
tWC
12
15
20
ns
Chip Select to End of Write
tCW
8
10
12
ns
Address Set-up Time
tAS
0
0
0
ns
Address Valid to End of Write
tAW
8
10
12
ns
Write Pulse Width
tWP
8
10
12
ns
Write Recovery Time
tWR
0
0
0
ns
Write to Output High-Z
tWHZ
0
Data to Write Time Overlap
tDW
6
7
9
ns
Data Hold from Write Time
tDH
0
0
0
ns
End of Write to Output Low-Z
tOW
3
3
3
ns
6
0
7
0
9
ns
HANBit Electronics Co.,Ltd.
HANBit
HMS1M32M8V
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE( Address Controlled)( /CE =/OE = VIL , /WE = VIH)
tRC
Address
tAA
tOH
Data out
Previous Data Valid
Data Valid
TIMING WAVEFORM OF READ CYCLE ( /WE = VIH )
tRC
Address
tHZ(3,4,5)
tAA
tCO
/CE
tLZ(4,5)
tOHZ
tOE
/OE
tOH
tOLZ
Data Out
Vcc Supply
Current
High-Z
Data Valid
lCC
lSB
tPU
50%
tPD
50%
Notes (Read Cycle)
1. /WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to first transition address.
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH
or VOL levels.
4. At any given temperature and voltage condition, tHZ (max.) is less than tLZ (min.) both for a given device and from device
to device.
5. Transition is measured ± 200mV from steady state voltage with Load (B). This parameter is sampled and not 100%
tested.
6. Device is continuously selected with /CE = VIL.
7. Address valid prior to coincident with /CE transition low.
HANBit Electronics Co.,Ltd.
HANBit
HMS1M32M8V
TIMING WAVEFORM OF WRITE CYCLE (/OE = Clock )
tWC
Address
tAW
tWR(5)
/OE
tCW(3)
/CE
tAS(4)
tWP(2)
/WE
tDW
tDH
High-Z
Data In
Data Valid
tOHZ
tOW
Data Out
High-Z
TIMING WAVEFORM OF WRITE CYCLE (/OE Low Fixed)
tWC
Address
tAW
tWR(5)
tCW(3)
/CE
tAS(4)
tOH
/WE
tWP(2)
tDW
Data In
tDH
High-Z
Data Valid
tWHZ(6,7)
Data Out
tOW
(10)
(9)
High-Z(8)
Notes(Write Cycle)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low /CE and a low /WE. A write begins at the latest transition among
/CE going low and /WE going low: A write ends at the earliest transition among /CE going high and /WE going high.
tWP is measured from the beginning of write to the end of write.
3. tCW is measured from the later of /CE going low to the end of write.
4. tAS is measured from the address valid to the beginning of wirte.
5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CE, or /WE going high.
6. If /OE,/CE and /WE are in the read mode during this period, the I/O pins are in the output low-Z state. Inputs of
HANBit Electronics Co.,Ltd.
HANBit
HMS1M32M8V
opposite phase of the output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and
write cycle.
8. If /CE goes low simultaneously with /WE going low or after /WE going low, the outputs remain high impedance state.
9. DOUT is the read data of the new address.
10. When /CE is low: I/O pins are in the output state. The input signals in the opposite phase leading to the output
should not be applied.
FUNCTIONAL DESCRIPTION
/CE
/WE
/OE
MODE
I/O PIN
SUPPLY CURRENT
H
X*
X
Not Select
High-Z
l SB, l SB1
L
H
H
Output Disable
High-Z
lCC
L
H
L
Read
DOUT
lCC
L
L
X
Write
DIN
lCC
Note: X means Don't Care
PACKAGING DIMMENSIONS
SIMM Design
108.20 mm
3.18 mm
TYP(2x)
16 mm
6.35 mm
1
72
2.03 mm
1.02 mm
6.35 mm
1.27 mm
3.34 mm
95.25 mm
2.54 mm
0.25 mm MAX
MIN
1.29 mm
Gold : 1.04±0.10 mm
1.27
Solder : 0.914±0.10 mm
(Solder & Gold Plating Lead)
HANBit Electronics Co.,Ltd.
HANBit
HMS1M32M8V
ORDERING INFORMATION
1
2
3
HMS
4
5
6
7
8
1M 32 M8V-15
15ns Access Time
HANBit
Component, 3.3V
Memory
Modules
SIMM
SRAM
x32bit
1M
1. - Product Line Identifier
HANBit ------------------------------------------------------- H
2. - Memory Modules
3. - SRAM
4. - Depth : 1M
5. - Width : x 32bit
6. - Package Code
SIMM ------------------------------------------------------- M
ZIP
------------------------------------------------------- Z
7. - Number of Memory Components, 3.3V --------------V
8. - Access time
10 ----------------------------------------------------------- 10ns
12 ----------------------------------------------------------- 12ns
15 ----------------------------------------------------------- 15ns
17 ----------------------------------------------------------- 17ns
20 ----------------------------------------------------------- 20ns
HANBit Electronics Co.,Ltd.
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