Hynix HMS77C1000A 8-bit single-chip microcontroller Datasheet

8-BIT SINGLE-CHIP MICROCONTROLLERS
HMS77C1000A
HMS77C1001A
User’s Manual (Ver. 2.0)
Version 1.1
Published by
MCU Application Team
2001 Hynix Semiconductor All right reserved.
Additional information of this manual may be served by Hynix Semiconductor offices in Korea or Distributors and Representatives listed
at address directory.
Hynix Semiconductor reserves the right to make changes to any information here in at any time without notice.
The information, diagrams and other data in this manual are correct and reliable; however, Hynix Semiconductor is in no way responsible
for any violations of patents or other rights of the third party generated by the use of this manual.
HMS77C1000A/HMS77C1001A
Contents of Table
OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . 1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Port RB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
I/O Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . 24
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
I/O Successive Operations . . . . . . . . . . . . . . . 24
BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . 2
TIMER0 MODULE AND TMR0 REGISTER 26
PIN ASSIGNMENT . . . . . . . . . . . . . . . . . . . 3
Timer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 27
PACKAGE DIAGRAM . . . . . . . . . . . . . . . . . 4
Counter Mode . . . . . . . . . . . . . . . . . . . . . . . . 27
PIN FUNCTION . . . . . . . . . . . . . . . . . . . . . . 6
Using Timer0 with an External Clock . . . . . . . 28
Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
PORT STRUCTURES . . . . . . . . . . . . . . . . . 7
CONFIGURATION AREA . . . . . . . . . . . . . 30
ELECTRICAL CHARACTERISTICS . . . . . . 9
OSCILLATOR CIRCUITS . . . . . . . . . . . . . 31
Absolute Maximum Ratings . . . . . . . . . . . . . . . 9
XT, HF or LF Mode . . . . . . . . . . . . . . . . . . . . 31
Recommended Operating Conditions . . . . . . . 9
RC Oscillation Mode . . . . . . . . . . . . . . . . . . . 31
DC Characteristics (1). . . . . . . . . . . . . . . . . . . 10
DC Electrical Characteristics (2) . . . . . . . . . . 11
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
AC Electrical Characteristics (1) . . . . . . . . . . 12
Power-On Reset (POR) . . . . . . . . . . . . . . . . . 34
Internal Reset Timer (IRT) . . . . . . . . . . . . . . . 36
AC Electrical Characteristics (2) . . . . . . . . . . 13
Typical Characteristics . . . . . . . . . . . . . . . . . . 14
WATCHDOG TIMER (WDT) . . . . . . . . . . . 37
ARCHITECTURE . . . . . . . . . . . . . . . . . . . 17
WDT Period . . . . . . . . . . . . . . . . . . . . . . . . . . 37
CPU Architecture . . . . . . . . . . . . . . . . . . . . . . 17
MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Program Memory . . . . . . . . . . . . . . . . . . . . . . 18
Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . 18
Special Function Registers . . . . . . . . . . . . . . 19
I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . 24
Port RA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Oct. 2001 Ver. 2.0
WDT Programming Considerations . . . . . . . . 37
Power-Down Mode (SLEEP) . . . . . . . . . . 38
SLEEP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Wake-up From SLEEP . . . . . . . . . . . . . . . . . . 39
Minimizing Current Consumption . . . . . . . . . . 39
TIME-OUT SEQUENCE AND POWER DOWN
STATUS BITS (TO/PD) . . . . . . . . . . . . . 41
POWER FAIL DETECTION PROCESSOR 42
HMS77C1000A/HMS77C1001A
HMS77C1000A / HMS77C1001A
CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
1. OVERVIEW
1.1 Description
The HMS77C1000A and HMS77C1001A are an advanced CMOS 8-bit microcontroller with 0.5K/1K words(12-bit) of
EPROM. The Hynix Semiconductor HMS77C1000A and HMS77C1001A are a powerful microcontroller which provides a
high flexibility and cost effective solution to many small applications. The HMS77C1000A and HMS77C1001A provide the
following standard features: 0.5K/1K words of EPROM, 25 bytes of RAM, 8-bit timer/counter, power-on reset, on-chip oscillator and clock circuitry. In addition, the HMS77C1000A and HMS77C1001A supports power saving modes to reduce
power consumption.
Device name
ROM Size
RAM Size
Package
HMS77C1000A
0.5K words(12-bit)
25 bytes
18 PDIP, SOP or 20 SSOP
HMS77C1001A
1K words(12-bit)
25 bytes
18 PDIP, SOP or 20 SSOP
1.2 Features
• High-Performance RISC CPU:
-
Internal Reset Timer (IRT)
-
Watchdog Timer (WDT) with on-chip RC oscillator
-
12-bit wide instructions and 8-bit wide data path
-
33 single word instructions
-
0.5K/1K words on-chip program memory
-
Programmable code-protection
-
25 bytes on-chip data memory
-
Power saving SLEEP mode
-
Minimum instruction execution time
200ns @20MHz
-
Selectable oscillator options: Configuration word
-
Operating speed: DC - 20 MHz clock input
-
Seven special function hardware registers
-
Two-level hardware stack
RC: Low-cost RC oscillator (200KHz~4MHz)
XT: Standard crystal/resonator (455KHz~4MHz)
HF: High-speed crystal/resonator (4~20MHz)
LF: Power saving, low-frequency crystal/resonator
(32~200KHz)
• CMOS Technology:
• Peripheral Features:
-
Twelve programmable I/O lines
-
One 8-bit timer/counter with 8-bit programmable
prescaler
-
Power-On Reset (POR)
-
Power Fail Detector : noise immunity circuit
2 level detect ( 2.7V, 1.8V )
Oct. 2001 Ver. 2.0
-
Low-power, high-speed CMOS EPROM technology
-
Fully static design
-
Wide-operating range:
2.5V to 5.5V @ RC, XT, LF
4.5V to 5.5V @ HF
1
HMS77C1000A/HMS77C1001A
2. BLOCK DIAGRAM
OPTION
STATUS
ALU
8-bit
Timer/
Counter
PC
STACK 1
Data
STACK 2
Memory
Power Fail Detector
RESET
System controller
Xin
Clock Generator
Timing Control
Xout
VDD
Program
Memory
W
WDT/
TMR0
Prescaler
WDT time out
Watch-dog
Timer
Instruction
Decoder
Configuration Word
VSS
Power
Supply
RA
RA0
RA1
RA2
RA3
2
TRISA
RB
EC0
TRISB
RB0
RB1
RB2
RB3
RB4
RB5
RB6
RB7
Oct. 2001 Ver. 2.0
HMS77C1000A/HMS77C1001A
3. PIN ASSIGNMENT
18 PDIP or SOP
RA2
1
18
RA1
RA3
2
17
RA0
EC0
3
16
Xin
RESET/VPP
4
15
Xout
VSS
5
14
VDD
RB0
6
13
RB7
RB1
7
12
RB6
RB2
8
11
RB5
RB3
9
10
RB4
20 SSOP
Oct. 2001 Ver. 2.0
RA2
1
20
RA1
RA3
2
19
RA0
EC0
3
18
Xin
RESET/VPP
4
17
Xout
VSS
5
16
VDD
VSS
6
15
VDD
RB0
7
14
RB7
RB1
8
13
RB6
RB2
9
12
RB5
RB3
10
11
RB4
3
HMS77C1000A/HMS77C1001A
4. PACKAGE DIAGRAM
18 PDIP
unit: inch
MAX
MIN
TYP 0.300
0.925
0.270
0.245
0.120
0.140
MAX 0.180
MIN 0.020
0.895
5
0.01
8
0.00
0.022
0.065
0.015
0 ~ 15°
TYP 0.10
0.045
4
0.410
0.400
0.292
0 ~ 8°
TYP 0.050
0.0125
0.029
0.014
0.0091
0.104
0.097
0.461
0.451
0.0115
0.005
0.299
18 SOP
0.040
0.024
Oct. 2001 Ver. 2.0
HMS77C1000A/HMS77C1001A
20 SSOP
unit: inch
MAX
Oct. 2001 Ver. 2.0
0.311
0.301
0.205
0 ~ 8°
TYP 0.0256
0.008
0.015
0.010
0.004
0.078
0.068
0.289
0.278
0.008
0.002
0.212
MIN
0.037
0.025
5
HMS77C1000A/HMS77C1001A
5. PIN FUNCTION
VDD: Supply voltage.
RA pins can be used as outputs or inputs according to “0”
or “1” written the their Port Direction Register(TRISA).
VSS: Circuit ground.
RESET: Reset the MCU.
XIN: Input to the inverting oscillator amplifier and input to
the internal main clock operating circuit.
XOUT: Output from the inverting oscillator amplifier.
RA0~RA3: RA is an 4-bit, CMOS, bidirectional I/O port.
RB0~RB7: RB is a 8-bit, CMOS, bidirectional I/O port.
RB pins can be used as outputs or inputs according to “0”
or “1” written the their Port Direction Register(TRISB).
EC0: EC0 is an external clock input to Timer0. It should
be tied to VSS or VDD, if not in use, to reduce current consumption.
PIN NAME
DIP, SOP
Pin No.
SSOP
Pin No.
In/Out
Input
Levels
VDD
14
15,16
P
-
Supply voltage
VSS
5
5,6
P
-
Circuit ground
RESET
4
4
I
ST
Reset signal input/programming voltage input. This pin is an active low
reset to the device. Voltage on the RESET pin must not exceed VDD to
avoid unintended entering of programming mode.
XIN
16
18
I
ST
Oscillator crystal input/external clock source input
XOUT
15
17
O
-
RA0
17
19
I/O
TTL
RA1
18
20
I/O
TTL
RA2
1
1
I/O
TTL
RA3
2
2
I/O
TTL
RB0
6
7
I/O
TTL
RB1
7
8
I/O
TTL
Function
Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, XOUT pin outputs CLKOUT which has 1/4 the frequency of XIN, and denotes the instruction cycle rate.
4-bit bi-directional I/O ports
RB2
8
9
I/O
TTL
RB3
9
10
I/O
TTL
RB4
10
11
I/O
TTL
RB5
11
12
I/O
TTL
RB6
12
13
I/O
TTL
RB7
13
14
I/O
TTL
EC0
3
3
I
ST
8-bit bi-directional I/O ports
Clock input to Timer0. Must be tied to VDD or VSS, if not in use, to reduce
current consumption.
TABLE 5-1 PINOUT DESCRIPTION
Legend : I =input, O = output, I/O = input/output, P = power, - = Not used, TTL = TTL input, ST = Schmitt Trigger input
6
Oct. 2001 Ver. 2.0
HMS77C1000A/HMS77C1001A
6. PORT STRUCTURES
• RESET
Internal RESET
VSS
• Xin, Xout
( XT, HF, LF Mode )
VDD
EN ( XT, HF, LF )
Xout
To Internal Clock
RF
VSS
Amplifier varies with
the oscillation mode
Xin
( RC Mode )
EN ( RC )
VDD
÷4
Xout
VSS
Internal
Capacitance ( appx. 6pF )
To Internal Clock
Oct. 2001 Ver. 2.0
Xin
7
HMS77C1000A/HMS77C1001A
• RA0~3/RB0~7
VDD
Data Reg.
Data Bus
Direction Reg.
Data Bus
VSS
Data Bus
Read
• EC0
VDD
EC0
Timer Counter Clock Input
VSS
8
Oct. 2001 Ver. 2.0
HMS77C1000A/HMS77C1001A
7. ELECTRICAL CHARACTERISTICS
7.1 Absolute Maximum Ratings
Supply voltage .............................................. -0 to +7.5 V
Maximum current (ΣIOL) .................................... 120 mA
Storage Temperature ................................-65 to +125 °C
Maximum current (ΣIOH)...................................... 80 mA
Voltage on RESET with respect to VSS .......0.3 to 13.5V
Voltage on any pin with respect to VSS. -0.3 to VDD+0.3
Maximum current out of VSS pin ........................150 mA
Maximum current into V DD pin ..........................100 mA
Maximum output current sunk by (I OL per I/O Pin)25 mA
Maximum output current sourced by (IOH per I/O Pin)
...............................................................................20 mA
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at any other conditions above
those indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods
may affect device reliability.
7.2 Recommended Operating Conditions
Specifications
Parameter
Supply Voltage
Operating Frequency
Operating Temperature
Oct. 2001 Ver. 2.0
Symbol
VDD
fXIN
TOPR
Condition
Unit
Min.
Max.
fXIN=20MHz
4.5
5.5
fXIN=4MHz
2.5
5.5
RC Mode
0.2
4
XT Mode
0.455
4
HF Mode
4
20
LF Mode
32
200
KHz
-40
85
°C
V
MHz
9
HMS77C1000A/HMS77C1001A
7.3 DC Characteristics (1)
• (TA=-40°°C~+85°°C)
Specification
Parameter
Symbol
Test Condition
Min
Typ1
Max
Unit
Supply Voltage
XT, RC, LF
VDD
HF
2.5
5.5
4.5
5.5
V
VDD start voltage to ensure
Power-On Reset
VPOR
-
VSS
-
V
VDD rise rate
SVDD2
0.05
-
-
V/mS
VDR
-
1.5
-
V
VPFD
-
2.7
-
V
-
1.8
-
XIN = 4MHz, VDD = 5V
-
1.8
3.3
mA
XIN = 20MHz, VDD = 5V
-
9.0
20
mA
XIN = 32KHz, VDD = 3V, WDT Disabled
-
17
40
uA
VDD = 3V, WDT Enabled
-
4
14
VDD = 3V, WDT Disabled
-
0.4
5
RAM Data Retention
Voltage
Power Fail Detection
Normal Level
Low Level
Supply Current
XT, RC4
HF
IDD3
LF
Power Down Current
1.
2.
3.
4.
5.
10
IPD5
uA
Data in “Typ” column is at 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
This parameter is characterized but not tested.
The test conditions for all IDD measurements in NOP execution are:
XIN = external square wave; all I/O pins tristated, pulled to VSS, EC0 = VDD, RESET = VDD; WDT disabled/enabled as specified.
Does not include current through Rext. The current through the resistor can be estimated by the formula; IR = VDD/2Rext (mA)
Power down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS as
like measurement conditions of supply current.
Oct. 2001 Ver. 2.0
HMS77C1000A/HMS77C1001A
7.4 DC Electrical Characteristics (2)
• (TA=-40°°C~+85°°C)
Specification
Parameter
Symbol
Test Condition
Min
Typ1
Max
Unit
Input High Voltage
0.25VDD +0.8
I/O Ports (TTL)
RESET, EC0, (ST)
0.85VDD
VIH
XIN (ST)
RC only
0.85VDD
XIN (ST)
XT, HF, LF
0.7VDD
VDD
V
Input Low Voltage
0.15VDD
I/O Ports (TTL)
RESET, EC0, (ST)
VSS
VIL
0.15VDD
XIN (ST)
RC only
0.15VDD
XIN (ST)
XT, HF, LF
0.3VDD
Hysteresis of Schmitt
Trigger Inputs
V
VIN = VDD or VSS
Input Leakage Current
XIN (ST)
0.15VDD2
VHYS
V
IL
XT, HF, LF
Other Pins
-3.0
0.5
3.0
-1.0
0.2
1.0
uA
Output High Voltage
I/O Ports
VOH
XOUT
IOH = -5.0mA, VDD = 4.5V
VDD - 0.9
VDD
V
VSS
0.8
V
IOH = -0.5mA, VDD = 4.5V, RC osc.
Output Low Voltage
I/O Ports
XOUT
1.
2.
VOL
IOL = 8.0mA, VDD = 4.5V
IOL = 0.6mA, VDD = 4.5V, RC osc.
Data in “Typ” column is at 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
This parameter are characterized but not tested.
Oct. 2001 Ver. 2.0
11
HMS77C1000A/HMS77C1001A
7.5 AC Electrical Characteristics (1)
• (TA=-40°°C~+85°°C)
Parameter
External Clock Input
Frequency
Oscillator Frequency 1
External Clock Input
Period
Oscillator Period 1
Clock in XIN Pin 1
Low to High Time
Clock in XIN Pin 1
Rise or Fall Time
1.
12
Symbol
FXIN
FXIN
TXIN
TXIN
TXINL
TXINH
TXINR
TXINF
Test Condition
Specification
Unit
Min
Typ
Max
XT osc mode
DC
-
4.0
MHz
HF osc mode
DC
-
20
MHz
LF osc mode
DC
-
200
KHz
RC osc mode
DC
-
4.0
MHz
XT osc mode
0.1
-
4.0
MHz
HF osc mode
4.0
-
20
MHz
LF osc mode
5.0
-
200
KHz
XT osc mode
250
-
-
nS
HF osc mode
50
-
-
nS
LF osc mode
5
-
-
uS
RC osc mode
250
-
-
nS
XT osc mode
250
-
10,000
nS
HF osc mode
50
-
250
nS
LF osc mode
5
-
200
uS
XT osc mode
85
-
-
nS
HF osc mode
20
-
-
nS
LF osc mode
2
-
-
uS
XT osc mode
-
-
25
nS
HF osc mode
-
-
25
nS
LF osc mode
-
-
50
nS
This parameter is characterized but not tested.
Oct. 2001 Ver. 2.0
HMS77C1000A/HMS77C1001A
7.6 AC Electrical Characteristics (2)
• (TA=-40°°C~+85°°C)
Parameter 1
Specification
Symbol
Test Condition
Min
Typ2
Max
Unit
RESET Pulse Width (Low)
TRESET
VDD = 5V
100
-
-
nS
Watchdog Timer Time-Out
Period ( No-prescaler )
TWDT
VDD = 5V
9
18
30
mS
Internal Reset Timer Period
TIRT
VDD = 5V
9
18
30
mS
TCY = 4 X TXIN
10
-
-
nS
0.5TCY + 20
-
-
20
-
-
(TCY+40) / N
-
-
EC0 High or Low Pulse Width
No Prescaler
TEC0H
TEC0L
With Prescaler
EC0 Period
No Prescaler
TEC0P
N = Prescaler Value
( 1,2,4,......256 )
With Prescaler
1.
2.
nS
These parameters are characterized but not tested.
Data in “Typ” column is at 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
TXINH
TXIN
TXINL
0.85VDD
XIN
0.15V
TXINR
TXINF
TRESET
RESET
0.15VDD
TEC0H
TEC0H
0.85VDD
EC0
0.15VDD
TEC0P
Oct. 2001 Ver. 2.0
13
HMS77C1000A/HMS77C1001A
7.7 Typical Characteristics
These graphs and tables are for design guidance only and
are not tested or guaranteed.
In some graphs or tables the data presented are outside specified operating range (e.g. outside specified
VDD range). This is for information only and devices
are guaranteed to operate properly only within the
specified range.
The data is a statistical summary of data collected on units
from different lots over a period of time. “Typical” represents the mean of the distribution while “max” or “min”
represents (mean + 3σ) and (mean − 3σ) respectively
where σ is standard deviation
Operating Area
Normal Operation
IDD−VDD
fXIN
(MHz)
IDD
(mA)
Ta= 25°C
24
Ta=25°C
4
20
fXIN = 20MHz
16
3
12
2
8
1
4
0
4MHz
32KHz
0
2
3
4
5
6
2
VDD
(V)
IOL−VOL, VDD=5V
3
4
5
VDD
6 (V)
IOL−VOL, VDD=3V
IOL
(mA)
IOL
(mA)
Ta=25°C
Ta=25°C
40
18
32
24
12
16
6
8
0
0.4
14
0.8
1.2
1.6
VOL
2.0 (V)
0
0.4
0.8
1.2
1.6
VOL
2.0 (V)
Oct. 2001 Ver. 2.0
HMS77C1000A/HMS77C1001A
IOH−VOH, VDD=5V
IOH
(mA)
IOH−VOH, VDD=3V
IOH
(mA)
Ta=25°C
-20
Ta=25°C
-8
-16
-6
-12
-4
-8
-2
-4
0
0.5
1.0
VDD-VOH
(V)
1.5
0
0.5
2.0
Typical RC Oscillator
Frequency VS. VDD
FOSC
(MHz)
7.5
Cext=20pF
Ta=25°C
4.5
R=3.3K
VDD-VOH
(V)
1.5
Typical RC Oscillator
Frequency VS. VDD
FOSC
(MHz)
Cext=0pF
Ta=25°C
1.0
R=3.3K
4.0
3.5
6.0
R=5K
R=5K
3.0
2.5
4.5
2.0
R=15K
3.0
R=15K
1.5
1.0
1.5
0.5
R=100K
0
2.5
FOSC
(MHz)
2.00
3
3.5
4
4.5
5
5.5
VDD
6 (V)
Typical RC Oscillator
Frequency VS. VDD
Cext=100pF
Ta=25°C
FOSC
(MHz)
0.8
R=3.3K
1.75
0.7
1.50
0.6
1.25
R=100K
0
2.5
3
3.5
4
4.5
5.5
5
VDD
6 (V)
Typical RC Oscillator
Frequency VS. VDD
Cext=300pF
Ta=25°C
R=3.3K
R=5K
0.5
R=5K
0.4
1.00
0.75
R=15K
0.3
R=15K
0.2
0.50
0.25
0.1
R=100K
0
2.5
Oct. 2001 Ver. 2.0
3
3.5
4
4.5
5
5.5
VDD
6 (V)
R=100K
0
2.5
3
3.5
4
4.5
5
5.5
VDD
6 (V)
15
HMS77C1000A/HMS77C1001A
Cext
Rext
0pF
20pF
100pF
300pF
Average
Fosc @ 5V,25°C
3.3K
6.5MHz
5K
5.4MHz
15K
2.3MHz
100K
400KHz
3.3K
4.3MHz
5K
3.5MHz
15K
1.4MHz
100K
240KHz
3.3K
1.8MHz
5K
1.5MHz
15K
610KHz
100K
100KHz
3.3K
780KHz
5K
630KHz
15K
260KHz
100K
42.5KHz
Table 7-1 RC Oscillator Frequencies
16
Oct. 2001 Ver. 2.0
HMS77C1000A/HMS77C1001A
8. ARCHITECTURE
8.1 CPU Architecture
The HMS700 core is a RISC-based CPU and uses a modified Harvard architecture. This architecture uses two separate memories with separate address buses, one for the
program memory and the other for the data memory. This
architecture adapts 33 single word instructions that are 12bit wide instruction and has an internal 2-stage pipeline
(fetch and execute), which results in execution of one instruction per single cycle(200ns @ 20MHz) except for program branches.
The HMS77C100XA can address 1K x 12 Bits program
memory and 25 Bytes data memory. And it can directly or
indirectly address data memory.
The HMS700 core has three special function registers PC, STATUS and FSR - in data memory map and has ATU
(Address Translation Unit) to provide address for data
memory and has an 8-bit general purpose ALU and working register(W) as an accumulator. The W register consists
of 8-bit register and it can not be an addressed register.
Program Memory Address
Instruction
PC with 2-level Stack
STATUS
Immediate Data
Instruction
Decode
&
Control
Unit
FSR
Indirect Address
Control
Signals
Address Translation
Unit
W
ALU
Status
ALU
Data Bus
Data Memory Bus
FIGURE 8-1 HMS700 CPU BLOCK DIAGRAM
Oct. 2001 Ver. 2.0
17
HMS77C1000A/HMS77C1001A
9. MEMORY
The HMS77C100XA has separate memory maps for program memory and data memory. Program memory can
only be read, not written to. It can be up to 1K words of
program memory. Data memory can be read and written to
32 bytes including special function registers.
PC<9:0>
Stack Level 1
9.1 Program Memory
Stack Level 2
The program memory is organized as 0.5K, 12-bit wide
words(HMS77C1000A) and 1K, 12-bit wide
words(HMS77C1001A). The program memory words are
addressed sequentially by a program counter. Incrementi n g a t loc a tion 1FF H ( H M S 77 C 1 0 0 0A ) o r 3F F H
(HMS77C1001A) will cause a wrap around to 000H.
000H
PC<8:0>
000H
1FFH
2FFH
300H
On-chip
Program
Memory
(Page 1)
3FFH
Reset Vector
FIGURE 9-2 HMS77C1001A PROGRAM MEMORY MAP
AND STACK
Stack Level 2
9.2 Data Memory
On-chip
Program
Memory
User Memory
Space
0FFH
100H
User Memory
Space
1FFH
200H
Figure 9-1 and Figure 9-2 show a map of program memory. After reset, CPU begins execution from reset vector
which is stored in address(1FFH: HMS77C1000A, 3FFH:
HMS77C1001A).
Stack Level 1
On-chip
Program
Memory
(Page 0)
0FFH
100H
Reset Vector
FIGURE 9-1 HMS77C1000A PROGRAM MEMORY MAP
AND STACK
The data memory consists of 25 bytes of RAM and seven
special function registers. The data memory locations are
addressed directly or indirectly by using FSR.
Figure 9-3 shows a map of data memory. The special function registers are mapped into the data memory..
File Address
00H
INDF
01H
TMR0
02H
PCL
03H
STATUS
04H
FSR
05H
RA
06H
RB
00H
06H
07H
0FH
10H
Special
Function
Registers
DATA
MEMORY
(SRAM)
DATA
MEMORY
(SRAM)
1FH
FIGURE 9-3 HMS77C100XA DATA MEMORY MAP
18
Oct. 2001 Ver. 2.0
HMS77C1000A/HMS77C1001A
9.3 Special Function Registers
This devices has seven special function register that are the
INDF register, the Program Counter(PC), the STATUS
register, File Select Register(FSR), 8-bit Timer(TMR0),
and I/O data register(RA, RB).
the device (Table 9-1).
TMR0, RA and RB are not in the G700 CPU. They are located in each peripheral function blocks. All special function register are placed on data memory map. The INDF
register is not a physical register and this register is used
for indirect addressing mode...
The Special Function Registers are registers used by the
CPU and peripheral functions to control the operation of
Power-On
Reset
RESET and
WDT Reset
I/O control registers (TRISA, TRISB)
1111 1111
1111 1111
N/A
Contains control bits to configure Timer0, Timer0/WDT
prescaler and PFD
0011 1111
0011 1111
INDF
00H
Uses contents of FSR to address data memory (not a
physical register)
xxxx xxxx
uuuu uuuu
TMR0
01H
8-bit real-time clock/counter
xxxx xxxx
uuuu uuuu
PCL
02H
Low order 8bits of PC
1111 1111
1111 1111
STATUS
03H
0001 1xxx
000q quuu
FSR
04H
1xxx xxxx
1uuu uuuu
RA
05H
-
-
-
-
RA3
RA2
RA1
RA0
---- xxxx
---- uuuu
RB
06H
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx
uuuu uuuu
Name
Address
Bit7
TRIS
N/A
OPTION
-
Bit6
-
Bit5
PA0
Bit4
TO
Bit3
PD
Bit2
Z
Bit1
DC
Bit0
C
Indirect data memory address pointer
TABLE 9-1 SPECIAL FUNCTION REGISTER SUMMARY
Legend : Shaded boxes = unimplemented or unused, - = unimplemented, read as ‘0’
x = unknown, u = unchanged, q = see the tables in Section 17 for possible values.
9.3.1 INDF Register
The INDF register is not physically implemented register,
used for indirect addressing mode. If the INDF register
are accessed, CPU goes to indirect addressing mode. Then
CPU accesses the Data memory which address is the contents of FSR.
If the INDF register are accessed in indirect addressing
mode(I.e., FSR=00H), 00H will be loaded into data bus.
This time, note the arithmetic status bits of STATUS register may be affected.
The FSR<4:0> bits are used to select data memory addresses 00H to 1FH.
Direct Addressing
4
(opcode)
location
select
00H
Data
Memory
0FH
10H
0
Indirect Addressing
(FSR)
0
4
location
select
HMS77C1000A and HMS77C1001A do not use banking.
FSR<7:5> are unimplemented and read as '1's.
1FH
FIGURE 9-4 DIRECT/INDIRECT ADDRESSING
Oct. 2001 Ver. 2.0
19
HMS77C1000A/HMS77C1001A
subroutine call instruction
9.3.2 TMR0 Register
The TMR0 register is a data register for 8-bit timer/
counter. In reset state, the TMR0 register is initialized with
“00H”.
8
7
0
PC
PCL
9.3.3 Program Counter (PC)
Instruction Word
The program counter contains the 10-bit address of the instruction to be executed(9-bit address for
HMS77C1000A).
The lower 8 bits of the program counter are contained in
the PCL register which can be provided by the instruction
word for a call instruction, or any instruction where the
PCL is the destination while the ninth bit of the program
counter comes from the page address bit - PA0 of the STATUS register(HMS77C1001A only).
Reset to ‘0’
FIGURE 9-5 LOADING OF BRANCH INSTRUCTION HMS77C1000A
jump instruction
9
8
0
PC
PCL
This is necessary to cause program branches across program memory page boundaries.
Instruction Word
PA0
Prior to the execution of a branch operation, the user must
initialize the PA0 bit of STATUS register.
The eighth bit of the program counter can come from the
instruction word by execution of goto instruction, or can be
cleared by execution of call or any instruction where the
PCL is the destination.
subroutine call Instruction
9
8
7
0
PC
PCL
In reset state, the program counter is initialized with
“1FFH”(HMS77C1000A) or “3FFH”(HMS77C1001A).
Instruction Word
Reset to ‘0’
PA0
Note: Because PC<8> is cleared in the subroutine call instruction, or any Modify PCL instruction, all subroutine calls or computed jumps are limited to the first
256 locations of any program memory page (512
words long).
FIGURE 9-6 LOADING OF BRANCH INSTRUCTION HMS77C1001A
jump instrunciton
9.3.4 Stack Operation
8
PC
0
PCL
Instruction Word
20
The HMS77C100XA have a 2-level hardware stack. The
s tack reg is ter co nsis ts o f two 9 -bit sa ve re gisters(HMS77C1000A), 10-bit save registers(HMS77C1001A). A physical transfer of register
contents from the program counter to the stack or vice versa, and within the stack, occurs on call and return instructions. If more than two sequential call instructions are
executed, only the most recent two return address are
stored. If more than two sequential return instructions are
executed, the stack will be filled with the address previously stored in level 2. The stack cannot be read or written by
Oct. 2001 Ver. 2.0
HMS77C1000A/HMS77C1001A
program.
RESET status, and the page select bit for program memories larger than 512 words.
The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z,
DC or C bits, then the write to these three bits is disabled.
These bits are set or cleared according to the device logic.
Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register
as destination may be different than intended.
HMS77C1001A(HMS77C1000A)
9(8)
0
PC
subroutine call
return
STACK LEVEL1
subroutine call
return
It is recommended that only instructions that do not affect
status of CPU be used on STATUS register. Care should be
exercised when writing to the STATUS register as the
ALU status bits are updated upon completion of the write
operation, possibly leaving the STATUS register with a result that is different than intended. In reset state, the STATUS register is initialized with “00011XXXB”.
STACK LEVEL2
FIGURE 9-7 OPERATION OF 2-LEVEL STACK
9.3.5 STATUS Register
This register contains the arithmetic status of the ALU, the
-
-
R/W
R
R
R/W
R/W
R/W
PA0
TO
PD
Z
DC
C
bit7
PA0: Program memory page select bits
0 = page 0 (000h - 1FFh) - HMS77C1000A/
1001A
1 = page 1 (200h - 3FFh) - HMS77C1001A
TO: Time-overflow bit
1 = After power-up, watchdog clear instruction, or
entering power-down mode
0 = A watchdog timer time-overflow occurred
PD: Power-down bit
1 = After power-up or by the watchdog clear
instruction
0 = By execution of power-down mode
Z: Zero bit
1 = The result of an arithmetic or logic operation
is zero
0 = The result of an arithmetic or logic operation
is not zero
bit0
ADDRESS ; 03H
RESET VALUE : 0001_1XXX
R = Readable bit
W = Writable bit
DC: Digit carry/borrow bit
(for addition and subtraction)
addition
1 = A carry from the 4th low order bit of the result
occurred
0 = A carry from the 4th low order bit of the result
did not occur
subtraction
1 = A borrow from the 4th low order bit of the
result did not occur
0 = A borrow from the 4th low order bit of the
result occurred
C: Carry/borrow bit
(for additon,subtraction and rotation)
addition
1 = A carry occurred
0 = A carry did not occur
subtraction
1 = A borrow did not occur
0 = A borrow occurred
rotation
Load bit with LSB or MSB, respectively
FIGURE 9-8 STATUS REGISTER
Oct. 2001 Ver. 2.0
21
HMS77C1000A/HMS77C1001A
9.3.6 FSR Register
dressing mode.
The FSR register is an 8-bit register. The lower 5 bits are
used to store indirect address for data memory. The upper
3 bits are unimplemented and read as “0”. Figure 9-9
shows how the FSR register can be used in indirect ad-
In reset state, the FSR register is initialized with
“1XXX_XXXXB”.
11
Instruction Word
5 4
0
4
8
-
-
OPCODE
Direct Addressing mode
-
0
FSR
Address : 04H
RESET Value: 1XXX_XXXXB
Indirect Addressing mode
0
1
Data Memory Address
FIGURE 9-9 FSR REGISTER AND DIRECT/INDIRECT ADDRESSING MODE
9.3.7 OPTION Register
The OPTION register consists of 8-bit write-only register
and can not addressed. This register is able to control the
status of PFD, TMR0/WDT prescaler and TMR0.
22
To modify the OPTION register, the content of W register
are transferred to the OPTION register by executing the
OPTION instruction.
In reset state, the OPTION register is initialized with
“00111111B” .
Oct. 2001 Ver. 2.0
HMS77C1000A/HMS77C1001A
W
W
LOWOPT PFDEN
W
W
W
W
W
W
T0CS
T0SE
PSA
PS2
PS1
PS0
5
4
3
2
1
bit7
6
LOWOPT:
Power-fail detection level select bit.
1 = Lowered detection level (1.8V @ 5V)
0 = Normal detection level (2.7V @ 5V)
PFDEN:
T0CS:
T0SE:
PSA:
Power-fail detection enable bit
1 = Enable power-fail detection
0 = Disable power-fail detection
Timer 0 clock source select bit
1 = Transition on EC0 pin
0 = Internal instruction cycle clock
Timer 0 source edge select bit
1 = Increment on high-to-low transition on
EC0
0 = Increment on low-to-high transition on
EC0
ADDRESS ; N/A
RESET VALUE : 0011_1111
bit0
PS2-PS0:
W = Writable bit
-n = Value at POR reset
Prescaler rate select bits)
Bit Value
Timer 0 rate
WDT rate
000
1:2
1:1
001
1:4
1:2
010
1:8
1:4
011
1:16
1:8
100
1:32
1:16
101
1:64
1:32
110
1:128
1:64
111
1:256
1:128
Prescaler assignment bit
1 = Prescaler assigned to the WDT
0 = Prescaler assigned to the Timer 0
FIGURE 9-10 OPTION REGISTER
Oct. 2001 Ver. 2.0
23
HMS77C1000A/HMS77C1001A
10. I/O PORTS
The HMS77C100XA has a 4-bit I/O port(RA) and a 8-bit
I/O port(RB).
All pin have data(RA,RB) and direction(TRISA,TRISB)
registers which can assign these ports as output or input.
A “0” in the port direction registers configure the corresponding port pin as output. Conversely, write “1” to the
corresponding bit to specify it as input pin (Hi-Z state).
10.2 Port RB
RB is an 8-bit I/O register. Each I/O pin can independently
used as an input or an output through the port direction register, TRISB. A “0” in the TRISB register configure the
corresponding port pin as output. Conversely, write “1”to
the corresponding bit to specify it as input pin.
ADDRESS : 06H
RESET VALUE : Undefined
For example, to use the even numbered bit of RB as output
ports and the odd numbered bits as input ports, write “55H”
to TRISB register during initial setting as shown in Figure
10-1.
RB Data Register
All the port direction registers in the HMS77C100XA have
“1” written to them by reset function. This causes all port
as input.
RB Direction Register
Write “55H” to port RB direction register
6
5
4
3
2
1
0
0
1
0
1
0
1
0
1
PORT RB O U T IN O U T IN O U T IN O U T IN
FIGURE 10-1 EXAMPLE OF PORT I/O ASSIGNMENT
10.1 Port RA
RA is a 4-bit I/O register. Each I/O pin can independently
used as an input or an output through the port direction register, TRISA. A “0” in the TRISA register configure the
corresponding port pin as output. Conversely, write “1”to
the corresponding bit to specify it as input pin.
Bits 7-4 are unimplemented and read as '0's.
RA Data Register
3
2
1
0
ADDRESS : 05H
RESET VALUE : Undefined
RA R A 3 R A 2 R A 1 R A 0
RA Direction Register
5
4
3
2
1
0
ADDRESS : N/A
RESET VALUE : FFH
TRISB
Note: A read of the ports reads the pins, not the output
data latches. That is, if an output driver on a pin is
enabled and driven high, but the external system is
holding it low, a read of the port will indicate that the
pin is low.
10.3 I/O Interfacing
The equivalent circuit for an I/O port pin is shown in Figure 10-4. All ports may be used for both input and output
operation.
For input operations these ports are non-latching. Any input must be present until read by an input instruction. The
outputs are latched and remain unchanged until the output
latch is rewritten. To use a port pin as output, the corresponding direction control bit (in TRISA, TRISB) must be
cleared (= 0). For use as an input, the corresponding TRIS
bit must be set. Any I/O pin can be programmed individually as input or output..
10.4 I/O Successive Operations
ADDRESS : N/A
RESET VALUE : 0FH
TRISA
FIGURE 10-2 RA PORT REGISTERS
24
6
FIGURE 10-3 RB PORT REGISTERS
7
TRISB
7
RB R B 7 R B 6 R B 5 R B 4 R B 3 R B 2 R B 1 R B 0
The actual write to an I/O port happens at the end of an instruction cycle, whereas for reading, the data must be valid
at the beginning of the instruction cycle (Figure 10-5).
Therefore, care must be exercised if a write followed by a
read operation is carried out on the same I/O port.
The sequence of instructions should allow the pin voltage
to stabilize (load dependent) before the next instruction,
which causes that file to be read into the CPU, is executed.
Oct. 2001 Ver. 2.0
HMS77C1000A/HMS77C1001A
VDD
Data Reg.
Data Bus
Direction Reg.
Data Bus
VSS
Data Bus
Read
FIGURE 10-4 EQUIVALENT CIRCUIT FOR A SINGLE I/O PIN
Name
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
I/O control registers (TRISA, TRISB)
Power-On
Reset
RESET and
WDT Reset
1111 1111
1111 1111
TRIS
N/A
RA
05H
-
-
-
-
RA3
RA2
RA1
RA0
---- xxxx
---- uuuu
RB
06H
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx
uuuu uuuu
TABLE 10-1 SUMMARY OF PORT REGISTERS
Legend: Shaded boxes = unimplemented or unused, - = unimplemented, read as ‘0’, x = unknown, u = unchanged.
Otherwise, the previous state of that pin may be read into
the CPU rather than the new state.
When in doubt, it is better to separate these instructions
with a NOP or another instruction not accessing this I/O
port.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Instruction
fetched
PC
output RB
PC+1
read RB port
PC+2
no operation
PC+3
This example shows a write
to RB followed by a read
from RB.
no operation
RB7:RB0
Port pin
written here
Port pin
read here
FIGURE 10-5 SUCCESSIVE I/O OPERATION
Oct. 2001 Ver. 2.0
25
HMS77C1000A/HMS77C1001A
11. TIMER0 MODULE AND TMR0 REGISTER
The Timer0 module has the following features:
• Edge select for external clock
• 8-bit timer/counter register, TMR0
• 8-bit software programmable prescaler
• Internal or external clock select
Figure 11-1 is a simplified block diagram of the Timer0
module, while Figure 11-2 shows the electrical structure of
the Timer0 input.
TCY ( = FOSC/4)
Data bus
0
8
1
MUX
1
0
EC0
pin
MUX
Sync with
Internal
Clocks
TMR0 reg
(2cycle delay)
T0SE
T0CS
PSA
0
1
Watchdog
Timer
MUX
8-bit Prescaler
clear
8
8 - to - 1 MUX
WDT Enable bit
PS2:PS0
PSA
0
1
MUX
PSA
WDT Time-Out
FIGURE 11-1 BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
P
RIN
Noise Filter
ECO
pin
N
(1)
Schmitt Trigger
Input Buffer
Note 1: ESD protection circuits
FIGURE 11-2 ELECTRICAL STRUCTURE OF EC0 PIN
26
Oct. 2001 Ver. 2.0
HMS77C1000A/HMS77C1001A
11.1 Timer Mode
If the OPTION register bit5(T0CS) is cleared, the timer
mode is selected and is operated with internal system clock
(TCY). The Timer0 module will increment every instruction cycle (without prescaler). If TMR0 register is written,
the increment is inhibited for the following two cycles. The
user can work around this by writing an adjusted value to
the TMR0 register.
Figure 11-3 and Figure 11-4 show the timing diagram of
Timer.
- No Prescaler (PSA=0)
Timer will increment every instruction cycle(Q4).
- With Prescaler (PSA=1)
Timer will increment with prescaler division ratio.
@ PS2~PS0 = (1:2) ~ (1:256)Counter Mode
11.2 Counter Mode
If the OPTION register bit5(T0CS) is set, the counter
mode is selected and operates with event clock input.
In this mode, Timer0 will increment either on every rising
or falling edge of pin EC0. The incrementing edge is determined by the source edge select bit T0SE (OPTION<4>).
Clearing the T0SE bit selects the rising edge.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
(Program
Counter)
PC-1
Instruction
Fetch
PC
PC+1
[ W ’ TMR0 ]
Instruction
Executed
TMR0
[ TMR0 ’ W ]
PC+2
[ TMR0 ’ W ]
Write TMR0 Read TMR0
executed
reads NT0
T0
T0+1
T0+2
PC+3
[ TMR0 ’ W ]
Read TMR0
reads NT0
PC+4
[ TMR0 ’ W ]
PC+5
PC+6
[ TMR0 ’ W ]
Read TMR0 Read TMR0 Read TMR0
reads NT0
reads NT0+1 reads NT0+2
NT0
NT0+1
NT0+2
increment inhibited
Timer0
Clock
FIGURE 11-3 TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
(Program
Counter)
PC-1
Instruction
Fetch
Instruction
Executed
TMR0
PC
PC+1
[ W ’ TMR0 ]
[ TMR0 ’ W ]
PC+2
[ TMR0 ’ W ]
Write TMR0 Read TMR0
executed
reads NT0
T0
Timer0
Clock
T0+1
PC+3
PC+4
PC+5
PC+6
[ TMR0 ’ W ]
[ TMR0 ’ W ]
[ TMR0 ’ W ]
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0 Read TMR0
reads NT0+1 reads NT0+2
NT0
NT0+1
increment inhabited
FIGURE 11-4 TIMER0 TIMING: INTERNAL CLOCK/PRESCALER 1:2
Oct. 2001 Ver. 2.0
27
HMS77C1000A/HMS77C1001A
Name
TMR0
Address
01H
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
8-bit real-time clock/counter
OPTION N/A
LOWOPT PFDEN
T0CS
T0SE
PSA
PS2
PS1
PS0
Power-On
Reset
RESET and
WDT Reset
xxxx xxxx
uuuu uuuu
0011 1111
0011 1111
TABLE 11-1 REGISTERS ASSOCIATED WITH TIMER0
Legend: x = unknown, u = unchanged.
11.3 Using Timer0 with an External Clock
chronization and the increment of the counter mode.
When an external clock input is used for Timer0, it must
meet certain requirements. The external clock requirement
is due to internal phase clock (TOSC) synchronization. Also, there is a delay in the actual incrementing of Timer0 after synchronization.
• EC0 clock specification
- No Prescaler (PSA = 0)
High or low time(min) ≥ 2TXIN + 20ns
- With Prescaler (PSA = 1)
High or low time(min) ≥ 4TXIN + 40ns
11.3.1 External Clock Synchronization
But, there is a noise filter on the EC0 pin, the minimum low
or high time(10ns) should be required.
The synchronization of EC0 input with the internal phase
clocks is accomplished by sampling EC0 clock or the prescaler output on the Q2 and Q4 falling of the internal phase
clocks.
11.3.2 Timer0 Increment Delay
Since the prescaler output is synchronized with the internal
clocks, there is a small delay from the time the external
clock edge occurs to the time the Timer0 module is actually incrementing. Figure 11-5 shows the delay from the external clock edge to the timer incrementing.
After the synchronization, counter increments on the next
instruction cycle (Q4). There is a small delay from the time
the external clock edge occurs to the time the Timer0 module is actually incrementing. Figure 11-5 shows the syn-
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
External Clock Input or
Prescaler Output(2)
Small Pulse
misses sampling
(1)
External Clock/Prescaler
Output After Sampling
(3)
Increment TMR0 (Q4)
TMR0
T0
T0+1
T0+2
Note 1: Delay from clock input change to TMR0 increment is 3TXIN to 7TXIN . (Duration of Q = TXIN).
Therefore, the error in measuring the interval between two edges on TMR0 input = ±4TXIN max.
2: External clock if no prescaler selected, prescaler output otherwise.
3: The arrows indicate the points in time where sampling occurs.
FIGURE 11-5 TIMER0 TIMING WITH EXTERNAL CLOCK
11.4 Prescaler
The prescaler may be used by either the Timer0 module or
the Watchdog Timer, but not both. Thus, a prescaler assignment for the Timer0 module means that there is no
prescaler for the WDT, and vice-versa.
The prescaler assignment is controlled in software by the
28
control bit PSA (OPTION<3>). Clearing the PSA bit will
assign the prescaler to Timer0. The prescaler is neither
readable nor writable.
The PSA and PS2:PS0 bits (OPTION<3:0>) determine
prescaler assignment and prescale ratio. When the prescaler is assigned to the Timer0 module, prescale values of 1:2,
Oct. 2001 Ver. 2.0
HMS77C1000A/HMS77C1001A
1:4,..., 1:256 are selectable.
When assigned to the Timer0 module, all instructions writing to the TMR0 register will clear the prescaler. When as-
Oct. 2001 Ver. 2.0
signed to WDT, a CLRWDT instruction will clear the
prescaler along with the WDT.
On a RESET, the prescaler contains all '0's.
29
HMS77C1000A/HMS77C1001A
12. CONFIGURATION AREA
The device configuration area can be programmed or left
unprogrammed to select device configurations such as oscillator type, security bit or watchdog timer enable bit.
bit11
4 3
Four memory locations [AAAH ~ (AAA+3)H] are designated as customer ID recording locations where the user
can store check-sum or other customer identification numbers. These area are not accessible during normal execution but are readable and writable during program/verify
mode. It is recommended that only the 4 least significant
bits of ID recording locations are used.
bit0
AAAH
-
ID0
AAAH+1
-
ID1
AAAH+2
-
ID2
AAAH+3
-
ID3
Configuration Word
FFFH
FIGURE 12-1 DEVICE CONFIGURATION AREA
bit11
Configuration Word
4
-
3
CP
2
1
bit0
WDTE FOSC1 FOSC0
Address : FFFH
Unimplemented, read as ‘0’
bit 3
CP : Code protection bit.
1 = Code protection disabled
0 = Code protection enabled
bit 2
WDTE: Watchdog timer enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0
FOSC1:FOSC0: Oscillator selection bits
11 = RC oscillator
10 = HF oscillator
01 = XT oscillator
00 = LF oscillator
FIGURE 12-2 CONFIGURATION WORD FOR HMS77C100XA
30
Oct. 2001 Ver. 2.0
HMS77C1000A/HMS77C1001A
13. OSCILLATOR CIRCUITS
HMS77C100XA supports four user-selectable oscillator
modes. The oscillator modes are selected by programming
the appropriate values into the configuration word.
-
XT : Crystal/Resonator
HF : High Speed Crystal/Resonator
LF : Low Speed and Low Power Crystal
RC : External Resistor/Capacitor
Osc
Type
Resonator
Freq
Cap.Range
C1
Cap. Range
C2
XT
455 kHz
2.0 MHz
4.0 MHz
22-100 pF
15-68 pF
15-68 pF
22-100 pF
15-68 pF
15-68 pF
HF
4.0 MHz
8.0 MHz
16.0 MHz
15-68 pF
10-68 pF
10-22 pF
15-68 pF
10-68 pF
10-22 pF
13.1 XT, HF or LF Mode
In XT, LF or HF modes, a crystal or ceramic resonator is
connected to the XIN and XOUT pins to establish oscillation
(Figure 13-1). The HMS77C100XA oscillator design requires the use of a parallel cut crystal. Use of a series cut
crystal may give a frequency out of the crystal manufacturers specifications. Bits 0 and 1 of the configuration register
(FOSC1:FOSC2) are used to configure the different external resonator/crystal oscillator modes. These bits allow the
selection of the appropriate gain setting for the internal
driver to match the desired operating frequency. When in
XT, LF or HF modes, the device can have an external clock
source drive the XIN pin (Figure 13-2). In this case, the
XOUT pin should be left open.
C1(1)
TABLE 13-1 CAPACITOR SELECTION FOR CERAMIC
RESONATORS
Note: These values are for design guidance only. Since
each resonator has its own characteristics, the user
should consult the resonator manufacturer for appropriate values of external components.
Osc
Type
Crystal
Freq
Cap.Range
C1
Cap. Range
C2
LF
32 kHz1
100 kHz
200 kHZ
15 pF
15-30 pF
15-30 pF
15 pF
30-47 pF
15-82 pF
XT
100 kHz
200 kHz
455 kHz
1 MHz
2 MHz
4 MHz
15-30 pF
15-30 pF
15-30 pF
15-30 pF
15-30 pF
15-47 pF
200-300 pF
100-200 pF
15-100 pF
15-30 pF
15-30 pF
15-47 pF
HF
4 MHz
8 MHz
20 MHz
15-30 pF
15-30 pF
15-30 pF
15-30 pF
15-30 pF
15-30 pF
XOUT
SLEEP
RF(2)
XTAL
XIN
To internal
logic
C2(1)
Note 1: See Capacitor Selection tables for recommended
values of C1 and C2.
2: RF varies with the crystal chosen
(approx. value = 9 MΩ).
FIGURE 13-1 CRYSTAL OR CERAMIC RESONATOR
(HF, XT OR LF OSC CONFIGURATION)
Clock from
ext. system
XIN
TABLE 13-2 CAPACITOR SELECTION FOR CRYSTAL
1. For VDD > 4.5V, C1 = C2 ≈ 30 pF is recommended.
Note: These values are for design guidance only. Since
each crystal has its own characteristics, the user
should consult the crystal manufacturer for appropriate values of external components.
If you change from this device to another device,
please verify oscillator characteristics in your
application.
HMS77C100XA
OPEN
XOUT
FIGURE 13-2 EXTERNAL CLOCK INPUT OPERATION
(HF, XT OR LF OSC CONFIGURATION)
Oct. 2001 Ver. 2.0
13.2 RC Oscillation Mode
The external RC oscillator mode provides a cost-effective
approach for applications that do not require a precise operating frequency. In this mode, the RC oscillator frequen-
31
HMS77C1000A/HMS77C1001A
cy is a function of the supply voltage, the resistor(R) and
capacitor(C) values, and the operating temperature.
The Electrical Specifications sections show R frequency
variation from part to part due to normal process variation.
In addition, the oscillator frequency will vary from unit to
unit due to normal manufacturing process variations. Furthermore, the difference in lead frame capacitance between
package types also affects the oscillation frequency, especially for low C values. The external R and C component
tolerances contribute to oscillator frequency variation as
well.
Also, see the Electrical Specifications sections for variation of oscillator frequency due to VDD for given Rext/Cext values as well
as frequency variation due to operating temperature for given R,
C, and VDD values.
The oscillator frequency, divided by 4, is available on the
XOUT pin, and can be used for test purposes or to synchronize other logic.
The user also needs to take into account variation due to
tolerance of external R and C components used.
Figure 13-3 shows how the R is connected to the
HMS77C100XA. For Rext values below 2.2 kΩ, the oscillator operation may become unstable, or stop completely.
For very high Rext values (e.g., 1 MΩ) the oscillator becomes sensitive to noise, humidity and leakage. Thus, we
recommend keeping Rext between 3 kΩ and 100 kΩ. Table 13-3 shows recommended value of Rext and Cext.
Although the oscillator will operate with no external capacitor (Cext = 0 pF), it is recommend using values above
20 pF for noise and stability reasons. With no or small external capacitance, the oscillation frequency can vary dramatically due to changes in external capacitances, such as
PCB trace capacitance or package lead frame capacitance.
VDD
Rext
XIN
Cext
FXIN/4
Internal
Clock
N
XOUT
FIGURE 13-3 RC OSCILLATION MODE
Cext
Rext
Average FXIN @ 5V, 25°C
0pF
3.3K
5K
15K
100K
6.5MHz
5.4MHz
2.3MHz
400KHz
20pF
3.3K
5K
15K
100K
4.3MHz
3.5MHz
1.4MHz
240KHz
100pF
3.3K
5K
15K
100K
1.8MHz
1.5MHz
610KHz
100KHz
300pF
3.3K
5K
15K
100K
780KHz
630KHz
260KHz
42.5KHz
TABLE 13-3 RC OSCILLATION FREQUENCIES
32
Oct. 2001 Ver. 2.0
HMS77C1000A/HMS77C1001A
14. RESET
HMS77C100XA devices may be reset in one of the following ways:
- Power-On Reset (POR)
- Power-Fail detect reset (PFDR)
- RESET (normal operation)
- RESET wake-up reset (from SLEEP)
- WDT reset (normal operation)
- WDT wake-up reset (from SLEEP)
Table 14-2 lists a full description of reset states of all registers. Figure 14-1 shows a simplified block diagram of the
on-chip reset circuit.
PCL
Addr: 02H
STATUS
Addr: 03H
Power-On Reset
1111 1111
0001 1xxx
RESET reset or PFD
reset (normal operation)
1111 1111
000u uuuu1
RESET wake-up or PFD
reset (from SLEEP)
1111 1111
0001 0uuu
WDT reset (normal
operation)
1111 1111
0000 uuuu2
WDT wake-up (from
SLEEP)
1111 1111
0000 0uuu
Condition
Each one of these reset conditions causes the program
counter to branch to reset vector address. (HMS77C1000A
is 1FFH and HMS77C1001A is 3FFH ).
Table 14-1 shows these reset conditions for the PCL and
STATUS registers.
Some registers are not affected in any reset condition.
Their status is unknown on POR and unchanged in any
other reset. Most other registers are reset to a “reset state”
on Power-On Reset (POR), PFDR, RESET or WDT reset.
A RESET or WDT wake-up from SLEEP also results in a
device reset, and not a continuation of operation before
SLEEP.
The TO and PD bits (STATUS <4:3>) are set or cleared
depending on the different reset conditions. These bits may
be used to determine the nature of the reset.
TABLE 14-1 RESET CONDITIONS FOR SPECIAL
REGISTERS
1. TO and PD bits retain their last value until one of the other
reset conditions occur.
2. The CLRWDT instruction will set the TO and PD bits.
Legend : x = unknown, u = unchanged.
Address
Power-On
Reset
Wake-up
Reset
RESET, PFDR,
WDT Reset
W
N/A
xxxx xxxx
uuuu uuuu
uuuu uuuu
TRIS
N/A
1111 1111
1111 1111
1111 1111
OPTION
N/A
0011 1111
0011 1111
0011 1111
INDF
00H
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR0
01H
xxxx xxxx
uuuu uuuu
uuuu uuuu
PCL1
02H
1111 1111
1111 1111
1111 1111
STATUS1
03H
0001 1xxx
100q quuu
000q quuu
FSR
04H
1xxx xxxx
1uuu uuuu
1uuu uuuu
PORTA
05H
---- xxxx
---- uuuu
---- uuuu
PORTB
06H
xxxx xxxx
uuuu uuuu
uuuu uuuu
07-1FH
xxxx xxxx
uuuu uuuu
uuuu uuuu
Register
General Purpose Register Files
TABLE 14-2 RESET CONDITIONS FOR ALL REGISTERS
1. See Table 14-1 for reset value for specific conditions.
Legend : - = unimplemented, read as ‘0’, x = unknown, u = unchanged.
q = see the tables in Section 17 for possible values.
Oct. 2001 Ver. 2.0
33
HMS77C1000A/HMS77C1001A
Power-On
RESET
VDD
WDT Time-Overflow
Power-Fail
Detect
Noise
Filter
S
Q
R
Q
Internal RESET
RESET/VPP pin
WDT
On-Chip
RC OSC
reset
clear
Internal RESET
Timer ( 8-bit asyn.
ripple counter )
FIGURE 14-1 SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
14.1 Power-On Reset (POR)
The HMS77C100XA family incorporates on-chip PowerOn Reset (POR) circuitry which provides an internal chip
reset for most power-up situations. To use this feature, the
user merely ties the RESET/VPP pin to VDD. A simplified
block diagram of the on-chip Power-On Reset circuit is
shown in Figure 14-1.
The Power-On Reset circuit and the Internal Reset Timer
circuit are closely related. On power-up, the reset latch is
set and the IRT is reset. The IRT timer begins counting
once it detects RESET to be high. After the time-out period, which is typically 7 ms (oscillation stabilization time),
it will reset the reset latch and thus end the on-chip reset
signal.
VDD
RESET
TIRT
INTERNAL POR
IRT TIMER-OUT
INTERNAL RESET
FIGURE 14-2 TIME-OUT SEQUENCE ON POWER-UP (RESET NOT TIED TO VDD)
34
Oct. 2001 Ver. 2.0
HMS77C1000A/HMS77C1001A
VDD
RESET
TIRT
INTERNAL POR
IRT TIMER-OUT
INTERNAL RESET
FIGURE 14-3 TIME-OUT SEQUENCE ON POWER-UP (RESET TIOED TO VDD): FAST VDD RISE TIME
VDD
RESET
TIRT
INTERNAL POR
IRT TIMER-OUT
INTERNAL RESET
- When VDD rise slowly, the TIRT time-out expires long before VDD has reached its final value.
In this example, the chip will reset properly if, V1 ≥ VDDmin.
FIGURE 14-4 TIME-OUT SEQUENCE ON POWER-UP (RESET TIOED TO VDD): SLOW VDD RISE TIME
A power-up example where RESET is not tied to VDD is
shown in Figure 14-2. VDD is allowed to rise and stabilize
before bringing RESET high. The chip will actually come
out of reset TIRT after RESET goes high and POR, PFDR
is released.
In Figure 14-3, the on-chip Power-On Reset feature is being used (RESET and VDD are tied together). The VDD is
stable before the internal reset timer times out and there is
no problem in getting a proper reset. However, Figure 144 depicts a problem situation where VDD rises too slowly.
The time between when the IRT senses a high on the RESET/VPP pin, and when the RESET/VPP pin (and VDD)
actually reach their full value, is too long. In this situation,
Oct. 2001 Ver. 2.0
when the internal reset timer times out, VDD has not
reached the VDD (min) value and the chip is, therefore, not
guaranteed to function correctly. For such situations, we
recommend that external R circuits be used to achieve
longer POR delay times (Figure 14-5).
Note: When the device starts normal operation (exits the
reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be meet to
ensure operation. If these conditions are not met,
the device must be held in reset until the operating
conditions are met.
35
HMS77C1000A/HMS77C1001A
The POR circuit does not produce an internal reset when
VDD declines.
VDD
VDD
D
R
R1
RESET
C
- External Power-On Reset circuit is required only if VDD
power-up is too slow. The diode D helps discharge the
capacitor quickly when VDD powers down.
- R < 40 kΩ is recommended to make sure that voltage
drop across R does not violate the device electrical specification.
- R1 = 100W to 1 kW will limit any current flowing into
RESET from external capacitor C in the event of RESET
pin breakdown due to Electrostatic Discharge (ESD) or
Electrical Overstress (EOS).
14.2 Internal Reset Timer (IRT)
The Internal Reset Timer (IRT) provides a fixed 7 ms nominal time-out on reset. The IRT operates on an internal RC
oscillator. The processor is kept in RESET as long as the
IRT is active. The IRT delay allows VDD to rise above
VDD min., and for the oscillator to stabilize.
Oscillator circuits based on crystals or ceramic resonators
require a certain time after power-up to establish a stable
oscillation. The on-chip IRT keeps the device in a RESET
condition for approximately 7 ms after the voltage on the
RESET/VPP pin has reached a logic high (VIH) level and
POR released. Thus, external RC networks connected to
the RESET input are not required in most cases, allowing
for savings in cost-sensitive and/or space restricted applications. The Device Reset time delay will vary from chip
to chip due to VDD, temperature, and process variation.
The IRT will also be triggered upon a Watchdog Timer
time-out. This is particularly important for applications using the WDT to wake the HMS77C100XA from SLEEP
mode automatically.
FIGURE 14-5 EXTERNAL POWER-ON RESET
CIRCUIT (FOR SLOW VDD POWER- UP)
36
Oct. 2001 Ver. 2.0
HMS77C1000A/HMS77C1001A
15. WATCHDOG TIMER (WDT)
The Watchdog Timer (WDT) is a free running on-chip RC
oscillator which does not require any external components.
This RC oscillator is separate from the RC oscillator of the
XIN pin. That means that the WDT will run even if the
clock on the XIN and XOUT pins have been stopped, for example, by execution of a SLEEP instruction. During normal operation or SLEEP, a WDT reset or wake-up reset
generates a device RESET.
caler with a division ratio of up to 1:256 can be assigned to
the WDT (under software control) by writing to the OPTION register. Thus, time-out a period of a nominal 3.5
seconds can be realized. These periods vary with temperature, VDD and part-to-part process variations (see DC
specs).
Under worst case conditions (VDD = Min., Temperature =
Max., max. WDT prescaler), it may take several seconds
before a WDT time-out occurs.
The TO bit (STATUS<4>) will be cleared upon a Watchdog Timer reset.
15.2 WDT Programming Considerations
The WDT can be permanently disabled by programming
the configuration bit WDTE as a '0' (Figure 12-2). Refer to
the HMS77C100XA Programming Specifications to determine how to access the configuration word.
The CLRWDT instruction clears the WDT and the
postscaler, if assigned to the WDT, and prevents it from
timing out and generating a device RESET.
The SLEEP instruction resets the WDT and the postscaler,
if assigned to the WDT. This gives the maximum SLEEP
time before a WDT wake-up reset.
15.1 WDT Period
The WDT has a nominal time-out period of 14 ms, (with
no prescaler). If a longer time-out period is desired, a pres-
SLEEP
From TMR0 Clock Source
Watchdog Timer
8-bit asynchronous
ripple counter
on-chip
RC-OSC
PSA
clearing WDT
0
1
MUX
Postscaler
8
clear
8 - to - 1 MUX
enable
PS2:PS0
PSA
0
To TMR0
1
MUX
PSA
WDTE
SLEEP
WDT Time-Out
clearing WDT
FIGURE 15-1 WATCHDOG TIMER BLOCK DIAGRAM
Name
OPTION
Address
N/A
Bit7
LOWOPT
Bit6
Bit5
PFDEN T0CS
Bit4
Bit3
Bit2
Bit1
Bit0
Power-On
Reset
RESET and
WDT Reset
T0SE
PSA
PS2
PS1
PS0
0011 1111
0011 1111
TABLE 15-1 SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER
Oct. 2001 Ver. 2.0
37
HMS77C1000A/HMS77C1001A
16. Power-Down Mode (SLEEP)
For applications where power consumption is a critical
factor, device provides power down mode with Watchdog
operation. Executing of SLEEP Instruction is entrance to
SLEEP mode. In the SLEEP mode, oscillator is turn off
and system clock is disable and all functions is stop, but all
registers and RAM data is held. The wake-up sources from
SLEEP mode are external RESET pin reset and watchdog
time-overflow reset.
16.1 SLEEP
The Power-Down mode is entered by executing a SLEEP
instruction. If enabled, the Watchdog Timer will be cleared
It should be noted that a RESET generated by a WDT timeout does not drive the RESET pin low.
For lowest current consumption while powered down, the
EC0 input should be at VDD or VSS and the RESET pin
must be at a logic high level .
~
~
~
~
~
~
Oscillator
(XIN pin)
Fetch SLEEP
Execute SLEEP
Fetch RESET vector
TIRT
~
~
~
~
Internal
RESET
~
~
~
~
RESET
~
~ ~
~ ~
~
~
~
Internal
System Clock
Instruction
but keeps running, the TO bit (STATUS<4>) is set, the PD
bit (STATUS<3>) is cleared and the oscillator driver is
turned off. The I/O ports maintain the status they had before the SLEEP instruction was executed (driving high,
driving low, or hi-impedance).
FIGURE 16-1 TIMING DIAGRAM OF WAKE-UP FROM SLEEP MODE DUE TO EXTERNAL RESET PIN RESET
~
~
Execute SLEEP
Fetch RESET vector
~ ~
~
~
TIRT
~
~ ~
~ ~
~
Internal
RESET
Fetch SLEEP
~
~
~ ~
WDT
Overflow
~
~
Internal
System Clock
Instruction
~
~
~
~
Oscillator
(XIN pin)
FIGURE 16-2 TIMING DIAGRAM OF WAKE-UP FROM SLEEP MODE DUE TO WATCHDOG TIME-OVERFLOW RESET
38
Oct. 2001 Ver. 2.0
HMS77C1000A/HMS77C1001A
16.2 Wake-up From SLEEP
The device can wake up from SLEEP through one of the
following events:
1. An external reset input on RESET pin.
2. A Watchdog Timer time-out reset (if WDT was enabled).
3. PFD reset
Both of these events cause a device reset. The TO and PD
bits can be used to determine the cause of device reset. The
TO bit is cleared if a WDT time-out occurred (and caused
wake-up). The PD bit, which is set on power-up, is cleared
when SLEEP is invoked.
The WDT is cleared when the device wakes from sleep, regardless of the wake-up source.
16.3 Minimizing Current Consumption
The SLEEP mode is designed to reduce power consumption. To minimize current drawn during SLEEP mode, the
user should turn-off output drivers that are sourcing or
sinking current, if it is practical.
It should be set properly that current flow through port
doesn't exist.
First conseider the setting to input mode. Be sure that there
is no current flow after considering its relationship with
external circuit. In input mode, the pin impedance viewing
from external MCU is very high that the current doesn’t
flow.
But input voltage level should be VSS or VDD. Be careful
that if unspecified voltage, i.e. if uncertain voltage level
(not VSSor VDD) is applied to input pin, there can be little
current (max. 1mA at around 2V) flow.
Note: In the SLEEP operation, the power dissipation associated with the oscillator and the internal hardware
is lowered; however, the power dissipation associated with the pin interface (depending on the external
circuitry and program) is not directly determined by
the hardware operation of the SLEEP feature. This
point should be little current flows when the input
level is stable at the power voltage level (VDD/VSS);
however, when the input level becomes higher than
the power voltage level (by approximately 0.3V), a
current begins to flow. Therefore, if cutting off the
output transistor at an I/O port puts the pin signal
into the high-impedance state, a current flow across
the ports input transistor, requiring it to fix the level
by pull-up or other means.
If it is not appropriate to set as an input mode, then set to
output mode considering there is no current flow. Setting
to High or Low is decided considering its relationship with
external circuit. For example, if there is external pull-up resistor then it is set to output mode, i.e. to high, and if there
is external pull-down register, it is set to low.
VDD
INPUT PIN
INPUT PIN
VDD
VDD
internal
pull-up
VDD
i=0
O
OPEN
O
i
i
GND
X
Weak pull-up current flows
Very weak current flows
VDD
X
OPEN
O
i=0
GND
O
When port is configure as an input, input level should
be closed to 0V or 5V to avoid power consumption.
FIGURE 16-3 APPLICATION EXAMPLE OF UNUSED INPUT PORT
Oct. 2001 Ver. 2.0
39
HMS77C1000A/HMS77C1001A
OUTPUT PIN
OUTPUT PIN
VDD
ON
OPEN
OFF
ON
OFF
OFF
i
VDD
GND
X
ON
O
ON
OFF
VDD
L
OFF
ON
i
GND
X
O
L
i=0
GND
O
In the left case, Tr. base current flows from port to GND.
To avoid power consumption, there should be low output
to the port.
In the left case, much current flows from port to GND.
FIGURE 16-4 APPLICATION EXAMPLE OF UNUSED OUTPUT PORT
40
Oct. 2001 Ver. 2.0
HMS77C1000A/HMS77C1001A
17. TIME-OUT SEQUENCE AND POWER DOWN STATUS BITS (TO/PD)
The TO and PD bits in the STATUS register can be tested
to determine if a RESET condition has been caused by a
power-up condition, a RESET or Watchdog Timer (WDT)
reset, or a RESET or WDT wake-up reset.
RESET was caused by
Table 17-2.
Event
TO
PD
Power-up
1
1
WDT Time-out
0
u
TO
PD
1
1
Power-up(POR)
SLEEP instruction
1
0
u
u
RESET or PFD reset (normal operation)1
CLRWDT instruction
1
1
1
0
RESET Wake-up or PFD reset
(from SLEEP)
0
1
WDT reset (normal operation)
0
0
WDT wake-up reset (from SLEEP)
TABLE 17-1 TO/PD STATUS AFTER RESET
1. The TO and PD bits maintain their status (u) until a reset
occurs. A low-pulse on the RESET input does not change the
TO and PD status bits.
These STATUS bits are only affected by events listed in
Oct. 2001 Ver. 2.0
Remarks
No effect on PD
TABLE 17-2 EVENTS AFFECTING TO/PD STATUS
BITS
Note: A WDT time-out will occur regardless of the status of
the TO bit. A SLEEP instruction will be executed,
regardless of the status of the PD bit.
Table 14-1 lists the reset conditions for the special function
registers, while Table 14-2 lists the reset conditions for all
the registers.
41
HMS77C1000A/HMS77C1001A
18. POWER FAIL DETECTION PROCESSOR
HMS77C100XA has an on-chip power fail detection circuitry to immunize against power noise.
OPTION
Register
LOWOPT PFDEN
bit7
6
If VDD falls below a level for longer 100ns, the power fail
detection processor may reset MCU and preserve the device from the malfunction due to Power Noise.
T0CS
T0SE
PSA
PS2
PS1
5
4
3
2
1
bit 7
LOWOPT: Power-fail detection level select bit.
1 = Lowered detection level (typ. 1.8V @ 5V)
0 = Normal detection level (typ. 2.7V @ 5V)
bit 6
PFDEN: Power-fail detection enable bit
1 = Enable power-fail detection
0 = Disable power-fail detection
PS0
bit0
FIGURE 18-1 POWER FAIL DETECTION PROCESSOR
The bit6(PFDEN) of OPTION register activates the PFD
Circuit, and bit7(LOWopt) lowers the detection level of
the Power Noise. The normal detection level is typically
2.7V and the lowered detection level is typically 1.8V. Figure 18-2 shows a Power Fail Detection Situations where
the detection level is selected by LOWOPT Bit.
Note: The PFD circuit is not implemented on the in circuit
emulator, user can not experiment with it. There
fore, after final development user program, this
function may be experimented on OTP
TNVDD ≥ 100nS
VDD
PFDEN = 1
LOWOPT = 0
VDR=2.7V
TIRT
PFDR
Internal
RESET
TNVDD ≥ 100nS
VDD
VDR=1.8V
TIRT
PFDEN = 1
LOWOPT = 1
PFDR
Internal
RESET
VDD
VDD ≤ VDR
PFDEN = 1
LOWOPT = 0/1
VDR=2.7 or 1.8V
TIRT
PFDR
Internal
RESET
POR
When VDD falls below approximately 1.5V level, Power-On Reset may occur.
FIGURE 18-2 POWER FAIL DETECTION SITUATIONS
42
Oct. 2001 Ver. 2.0
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