Hynix HMT125R7AFP8C Ddr3 sdram registered dimm based on 1gb a version Datasheet

240pin DDR3 SDRAM Registered DIMM
DDR3 SDRAM Registered DIMM
Based on 1Gb A version
HMT112R7AFP8C
HMT125R7AFP8C
HMT125R7AFP4C
HMT151R7AFP4C
HMT151R7AFP8C
HMT31GR7AMP4C
** Contents may be changed at any time without any notice.
Rev. 0.4 /Jul. 2009
1
Revision History
Revision No.
History
Draft Date
0.1
Initial Release
2008-8
0.2
Added IDD Specification
2008-11
0.3
Reflected the actual measurement, nonphysical change (max thickness)
2009-02
0.4
Added Environment Parameter
2009-07
Rev. 0.4 / Jul. 2009
Remark
2
Table of Contents
1. Description
1.1 Device Features and Ordering Information
1.1.1 Features
1.1.2 Ordering Information
1.2 Key Parameters
1.3 Speed Grade
1.4 Address Table
2. Pin Architecture
2.1 Pin Definition
2.2 Input/Output Functional Description
2.3 Pin Assignment
3. Functional Block Diagram
3.1 1GB, 128Mx72 Module(1Rank of x8)
3.2 2GB, 256Mx72 Module(2Rank of x8)
3.3 2GB, 256Mx72 Module(1Rank of x4)
3.4 4GB, 512Mx72 Module(2Rank of x4)
3.5 4GB, 512Mx72 Module(4Rank of x8)
3.6 8GB,
1Gx72 Module(4Rank of x4)
4. Environment Parameter
5. Input/Output Capacitance & AC Parametrics
6. IDD Specifications
7. DIMM Outline Diagram
7.1 1GB, 128Mx72 Module(1Rank of x8)
7.2 2GB, 256Mx72 Module(2Rank of x8)
7.3 2GB, 256Mx72 Module(1Rank of x4)
7.4 4GB, 512Mx72 Module(2Rank of x4)
7.5 4GB, 512Mx72 Module(4Rank of x8)
7.6 8GB,
1Gx72 Module(4Rank of x4)
Rev. 0.4 / Jul. 2009
3
1. Description
This Hynix DDR3 SDRAM Registered Dual In-Line Memory Module (DIMM) series consists of 1Gb A generation. These
are intended for use as main memory in server and workstation systems, providing a high performance 8 byte interface in 133.35mm width form factor of industry standard. It is suitable for easy interchange and addition.
1.1 Product Features & Ordering Information
1.1.1 Features
• VDD=VDDQ=1.5V
• BL switch on the fly
• VDDSPD=3.3V to 3.6V
• 8 banks
• Fully differential clock inputs (CK, CK) operation
• 8K refresh cycles /64ms
• Differential Data Strobe (DQS, DQS)
• DDR3 SDRAM Package: JEDEC standard 78ball
FBGA(x4/x8), 96ball FBGA(x16) with support balls
• On chip DLL align DQ, DQS and /DQS transition with
CK transition
• Driver strength selected by EMRS
• DM masks write data-in at the both rising and falling
edges of the data strobe
• Dynamic On Die Termination supported
• All addresses and control inputs except data, data
strobes and data masks latched on the rising edges of
the clock
• ZQ calibration supported
• Programmable CAS latency 5, 6, 7, 8, 9, 10, and (11)
supported
• Asynchronous RESET pin supported
• TDQS (Termination Data Strobe) supported (x8 device
based only)
• Write Levelization supported
• Programmable additive latency 0, CL-1, and CL-2 sup
ported
• Auto Self Refresh supported
• Programmable CAS Write latency (CWL) = 5, 6, 7, 8
• Heat Spreader installed for 4GB/8GB
• Programmable burst length 4/8 with both nibble
sequential and interleave mode
• SPD with Integrated TS of Class B
• 8 bit pre-fetch
* This product in compliance with the directive petaining of RoHS.
1.1.2 Ordering Information
Density
Organization
# of
DRAMs
# of
ranks
Materials
FDHS
HMT112R7AFP8C-G7/H9
1GB
128Mx72
9
1
Lead free
X
HMT125R7AFP8C-G7/H9
2GB
256Mx72
18
2
Lead free
X
HMT125R7AFP4C-G7/H9
2GB
256Mx72
18
1
Lead free
X
HMT151R7AFP4C-G7/H9
4GB
512Mx72
36
2
Lead free
O
HMT151R7AFP8C-G7/H9
4GB
512Mx72
36
4
Lead free
O
HMT31GR7AMP4C-G7/H9
8GB
1Gx72
72
4
Lead free
O
Part Number
* Please Contact local sales administrator for more details of part number
Rev. 0.4 / Jul. 2009
4
1.2 Key Parameters
MT/s
DDR3-1066
DDR3-1333
Grade
-G7
-H9
tCK(min)
1.875
1.5
ns
CAS Latency
7
9
tCK
tRCD(min)
13.125
13.5
ns
tRP(min)
13.125
13.5
ns
tRAS(min)
37.5
36
ns
tRC(min)
50.625
49.5
ns
CL-tRCD-tRP
7-7-7
9-9-9
tCK
Unit
1.3 Speed Grade
Frequency [MHz]
Grade
Remark
CL5
CL6
CL7
CL8
-G7
800
1066
1066
-H9
800
1066
1066
CL9
CL10
1333
1333
1.4 Address Table
1GB(1Rx8)
2GB(2Rx8)
2GB(1Rx4)
4GB(2Rx4)
4GB(4Rx8)
8GB(4Rx4)
Organization
128M x 72
256M x 72
256M x 72
512M x 72
512M x 72
1G x 72
Refresh
Method
8K/64ms
8K/64ms
8K/64ms
8K/64ms
8K/64ms
8K/64ms
Row Address
A0-A13
A0-A13
A0-A13
A0-A13
A0-A13
A0-A13
Column
Address
A0-A9
A0-A9
A0-A9,A11
A0-A9,A11
A0-A9
A0-A9,A11
Bank Address
BA0-BA2
BA0-BA2
BA0-BA2
BA0-BA2
BA0-BA2
BA0-BA2
Page Size
1KB
1KB
1KB
1KB
1KB
1KB
# of Rank
1
2
1
2
4
4
# of Device
9
18
18
36
36
72
Rev. 0.4 / Jul. 2009
5
2. Pin Architecture
2.1 Pin Definition
Num
-ber
Pin
Name
Address Inputs
14
A10/AP
Address Input/Autoprecharge
1
SDRAM Bank Addresses
3
A12/BC
Address Input/Autoprecharge
1
RAS
Row Address Strobe
1
SCL
Serial Presence Detect (SPD) Clock Input
1
CAS
Column Address Strobe
1
SDA
SPD Data Input/Output
1
WE
Write Enable
1
SA0–SA2
Pin Name
A0–A9,A11
A13-A15
BA0–BA2
Description
Description
Num
-ber
SPD Address Inputs
3
1
Chip Selects
4
Par_in
Parity Bit For The Address and Control
Bus
CKE0–CKE1
Clock Enables
2
ERR_OUT
Parity Error Found on the Address and
Control Bus
1
ODT0–ODT1
On-die termination Inputs
2
EVENT
Reserved for Optional Hardware
temperature Sensing
1
Data Input/Output
64
TEST
Memory Bus Test Tool (Not Connected
and Not Usable on DIMMs)
1
Data Check Bits Input/Output
8
RESET
Register and SDRAM control pin
1
DQS0–DQS8
Data Strobes
9
VDD
Power Supply
22
DQS0–DQS8
Data Strobes, Negative Line
9
VSS
Ground
59
VREFDQ
Reference Voltage for DQ
1
VREFCA
Reference Voltage for CA
1
Termination Voltage
4
SPD Power
1
CK1
Clock Input, positive line
1
CK1
Clock Input, negative line
1
S0–S3
DQ0–DQ63
CB0–CB7
Data Masks
DM0–DM8
DQS9-DQS17 Data Strobes
TDQS9-TDQS17 Termination Data Strobes
DQS9–DQS17 Data Strobes, Negative Line
TDQS9–TDQS17 Termination Data Strobes
9
VTT
9
CK0
Clock Input, positive line
1
CK0
Clock Input, positive Line
1
Rev. 0.4 / Jul. 2009
VDDSPD
6
2.2 Input/Output Functional Description
Symbol
Type
Polarity
Function
CK0
IN
Positive Line
Positive line of the differential pair of system clock inputs that drives input
to the on-DIMM Clock Driver.
CK0
IN
Negative Line
Negative line of the differential pair of system clock inputs that drives the
input to the on-DIMM Clock Driver.
CK1
IN
Positive Line Terminated but not used on RDIMMs
CK1
IN
Negative Line Terminated but not used on RDIMMs
CKE0–CKE1
IN
Active High
CKE HIGH activates, and CKE LOW deactivates internal clock signals, and
device input buffers and output drivers of the SDRAMs. Taking CKE LOW
provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all
banks idle), or ACTIVE POWER DOWN (row ACTIVE in any bank)
S0–S3
IN
Active Low
Enables the command decoders for the associated rank of SDRAM when
low and disables decoders.When decoders are disabled, new commands
are ignored and previous operations continue.Other combinations of these
input signals perform unique functions, including disabling all outputs
(except CKE and ODT) of the register(s) on the DIMM or accessing internal
control words in the register device(s).For modules with two registers,S[3:2] operate similarly to S[1:0] for the second set of register outputs or register control words.
RAS, CAS, WE
IN
Active Low
When sampled at the positive rising edge of the clock, CAS, RAS, and WE
define the operation to be executed by the SDRAM.
ODT0–ODT1
IN
Active High
On-Die Termination control signals
VREFDQ
Supply
Reference voltage for DQ0-DQ63 and CB0-CB7
VREFCA
Supply
Reference voltage for A0-A15, BA0-BA2, RAS, CAS, WE, S0, S1, CKE0,
CKE1, Par_In, ODT0 and ODT1.
VDDQ
Supply
Power supply for the DDR3 SDRAM output buffers to provide improved
noise immunity. For all current DDR3 unbuffered DIMM designs, VDDQ
shares the same power plane as VDD pins.
Selects which SDRAM bank of eight is activated.
BA0–BA2
IN
—
BA0-BA2 define to which bank an Active, Read, Write or Precharge command is being applied.Bank address also determines mode register is to be
accessed during an MRS cycle.
A0-A9
A10/AP
A11
A12/BC
A13-A15
IN
—
Provided the row address for Active commands and the column address
and Auto Precharge bit for Read/Write commands to select one location
out of the memory array in the respective bank.A10 is sampled during a
Precharge command to determine whether the Precharge applies to one
bank (A10 LOW) or all banks (A10 HIGH).If only one bank is to be precharged, the bank is selected by BA.A12 is also utilized for BL 4/8 identification for “BL on the fly” during CAS command. The address inputs also
provide the op-code during Mode Register Set commands.
DQ0–DQ63,
CB0–CB7
I/O
—
Data and Check Bit Input/Output pins.
Rev. 0.4 / Jul. 2009
7
Symbol
Type
Polarity
DM0–DM8
IN
Active High
VDD, VSS
Supply
Power and ground for the DDR3 SDRAM input buffers, and core logic.
VTT
Supply
Termination Voltage for Address/Command/Control/Clock nets.
DQS0-DQS17
I/O
Positive Edge Positive line of the differential data strobe for input and output data.
DQS0–DQS17
I/O
Negative Edge Negative line of the differential data strobe for input and output data.
TDQS9-TDQS17
TDQS9-TDQS17
Masks write data when high, issued concurrently with input data.
TDQS/TDQS is applicable for x8 DRAMs only. WHen enabled via Mode Register A11=1 in MR1, DRAM will enable the same termination resistance
function on TDQS/TDQS that is applied to DQS/DQS. When disabled via
mode register A11=0 in MR1, DM/TDQS will provide the data mask function and TDQS is not used.x4/x16 DRAMs must disable the TDQS function
via mode register A11=0 in MR1.
OUT
SA0–SA2
Function
—
These signals are tied at the system planar to either VSS or VDDSPD to configure the serial SPD EEPROM address range.
SDA
I/O
—
This bidirectional pin is used to transfer data into or out of the SPD
EEPROM. An external resistor may be connected from the SDA bus line to
VDDSPD to act as a pullup on the system board.
SCL
IN
—
This signal is used to clock data into and out of the SPD EEPROM. An
external resistor may be connected from the SCL bus time to VDDSPD to act
as a pull up.
VDDSPD
Supply
EVENT
OUT
(open
drain)
Serial EEPROM positive power supply wired to a separate power pin at the
connector which supports from 3.0 Volt to 3.6 Volt (nominal 3.3V) operation.
Active Low
This signal indicates that a thermal event has been detected in the thermal
sensing device. The system should guarantee the electrical level requirement is met for the EVENT pin on TS/SPD part.
RESET
IN
The RESET pin is connected to the RESET pin on the register and to the
RESET pin on the DRAM. When low, all register outputs will be driven low
and the Clock Driver clocks to the DRAMs and register(s) will be set to low
level (the Clock Driver will remain synchronized with the input clock)
Par_In
IN
Parity bit for the Address and Control bus.(“1”:Odd, “0”:Even)
Err_Out
OUT
(open
drain)
TEST
Rev. 0.4 / Jul. 2009
Parity error detected on the Address and Control bus.A resistor may be
connected from Err_Out bus line to VDD on the system planar to act as a
pull up.
Used by memory bus analysis tools (unused (NC) on memory DIMMs)
8
2.3 Pin Assignment
Pin #
Front Side
(left 1–60)
Pin #
Back Side
(right 121–180)
Pin #
Front Side
(left 61–120)
Pin #
Back Side
(right 181–240)
1
VREFDQ
121
VSS
61
A2
181
A1
2
VSS
122
DQ4
62
VDD
182
VDD
3
DQ0
123
DQ5
63
NC, CK1
183
VDD
4
DQ1
124
VSS
64
NC, CK1
184
CK0
5
VSS
125
DM0,DQS9,TDQS9
65
VDD
185
CK0
6
DQS0
126
NC, DQS9,TDQS9
66
VDD
186
VDD
7
DQS0
127
VSS
67
VREFCA
187
EVENT, NC
8
VSS
128
DQ6
68
Par_in, NC
188
A0
9
DQ2
129
DQ7
69
VDD
189
VDD
10
DQ3
130
VSS
70
A10 / AP
190
BA1
11
VSS
131
DQ12
71
BA0
191
VDD
12
DQ8
132
DQ13
72
VDD
192
RAS
13
DQ9
133
VSS
73
WE
193
S0
14
VSS
134
DM1,DQS10,TDQS10
74
CAS
194
VDD
15
DQS1
135
NC,DQS10,TDQS10
75
VDD
195
ODT0
16
DQS1
136
VSS
76
S1, NC
196
A13
17
VSS
137
DQ14
77
ODT1, NC
197
VDD
18
DQ10
138
DQ15
78
VDD
198
S3, NC
19
DQ11
139
VSS
79
S2, NC
199
VSS
20
VSS
140
DQ20
80
VSS
200
DQ36
21
DQ16
141
DQ21
81
DQ32
201
DQ37
22
DQ17
142
VSS
82
DQ33
202
VSS
23
VSS
143
DM2,DQS11,TDQS11
83
VSS
203
DM4,DQS13,TDQS13
24
DQS2
144
NC,DQS11,TDQS11
84
DQS4
204
NC, DQS13,TDQS13
25
DQS2
145
VSS
85
DQS4
205
VSS
26
VSS
146
DQ22
86
VSS
206
DQ38
27
DQ18
147
DQ23
87
DQ34
207
DQ39
28
DQ19
148
VSS
88
DQ35
208
VSS
29
VSS
149
DQ28
89
VSS
209
DQ44
30
DQ24
150
DQ29
90
DQ40
210
DQ45
31
DQ25
151
VSS
91
DQ41
211
VSS
32
VSS
152
DM3,DQS12,TDQS12
92
VSS
212
DM5,DQS14,TDQS14
33
DQS3
153
NC, DQS12,TDQS12
93
DQS5
213
NC, DQS14,TDQS14
NC = No Connect; RFU = Reserved Future Use
Rev. 0.4 / Jul. 2009
9
Pin #
Front Side
(left 1–60)
Pin #
Back Side
(right 121–180)
Pin #
Front Side
(left 61–120)
Pin #
Back Side
(right 181–240)
34
DQS3
154
VSS
94
DQS5
214
VSS
35
VSS
155
DQ30
95
VSS
215
DQ46
36
DQ26
156
DQ31
96
DQ42
216
DQ47
37
DQ27
157
VSS
97
DQ43
217
VSS
38
VSS
158
CB4, NC
98
VSS
218
DQ52
39
CB0, NC
159
CB5, NC
99
DQ48
219
DQ53
40
CB1, NC
160
VSS
100
DQ49
220
VSS
41
VSS
161
DM8,DQS17,TDQS17
NC
101
VSS
221
DM6,DQS15,TDQS15
42
DQS8
162
NC,DQS17,TDQS17
102
DQS6
222
NC, DQS15,TDQS15
43
DQS8
163
VSS
103
DQS6
223
VSS
44
VSS
164
CB6, NC
104
VSS
224
DQ54
45
CB2, NC
165
CB7, NC
105
DQ50
225
DQ55
46
CB3, NC
166
VSS
106
DQ51
226
VSS
47
VSS
167
NC(TEST)
107
VSS
227
DQ60
48
VTT, NC
168
RESET
108
DQ56
228
DQ61
109
DQ57
229
VSS
KEY
KEY
49
VTT, NC
169
CKE1, NC
110
VSS
230
DM7,DQS16,TDQS16
50
CKE0
170
VDD
111
DQS7
231
NC, DQS16,TDQS16
51
VDD
171
A15
112
DQS7
232
VSS
52
BA2
172
A14
113
VSS
233
DQ62
53
Err_Out, NC
173
VDD
114
DQ58
234
DQ63
54
VDD
174
A12 / BC
115
DQ59
235
VSS
55
A11
175
A9
116
VSS
236
VDDSPD
56
A7
176
VDD
117
SA0
237
SA1
57
VDD
177
A8
118
SCL
238
SDA
58
A5
178
A6
119
SA2
239
VSS
59
A4
179
VDD
120
VTT
240
VTT
60
VDD
180
A3
NC = No Connect; RFU = Reserved Future Use
Rev. 0.4 / Jul. 2009
10
3. Functional Block Diagram
A[N:O]B
/BA[N:O]B
RODT0B
PCK0B
RCKE0B
RWEB
PCK0B
A[O:N]/BA[O:N]
ODT
CK
CKE
CK
CAS
WE
ODT
CK
CKE
CK
WE
CAS
D5
ODT
CK
CKE
CK
WE
CAS
D6
A[O:N]/BA[N:O]
ZQ
ODT
CK
CKE
CK
D7
A[N:O]/BA[N:O]
ZQ
WE
RAS
CS
A[N:O]/BA[N:O]
ODT
CK
CKE
CK
ZQ
A[O:N]/BA[N:O]
DQS
DQS
TDQS
TDQS
DQ [7:0]
ZQ
D0
RCASB
DQS7
DQS7
DM7/DQS16
DQS16
DQ[63:56]
RAS
DQS
DQS
TDQS
TDQS
DQ [7:0]
CS
DQS6
DQS6
DM6/DQS15
DQS15
DQ[55:48]
D4
CAS
ODT
A[O:N]/BA[N:O]
A[N:O]/BA[N:O]
ODT
DQS
DQS
TDQS
TDQS
DQ [7:0]
RAS
ODT
ODT
CK
CKE
CK
CKE
CK
CKE
RS0B
RRASB
A[N:O]A
/BA[N:O]A
RODT0A
PCK0A
RCKE0A
CK
CKE
CK
CK
D1
WE
CAS
RAS
CK
WE
ZQ
DQS
DQS
TDQS
TDQS
DQ [7:0]
CS
CK
CAS
WE
WE
CAS
CAS
CAS
D2
WE
RAS
CS
CS
RAS
RAS
ZQ
DQS5
DQS5
DM5/DQS14
DQS14
DQ[47:40]
CS
DQS
DQS
TDQS
TDQS
DQ [7:0]
D3
DQS
DQS
TDQS
TDQS
DQ [7:0]
RAS
DQS1
DQS1
DM1/DQS10
DQS10
DQ[15:8]
ZQ
ZQ
DQS4
DQS4
DM4/DQS13
DQS13
DQ[39:32]
CS
DQS
DQS
TDQS
TDQS
DQ [7:0]
A[N:O]/BA[N:O]
DQS2
DQS2
DM2/DQS11
DQS11
DQ[23:16]
D8
A[O:N]/BA[N:O]
DQS
DQS
TDQS
TDQS
DQ [7:0]
RAS
DQS3
DQS3
DM3/DQS12
DQS12
DQ[31:24]
CS
DQS
DQS
TDQS
TDQS
DQ [7:0]
CS
RWEA
ZQ
DQS8
DQS8
DM8/DQS17
DQS17
CB[7:0]
DQS0
DQS0
DM0/DQS9
DQS9
DQ[7:0]
PCK0A
RS0A
RRASA
RCASA
3.1 1GB, 128Mx72 Module(1Rank of x8)
Vtt
VDDSPD
SPD
VDD
D0–D8
VTT
VREFCA
D0–D8
VREFDQ
D0–D8
VSS
D0–D8
Note:
1.DQ-to-I/O wiring may be changed within byte.
2.ZQ resistors are 240Ω ± 1%.For all other resistor values refer to the
appropriate wiring diagram.
Vtt
S0
S1
BA[N:0]
A[N:0]
RAS
CAS
WE
CKE0
ODT0
CK0
CK0
CK0
CK0
PAR_IN
120Ω
± 1%
1:
2
R
E
G
I
S
T
E
R
/
P
L
L
120Ω
± 1%
RESET
OERR
RST
RS0A → CS0: SDRAMs D[3:0], D8
RS0B → CS0: SDRAMs D[7:4]
RBA[N:0]A → BA[N:0]: SDRAMs D[3:0], D8
RBA[N:0]A → BA[N:0]: SDRAMs D[7:4]
RA[N:0]A → A[N:0]: SDRAMs D[3:0], D8
RA[N:0]A → A[N:0]: SDRAMs D[7:4]
RRASA → RAS: SDRAMs D[3:0], D8
RRASA → RAS: SDRAMs D[7:4]
RCASA → CAS: SDRAMs D[3:0], D8
RCASA → CAS: SDRAMs D[7:4]
RWEA → WE: SDRAMs D[3:0], D8
RWEA → WE: SDRAMs D[7:4]
RCKE0A → CKE0: SDRAMs D[3:0], D8
RCKE0B → CKE0: SDRAMs D[7:4]
RODT0A → ODT0: SDRAMs D[3:0], D8
RODT0B → ODT0: SDRAMs D[7:4]
PCK0A → CK: SDRAMs D[3:0], D8
PCK0B → CK: SDRAMs D[7:4]
PCK0A → CK: SDRAMs D[3:0], D8
PCK0B → CK: SDRAMs D[7:4]
VDDSPD
EVENT
SCL
SDA
SA0
SA0
EVENT SPD with SA1
Integrated SA2
SCL
TS
VSS
SDA
SA1
VDDSPD
SA2
VSS
Plan to use SPD with Integrated TS of Class B and
might be changed on customer’s requests. For more
details of SPD and Thermal sensor, please contact
local Hynix sales representative
Err_Out
RST: SDRAMs D[8:0]
S[3:2], CKE1, ODT1, are NC (Unused register inputs ODT1 and CKE1 have a 330Ω resistor to ground
Rev. 0.4 / Jul. 2009
11
RODT1B
A[N:O]/BA[N:O]
ODT
A[N:O]/BA[N:O]
A[O:N]/BA[N:O]
ODT
ODT
ODT
CK
CKE
A[N:O]/BA[N:O]
PCK1B
CK
WE
CAS
CK
CKE
CK
CKE
CK
CKE
CK
CAS
WE
WE
CAS
RAS
D16
CK
RAS
CS
D15
DQS
DQS
TDQS
TDQS
DQ [7:0]
ZQ
CK
WE
CAS
D14
DQS
DQS
TDQS
TDQS
DQ [7:0]
ZQ
PCK1B
RCKE1B
RS1B
CS
RAS
RAS
CS
ZQ
CS
RODT0B
A[N:O]B
/BA[N:O]B
A[N:O]/BA[N:O]
ODT
D13
DQS
DQS
TDQS
TDQS
DQ [7:0]
A[N:O]/BA[N:O]
ODT
ODT
ODT
ZQ
A[N:O]/BA[N:O]
CK
CKE
DQS
DQS
TDQS
TDQS
DQ [7:0]
A[N:O]/BA[N:O]
RWEB
PCK0B
RCASB
PCK0B
RCKE0B
CK
CKE
CK
WE
WE
CK
CK
CK
CKE
CK
CKE
CS
ZQ
D7
A[N:O]/BA[N:O]
ODT
VDDSPD
EVENT
Vtt
SCL
SDA
Note:
1. DQ-to-I/O wiring may be changed within a byte.
2. Unless otherwise noted, resistor values are 15Ω ± 5%.
3. ZQ resistors are 240Ω ± 1%. For all other resistor values
refer to the appropriate wiring diagram.
4. See the wiring diagrams for all resistors associated with the
command, address and control bus.
Rev. 0.4 / Jul. 2009
WE
DQS
DQS
TDQS
TDQS
DQ [7:0]
WE
DQS7
DQS7
DM7/DQS16
DQS16
DQ[63:56]
D6
CAS
CS
ZQ
RAS
DQS
DQS
TDQS
TDQS
DQ [7:0]
CAS
DQS6
DQS6
DM6/DQS15
DQS15
DQ55:48]
D5
CAS
CS
ZQ
RAS
DQS
DQS
TDQS
TDQS
DQ [7:0]
RAS
DQS5
DQS5
DM5/DQS14
DQS14
DQ[47:40]
D4
CAS
CS
ZQ
RAS
DQS
DQS
TDQS
TDQS
DQ [7:0]
CK
RS0B
RRASB
RODT1A
A[N:O]/BA[N:O]
ODT
ODT
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
ODT
ODT
A[O:N]/BA[N:O]
PCK1A
CK
WE
CK
CKE
CK
CKE
CK
CKE
CK
CKE
CK
CKE
CK
WE
D9
CAS
RAS
DQS4
DQS4
DM4/DQS13
DQS13
DQ[39:32]
Vtt
DQS
DQS
TDQS
TDQS
DQ [7:0]
ZQ
CK
WE
D10
CAS
CS
ZQ
RAS
DQS
DQS
TDQS
TDQS
DQ [7:0]
CK
WE
D11
CAS
CS
ZQ
RAS
DQS
DQS
TDQS
TDQS
DQ [7:0]
CK
WE
D12
CAS
CS
RAS
DQS
DQS
TDQS
TDQS
DQ [7:0]
ZQ
PCK1A
RCKE1A
RS1A
D17
CAS
CS
ZQ
RAS
DQS
DQS
TDQS
TDQS
DQ [7:0]
CS
A[N:O]A
/BA[N:O]A
RODT0A
ODT
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
ODT
ODT
A[N:O]/BA[N:O]
A[O:N]/BA[N:O]
ODT
ODT
A[N:O]/BA[N:O]
RWEA
PCK0A
RCASA
PCK0A
RCKE0A
CK
CKE
CK
CKE
CK
CKE
CK
CKE
CK
CKE
WE
D0
CAS
CS
CK
CAS
WE
WE
CAS
CS
D1
DQS
DQS
TDQS
TDQS
DQ [7:0]
ZQ
CK
WE
WE
DQS
DQS
TDQS
TDQS
DQ [7:0]
ZQ
DQS0
DQS0
DM0/DQS9
DQS9
DQ[7:0]
D2
CAS
CS
ZQ
DQS1
DQS1
DM1/DQS10
DQS10
DQ[15:8]
CAS
DQS
DQS
TDQS
TDQS
DQ [7:0]
RAS
DQS2
DQS2
DM2/DQS11
DQS11
DQ[23:16]
D3
CK
CS
ZQ
RAS
DQS
DQS
TDQS
TDQS
DQ [7:0]
RAS
DQS3
DQS3
DM3/DQS12
DQS12
DQ[31:24]
D8
CK
CS
ZQ
RAS
DQS
DQS
TDQS
TDQS
DQ [7:0]
RAS
DQS8
DQS8
DM8/DQS17
DQS17
CB[7:0]
CK
RS0A
RRASA
3.2 2GB, 256Mx72 Module(2Rank of x8) - page1
SA0
SA0
EVENT SPD with SA1
Integrated SA2
SCL
TS
SDA
VSS
SA1
VDDSPD
SA2
VSS
Plan to use SPD with Integrated TS of Class B and
might be changed on customer’s requests. For more
details of SPD and Thermal sensor, please contact
local Hynix sales representative
VDDSPD
Serial PD
VDD
D0–D17
VTT
VREFCA
D0–D17
VREFDQ
D0–D17
VSS
D0–D17
D0–D17
12
3.2.2 2GB, 256Mx72 Module(2Rank of x8)-page2
S0
1:2
S1
S[3:2] NC
BA[N:0]
R
E
G
I
S
T
E
R
/
P
L
L
A[N:0]
RAS
CAS
WE
CKE0
CKE1
ODT0
ODT1
CK0
120Ω
± 5%
CK0
CK1
CK1
120Ω
± 5%
PAR_IN
RS0A → CS0: SDRAMs D[3:0], D8
RS0B → CS0: SDRAMs D[7:4]
RS1A → CS1: SDRAMs D[12:9], D17
RS1B → CS1: SDRAMs D[16:13]
RBA[N:0]A → BA[N:0]: SDRAMs D[3:0], D[12:8], D17
RBA[N:0]B → BA[N:0]: SDRAMs D[7:4], D[16:13]
RA[N:0]A → A[N:0]: SDRAMs D[3:0], D[12:8], D17
RA[N:0]B → A[N:0]: SDRAMs D[7:4], D[16:13]
RRASA → RAS: SDRAMs D[3:0], D[12:8], D17
RRASB → RAS: SDRAMs D[7:4], D[16:13]
RCASA → CAS: SDRAMs D[3:0], D[12:8], D17
RCASB → CAS: SDRAMs D[7:4], D[16:13]
RWEA → WE: SDRAMs D[3:0], D[12:8], D17
RWEB → WE: SDRAMs D[7:4], D[16:13]
RCKE0A → CKE0: SDRAMs D[3:0], D8
RCKE0B → CKE0: SDRAMs D[7:4]
RCKE1A → CKE1: SDRAMs D[12:9], D17
RCKE1B → CKE1: SDRAMs D[16:13]
RODT0A → ODT0: SDRAMs D[3:0], D8
RODT0B → ODT0: SDRAMs D[7:4]
RODT1A → ODT1: SDRAMs D[12:9], D17
RODT1A → ODT1: SDRAMs D[16:13]
PCK0A → CK: SDRAMs D[3:0], D8
PCK0B → CK: SDRAMs D[7:4]
PCK1A → CK: SDRAMs D[12:9], D17
PCK1B → CK: SDRAMs D[16:13]
PCK0A → CK: SDRAMs D[3:0], D8
PCK0B → CK: SDRAMs D[7:4]
PCK1A → CK: SDRAMs D[12:9], D17
PCK1B → CK: SDRAMs D[16:13]
OERR Err_Out
RESET
RST
RST: SDRAMs D[17:0]
* S[3:2], CK1 and CK1 are NC
Rev. 0.4 / Jul. 2009
13
ODT
CK
CKE
CK
WE
A[O:N]/BA[O:N]
ODT
CK
CKE
CK
VSS
VSS
A[O:N]/BA[O:N]
ODT
CK
CKE
CK
WE
CAS
ODT
CK
CK
CKE
VSS
D15
A[O:N]/BA[O:N]
ZQ
WE
ODT
CK
CKE
VSS
D16
A[O:N]/BA[O:N]
ZQ
CK
RAS
CS
D14
CAS
RAS
CS
ZQ
WE
A[O:N]/BA[O:N]
ODT
CK
CKE
CK
WE
D7
WE
DQS
DQS
DM
DQ [3:0]
D13
CAS
DQS16
DQS16
VSS
DQ[63:60]
ZQ
ZQ
CAS
A[O:N]/BA[O:N]
ODT
CK
CKE
CK
WE
CAS
D6
RAS
DQS
DQS
DM
DQ [3:0]
CS
DQS15
DQS15
VSS
DQ[55;52]
ZQ
RAS
A[O:N]/BA[O:N]
ODT
CK
CKE
CK
WE
CAS
D5
CS
RODT0B
RWEB
PCK0B
A[O:N]B
/BA[O:N]B
VSS
A[O:N]/BA[O:N]
DQS
DQS
DM
DQ [3:0]
VSS
ODT
VSS
DQS14
DQS14
VSS
DQ[47:44]
VSS
CK
CKE
DQS
DQS
DM
DQ [3:0]
ZQ
CAS
RAS
DQS13
DQS13
VSS
DQ[39:36]
Vtt
VSS
D9
A[O:N]/BA[O:N]
ZQ
RAS
CS
CS
A[O:N]/BA[O:N]
ODT
CK
CKE
CK
WE
CAS
D10
PCK0B
RCKE0B
RCASB
DQS
DQS
DM
DQ [3:0]
ZQ
CK
DQS7
DQS7
VSS
DQ[59:56]
CS
A[O:N]/BA[O:N]
ODT
CK
CKE
CK
WE
CAS
D11
D4
WE
RS0B
RRASB
DQS
DQS
DM
DQ [3:0]
ZQ
CAS
DQS6
DQS6
VSS
DQ[51:48]
ZQ
RAS
A[O:N]/BA[O:N]
ODT
CK
CKE
CK
WE
CAS
D12
RAS
DQS
DQS
DM
DQ [3:0]
CS
VSS
VSS
DQS5
DQS5
VSS
DQ[43:40]
VSS
A[O:N]/BA[O:N]
DQS
DQS
DM
DQ [3:0]
VSS
ODT
DQS4
DQS4
VSS
DQ[35:32]
ZQ
CAS
RAS
RAS
CS
CS
A[O:N]/BA[O:N]
ODT
CK
CKE
CK
WE
D0
CK
CKE
DQS
DQS
DM
DQ [3:0]
ZQ
CK
DQS9
DQS9
VSS
DQ[7:4]
CS
A[O:N]/BA[O:N]
ODT
CK
CKE
CK
WE
CAS
D1
D17
WE
DQS
DQS
DM
DQ [3:0]
ZQ
ZQ
CAS
DQS10
DQS10
VSS
DQ[15:12]
CS
A[O:N]/BA[O:N]
ODT
CK
CKE
CK
WE
CAS
D2
RAS
DQS
DQS
DM
DQ [3:0]
CS
DQS11
DQS11
VSS
DQ23:20]
ZQ
RAS
A[O:N]/BA[O:N]
ODT
CK
CKE
CK
WE
CAS
D3
RAS
PCK0A
RCKE0A
RODT0A
RWEA
PCK0A
A[O:N]A
/BA[O:N]A
VSS
CAS
DQS
DQS
DM
DQ [3:0]
ZQ
CAS
CS
RAS
RAS
CS
CS
RAS
RAS
CS
A[O:N]/BA[O:N]
DQS
DQS
DM
DQ [3:0]
VSS
DQS0
DQS0
VSS
DQ[3:0]
DQS12
DQS12
VSS
DQ[31:28]
VSS
DQS
DQS
DM
DQ [3:0]
DQS
DQS
DM
DQ [3:0]
VSS
DQS1
DQS1
VSS
DQ[11;8]
DQS17
DQS17
VSS
CB[7:4]
VSS
DQS
DQS
DM
DQ [3:0]
ODT
DQS2
DQS2
VSS
DQ[19:16]
D8
CK
CKE
DQS
DQS
DM
DQ [3:0]
ZQ
CK
DQS3
DQS3
VSS
DQ[27:24]
RAS
DQS
DQS
DM
DQ [3:0]
CS
DQS8
DQS8
VSS
CB[3:0]
WE
RS0A
RRASA
RCASA
3.3 2GB, 256Mx72 Module(1Rank of x4)-page1
Vtt
VDDSPD
EVENT
SA0
SA0
SPD with SA1
Integrated SA2
TS
VSS
SA1
VDDSPD
EVENT
SCL
SCL
SDA
SDA
SA2
VSS
Plan to use SPD with Integrated TS of Class B and
might be changed on customer’s requests. For more
details of SPD and Thermal sensor, please contact
local Hynix sales representative
Note:
1. DQ-to-I/O wiring may be changed within a nibble.
2. Unless otherwise noted, resistor values are 15%.
Ω ±5
3. See the wiring diagrams for all resistors associated with the command, address and control bus.
4. ZQ resistors are 240 Ω
%.±For
1 all other resistor values refer to the
appropriate wiring diagram.
Rev. 0.4 / Jul. 2009
VDDSPD
SPD
VDD
D0–D17
VTT
VREFCA
D0–D17
VREFDQ
D0–D17
VSS
D0–D17
D0–D17
14
3.3 2GB, 256Mx72 Module(1Rank of x4)-page2
S0
S1
1:2
BA[N:0]
R
E
A[N:0]
G
RAS
I
S
T
E
R
/
P
L
L
CAS
WE
CKE0
ODT0
RS0A → CS0: SDRAMs D[3:0], D[12:8], D17
RS0B → CS0: SDRAMs D[7:4], D[16:13]
RS1A → CS1: SDRAMs D[12:9], D17
RS1B → CS1: SDRAMs D[16:13]
RBA[N:0]A → BA[N:0]: SDRAMs D[3:0], D[12:8], D17
RBA[N:0]B → BA[N:0]: SDRAMs D[7:4], D[16:13]
RA[N:0]A → A[N:0]: SDRAMs D[3:0], D[12:8], D17
RA[N:0]B → A[N:0]: SDRAMs D[7:4], D[16:13]
RRASA → RAS: SDRAMs D[3:0], D[12:8], D17
RRASB → RAS: SDRAMs D[7:4], D[16:13]
RCASA → CAS: SDRAMs D[3:0], D[12:8], D17
RCASB → CAS: SDRAMs D[7:4], D[16:13]
RWEA → WE: SDRAMs D[3:0], D[12:8], D17
RWEB → WE: SDRAMs D[7:4], D[16:13]
RCKE0A → CKE0: SDRAMs D[3:0], D[12:8], D17
RCKE0B → CKE0: SDRAMs D[7:4], D[16:13]
RODT0A → ODT0: SDRAMs D[3:0], D[12:8]. D17
RODT0B → ODT0: SDRAMs D[7:4], D[16:13]
CK0
PCK0A → CK: SDRAMs D[3:0], D8
PCK0B → CK: SDRAMs D[7:4]
CK0
PCK0A → CK: SDRAMs D[3:0], D8
PCK0B → CK: SDRAMs D[7:4]
PAR_IN
OERR Err_Out
RESET
RST
RST: SDRAMs D[17:0]
* S[3:2], CKE1, ODT1, CK1 and CK1 are NC (Unused register inputs ODT1 and CKE1 have a 330Ω resistor to ground.)
Rev. 0.4 / Jul. 2009
15
DQS0
DQS0
VSS
DQ[3:0]
DQS
DQS
DM
DQ [3:0]
Vtt
Rev. 0.4 / Jul. 2009
D0
D18
DQS9
DQS9
VSS
DQ[7:4]
DQS
DQS
DM
DQ [3:0]
D9
DQS
DQS
DM
DQ [3:0]
ODT
A[N:O]/BA[N:O]
D27
A[N:O]/BA[N:O]
D19
ODT
CK
CKE
DQS
DQS
DM
DQ [3:0]
CK
CKE
D21
D20
A[N:O]/BA[N:O]
ODT
CK
CKE
CK
WE
CAS
RAS
CS
A[N:O]/BA[N:O]
ODT
CK
CKE
CK
WE
CAS
RAS
CS
A[N:O]/BA[N:O]
ODT
CK
CKE
CK
WE
CAS
D26
A[N:O]/BA[N:O]
ODT
CK
CKE
DQS
DQS
DM
DQ [3:0]
CK
WE
CAS
RAS
CS
DQS
DQS
DM
DQ [3:0]
CK
WE
CAS
RAS
CS
A[N:O]/BA[N:O]
ODT
CK
CKE
CK
WE
CAS
DQS
DQS
DM
DQ [3:0]
CK
WE
CAS
RAS
D1
CS
D2
A[N:O]/BA[N:O]
ODT
CK
CKE
CK
WE
CAS
D3
A[N:O]/BA[N:O]
ODT
CK
CKE
CK
WE
CAS
RAS
D8
A[N:O]/BA[N:O]
ODT
DQS
DQS
DM
DQ [3:0]
CK
CKE
DQS1
DQS1
VSS
DQ[11:8]
CK
DQS
DQS
DM
DQ [3:0]
RAS
DQS2
DQS2
VSS
DQ[19:16]
RAS
DQS
DQS
DM
DQ [3:0]
CS
DQS3
DQS3
VSS
DQ[27:24]
RAS
CS
A[N:O]/BA[N:O]
ODT
DQS
DQS
DM
DQ [3:0]
CS
CS
A[N:O]/BA[N:O]
ODT
CK
CKE
CK
WE
CAS
RAS
CS
DQS8
DQS8
VSS
CB[3:0]
WE
CAS
RAS
D28
CS
D29
A[N:O]/BA[N:O]
ODT
CK
CKE
D30
A[N:O]/BA[N:O]
ODT
CK
CKE
CK
WE
CAS
RAS
CS
A[N:O]/BA[N:O]
ODT
CK
CKE
CK
WE
CAS
D35
A[N:O]/BA[N:O]
ODT
DQS
DQS
DM
DQ [3:0]
CK
CKE
DQS
DQS
DM
DQ [3:0]
CK
CKE
DQS
DQS
DM
DQ [3:0]
CK
WE
CAS
RAS
CS
DQS
DQS
DM
DQ [3:0]
CK
WE
CAS
RAS
CS
A[N:O]/BA[N:O]
ODT
CK
CKE
CK
WE
CAS
DQS
DQS
DM
DQ [3:0]
CK
WE
CAS
RAS
D10
A[N:O]/BA[N:O]
D11
A[N:O]/BA[N:O]
ODT
CK
CKE
CK
WE
CAS
D12
A[N:O]/BA[N:O]
ODT
CK
CKE
CK
WE
CAS
RAS
DQS
DQS
DM
DQ [3:0]
D17
CS
CS
DQS10
DQS10
VSS
DQ[15:12]
RAS
DQS
DQS
DM
DQ [3:0]
ODT
CS
DQS11
DQS11
VSS
DQ[23:20]
RAS
DQS
DQS
DM
DQ [3:0]
CK
CKE
CS
DQS12
DQS12
VSS
DQ[31:28]
RAS
DQS
DQS
DM
DQ [3:0]
CK
CS
DQS17
DQS17
VSS
CB[7:4]
WE
CAS
RAS
CS
R0DT1A
RCKE1A
PCK1A
PCK1A
RS1A
A[O:N]A
/BA[O:N]A
RODT0A
PCK0A
RCKE0A
PCK0A
RWEA
RCASA
RS0A
RRASA
R0DT1A
RCKE1A
PCK1A
PCK1A
RS1A
A[O:N]A
/BA[O:N]A
RODT0A
PCK0A
RCKE0A
PCK0A
RWEA
RCASA
RS0A
RRASA
3.4 4GB, 512Mx72 Module(2Rank of x4)-page1
Vtt
16
Vtt
R0DT1B
A[N:O]/BA[N:O]
ODT
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
ODT
ODT
ODT
CK
CKE
CK
CKE
CK
CKE
CK
WE
D24
CAS
A[N:O]/BA[N:O]
PCK1B
RCKE1B
CK
CKE
CK
WE
DQS
DQS
DM
DQ [3:0]
CK
WE
D33
CAS
RAS
CS
DQS
DQS
DM
DQ [3:0]
CK
WE
D23
CAS
RAS
CS
DQS
DQS
DM
DQ [3:0]
RAS
PCK1B
RS1B
D31
CAS
RAS
CS
DQS
DQS
DM
DQ [3:0]
CS
A[N:O]B
/BA[N:O]B
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
ODT
ODT
CK
CKE
CK
D6
A[N:O]/BA[N:O]
CK
CKE
ODT
ODT
CK
CKE
CK
WE
CAS
D15
A[N:O]/BA[N:O]
PCK0B
RCKE0B
RODT0B
RWEB
CK
WE
CAS
D5
CAS
RAS
CS
CS
RAS
RAS
CK
CKE
DQS
DQS
DM
DQ [3:0]
CK
DQS6
DQS6
VSS
DQ[51:48]
PCK0B
RCASB
DQS
DQS
DM
DQ [3:0]
WE
DQS15
DQS15
VSS
DQ[55:52]
CAS
DQS
DQS
DM
DQ [3:0]
D13
WE
RS0B
RRASB
DQS5
DQS5
VSS
DQ[43:40]
RAS
DQS
DQS
DM
DQ [3:0]
CS
DQS13
DQS13
VSS
DQ[39:36]
CS
RCKE1B
R0DT1B
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
ODT
ODT
A[N:O]/BA[N:O]
ODT
ODT
CK
CKE
CK
CKE
WE
CAS
D25
A[N:O]/BA[N:O]
CK
WE
CAS
CK
CKE
CK
CKE
CK
WE
CAS
DQS
DQS
DM
DQ [3:0]
CK
WE
CAS
D34
CK
RAS
PCK1B
PCK1B
RS1B
CS
RAS
RAS
CS
D22
DQS
DQS
DM
DQ [3:0]
CS
A[N:O]B
/BA[N:O]B
A[N:O]/BA[N:O]
D32
DQS
DQS
DM
DQ [3:0]
RAS
ODT
CK
CKE
CK
DQS
DQS
DM
DQ [3:0]
CS
ODT
CK
CKE
CK
WE
WE
A[N:O]/BA[N:O]
PCK0B
RCKE0B
RWEB
PCK0B
RODT0B
ODT
CK
CKE
CK
WE
CAS
CAS
D7
CAS
RAS
CS
CS
RAS
RAS
CS
D16
A[N:O]/BA[N:O]
DQS
DQS
DM
DQ [3:0]
D4
A[N:O]/BA[N:O]
DQS7
DQS7
VSS
DQ[59:56]
ODT
DQS
DQS
DM
DQ [3:0]
CK
CKE
DQS16
DQS16
VSS
DQ[63:60]
CK
DQS
DQS
DM
DQ [3:0]
D14
CAS
DQS4
DQS4
VSS
DQ[35:32]
RAS
DQS
DQS
DM
DQ [3:0]
CS
DQS14
DQS14
VSS
DQ[47:44]
WE
RS0B
RRASB
RCASB
3.4 4GB, 512Mx72 Module(2Rank of x4)-page2
Vtt
VDDSPD
SPD
VDD
D0–D35
VTT
VREFCA
D0–D35
VREFDQ
D0–D35
VSS
D0–D35
D0–D35
VDDSPD
EVENT
SCL
SDA
SA0
SA0
EVENT SPD with SA1
Integrated SA2
SCL
TS
SDA
VSS
SA1
VDDSPD
SA2
VSS
Plan to use SPD with Integrated TS of Class B and
might be changed on customer’s requests. For more
details of SPD and Thermal sensor, please contact
local Hynix sales representative
Note:
1. DQ-to-I/O wiring may be changed within a nibble.
2. See wiring diagrams for all resistors values.
3. ZQ pins of each SDRAM are connected to individual RZQ resistors (240+/-1%) ohms.
Rev. 0.4 / Jul. 2009
17
3.4 4GB, 512Mx72 Module(2Rank of x4)-page3
S0
1:2
S1
R
E
G
I
S
T
E
R
/
P
L
L
BA[N:0]
A[N:0]
RAS
CAS
WE
CKE0
CKE1
ODT0
ODT1
CK0
CK0
CK1
CK1
120Ω
± 5%
PAR_IN
RS0A → CS0: SDRAMs D[3:0], D[12:8], D17
RS0B → CS0: SDRAMs D[7:4], D[16:13]
RS1A → CS1: SDRAMs D[21:18], D[30:26], D35
RS1B → CS1: SDRAMs D[25:22], D[34:31]
RBA[N:0]A → BA[N:0]: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
RBA[N:0]B → BA[N:0]: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
RA[N:0]A → A[N:0]: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
RA[N:0]B → A[N:0]: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
RRASA → RAS: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
RRASB → RAS: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
RCASA → CAS: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
RCASB → CAS: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
RWEA → WE: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
RWEB → WE: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
RCKE0A → CKE0: SDRAMs D[3:0], D[12:8], D17
RCKE0B → CKE0: SDRAMs D[7:4], D[16:13]
RCKE1A → CKE1: SDRAMs D[21:18], D[30:26], D35
RCKE1B → CKE1: SDRAMs D[25:22], D[34:31]
RODT0A → ODT0: SDRAMs D[3:0], D[12:8], D17
RODT0B → ODT0: SDRAMs D[7:4], D[16:13]
RODT1A → ODT1: SDRAMs D[21:18], D[30:26], D35
RODT1A → ODT1: SDRAMs D[25:22], D[34:31]
PCK0A → CK: SDRAMs D[3:0], D[12:8], D17
PCK0B → CK: SDRAMs D[7:4], D[16:13]
PCK1A → CK: SDRAMs D[21:18], D[30:26], D35
PCK1B → CK: SDRAMs D[25:22], D[34:31]
PCK0A → CK: SDRAMs D[3:0], D[12:8], D17
PCK0B → CK: SDRAMs D[7:4], D[16:13]
PCK1A → CK: SDRAMs D[21:18], D[30:26], D35
PCK1B → CK: SDRAMs D[25:22], D[34:31]
Err_Out
RESET
RST
RST: SDRAMs D[35:0]
* S[3:2], CK1 and CK1 are NC
Rev. 0.4 / Jul. 2009
18
CS
CS
CS
CS
DQS
DQS
TDQS
TDQS
DQ [7:0]
ZQ
DQS8
DQS8
DM8/TDQS17
TDQS17
CB[7:0]
DQS
DQS
TDQS
TDQS
DQ [7:0]
ZQ
Rev. 0.4 / Jul. 2009
U6
U15
CKE
U24
BA[N:O]
BA[N:O]
CKE
ODT
U32
A[N:O]
CKE
DQS
DQS
TDQS
TDQS
DQ [7:0]
ZQ
ODT
CKE
CK
CK
WE
CAS
BA[N:O]
A[N:O]
ODT
DQS
DQS
TDQS
TDQS
DQ [7:0]
ZQ
CK
CK
WE
CAS
CS
CKE
CK
CK
WE
CAS
RAS
BA[N:O]
A[N:O]
ODT
DQS
DQS
TDQS
TDQS
DQ [7:0]
ZQ
CK
CK
CS
RAS
BA[N:O]
A[N:O]
ODT
CKE
CK
CK
WE
PCK0
CK
ODT
BA[N:O]
A[N:O]
ODT
CKE
CK
CK
WE
CAS
RAS
CS
BA[N:O]
A[N:O]
ODT
CKE
VDD
WCKE1
PCK2
PCK2
CS3
WODT1
WCKE0
PCK2
PCK2
CK
CS2
VDD
CK
WE
CAS
RAS
CS
BA[N:O]
A[N:O]
WCKE01
PCK0
PCK0
CKE
CK
CS1
CK
WE
CAS
RAS
CS
WA[N:0]
WBA[N:0]
A[N:O]
DQS
DQS
TDQS
TDQS
DQ [7:0]
ZQ
A[N:O]
DQS
DQS
TDQS
TDQS
DQ [7:0]
ZQ
WE
CAS
U23
CS
U22
RAS
BA[N:O]
U21
RAS
BA[N:O]
A[N:O]
ODT
CKE
CK
CK
WE
CAS
RAS
CS
BA[N:O]
U20
CS
BA[N:O]
CKE
A[N:O]
ODT
DQS
DQS
TDQS
TDQS
DQ [7:0]
ZQ
A[N:O]
DQS
DQS
TDQS
TDQS
DQ [7:0]
ZQ
CK
CK
WE
CAS
RAS
CS
BA[N:O]
ODT
A[N:O]
DQS
DQS
TDQS
TDQS
DQ [7:0]
ZQ
CK
CK
CAS
RAS
ODT
A[N:O]
CKE
CK
CK
WE
WWE
PCK0
CK
WCAS
WE
WRAS
CS0
CAS
BA[N:O]
DQS
DQS
TDQS
TDQS
DQ [7:0]
ZQ
ODT
DQS
DQS
TDQS
TDQS
DQ [7:0]
ZQ
WE
U14
CS
BA[N:O]
U13
CAS
ODT
A[N:O]
CK
CKE
U12
RAS
CK
CK
WE
CS
CAS
RAS
U11
CS
BA[N:O]
A[N:O]
DQS
DQS
TDQS
TDQS
DQ [7:0]
ZQ
CKE
DQS
DQS
TDQS
TDQS
DQ [7:0]
ZQ
CKE
CK
WE
CS
CAS
RAS
DQS
DQS
TDQS
TDQS
DQ [7:0]
ZQ
CK
CK
CS
CAS
BA[N:O]
A[N:O]
ODT
CKE
CK
CK
WE
CAS
DQS
DQS
TDQS
TDQS
DQ [7:0]
ZQ
ODT
DQS
DQS
TDQS
TDQS
DQ [7:0]
ZQ
WE
U5
RAS
U4
CAS
BA[N:O]
A[N:O]
ODT
CKE
CK
CK
WE
CAS
U3
RAS
BA[N:O]
A[N:O]
ODT
CKE
CK
CK
WE
CAS
U2
CS
BA[N:O]
A[N:O]
ODT
CKE
CK
CK
WE
CAS
CS
RAS
WCKE0
DQS3
DQS3
DM3/TDQS12
TDQS12
DQ[31:24]
WODT0
DQS
DQS
TDQS
TDQS
DQ [7:0]
ZQ
CKE
DQS2
DQS2
DM2/TDQS11
TDQS11
DQ[32:16]
ODT
DQS
DQS
TDQS
TDQS
DQ [7:0]
ZQ
RAS
DQS1
DQS1
DM1/TDQS10
TDQS10
DQ[15:8]
RAS
DQS
DQS
TDQS
TDQS
DQ [7:0]
ZQ
RAS
DQS0
DQS0
DM0/TDQS9
TDQS9
DQ[7:0]
RAS
3.5 4GB, 512Mx72 Module(4Rank of x8)-page1
U29
U30
U31
U33
Vtt
19
BA[N:O]
VDD
ODT
A[N:O]
WCKE1
PCK2
CK
CK
WE
CKE
PCK2
BA[N:O]
ODT
A[N:O]
CKE
CK
CK
ODT
A[N:O]
BA[N:O]
ODT
BA[N:O]
CKE
CK
A[N:O]
DQS
DQS
TDQS
TDQS
DQ [7:0]
ZQ
CKE
CK
U36
WE
CAS
DQS
DQS
TDQS
TDQS
DQ [7:0]
ZQ
CK
CAS
WE
WE
CAS
U35
CK
CAS
CS3
CS
RAS
RAS
CS
CS
RAS
BA[N:O]
A[N:O]
A[N:O]
BA[N:O]
CKE
ODT
U34
DQS
DQS
TDQS
TDQS
DQ [7:0]
ZQ
CS
A[N:O]
BA[N:O]
ODT
CKE
CKE
ODT
CK
U28
DQS
DQS
TDQS
TDQS
DQ [7:0]
ZQ
RAS
A[N:O]
BA[N:O]
WCKE0
WODT1
CKE
ODT
PCK2
PCK2
CK
WE
CK
CK
U27
WE
CAS
DQS
DQS
TDQS
TDQS
DQ [7:0]
ZQ
DQS
DQS
TDQS
TDQS
DQ [7:0]
ZQ
CK
WE
CAS
CK
CK
WE
CAS
U26
CK
CAS
CS
RAS
RAS
CS
CS
RAS
BA[N:O]
BA[N:O]
U25
DQS
DQS
TDQS
TDQS
DQ [7:0]
ZQ
CS
BA[N:O]
ODT
A[N:O]
CKE
CKE
A[N:O]
ODT
ODT
A[N:O]
CKE
U19
DQS
DQS
TDQS
TDQS
DQ [7:0]
ZQ
RAS
BA[N:O]
CS2
VDD
WCKE01
CKE
ODT
CK
CK
CK
CK
U18
WE
CAS
CK
WE
CAS
CK
CK
WE
CAS
U17
DQS
DQS
TDQS
TDQS
DQ [7:0]
ZQ
DQS
DQS
TDQS
TDQS
DQ [7:0]
ZQ
A[N:O]
PCK0
PCK0
CK
WE
CAS
CS1
CS
RAS
RAS
CS
CS
RAS
BA[N:O]
A[N:O]
A[N:O]
BA[N:O]
U16
DQS
DQS
TDQS
TDQS
DQ [7:0]
ZQ
CS
A[N:O]
BA[N:O]
CK
ODT
CKE
CKE
ODT
CK
CK
CKE
U10
DQS
DQS
TDQS
TDQS
DQ [7:0]
ZQ
RAS
WA[N:0]
WBA[N:0]
A[N:O]
BA[N:O]
PCK0
WCKE0
WODT0
CK
CKE
ODT
WWE
PCK0
CK
CK
U9
ODT
CAS
RAS
CS
CS
CAS
RAS
CK
DQS
DQS
TDQS
TDQS
DQ [7:0]
ZQ
U8
CK
WCAS
DQS3
DQS3
DM3/TDQS12
TDQS12
DQ[31:24]
WE
WRAS
DQS
DQS
TDQS
TDQS
DQ [7:0]
ZQ
WE
DQS6
DQS6
DM6/TDQS15
TDQS15
DQ[55:48]
U7
WE
DQS
DQS
TDQS
TDQS
DQ [7:0]
ZQ
CS
DQS5
DQS5
DM5/TDQS14
TDQS14
DQ[47:40]
CAS
DQS
DQS
TDQS
TDQS
DQ [7:0]
ZQ
RAS
DQS4
DQS4
DM4/TDQS13
TDQS13
DQ[39:32]
WE
CS0
CAS
CS
RAS
3.5 4GB, 512Mx72 Module(4Rank of x8)-page2
U37
Vtt
VDDSPD
EVENT
SCL
SDA
VDDSPD
SA0
SA0
EVENT SPD with SA1
Integrated SA2
SCL
TS
VSS
SDA
SA1
SA2
Plan to use SPD with Integrated TS of Class B and
might be changed on customer’s requests. For more
details of SPD and Thermal sensor, please contact
local Hynix sales representative
VSS
VDDSPD
Notes:
1. DQ-to-I/O wiring may be changed within a byte.
2. See wiring diagrams for resistor values.
3. ZQ pins of each SDRAM are connected to individual RZQ resistors (240+/-1%) ohms.
Rev. 0.4 / Jul. 2009
VDD
Serial PD
U1–U37
VTT
VREFCA
U1-U37
VREFDQ
U1-U37
VSS
U1-U37
20
3.5 4GB, 512Mx72 Module(4Rank of x8)-page3
S0
S1
S2
S3
BA[N:0]
1:2
R
E
G
I
S
T
E
R
/
P
L
L
A[N:0]
RAS
CAS
WE
CKE0
CKE1
ODT0
ODT1
CK0
CK0
CK1
CK1
120Ω
± 5%
PAR_IN
CS0 → CS0: SDRAMs U[10:2]
CS1 → CS1: SDRAMs U[19:11]
CS2 → CS2: SDRAMs U[28:20]
CS3 → CS3: SDRAMs U[37:29]
WBA[N:0] → BA[N:0]: SDRAMs U[6:2], U[15:11], U[24:20], U[33:29]
EBA[N:0] → BA[N:0]: SDRAMs U[10:7], U[19:16], U[28:25], U[37:34]
WA[N:0] → A[N:0]: SDRAMs U[6:2], U[15:11], U[24:20], U[33:29]
EA[N:0] → A[N:0]: SDRAMs U[10:7], U[19:16], U[28:25], U[37:34]
WRAS → RAS: SDRAMs U[6:2], U[15:11], U[24:20], U[33:29]
ERAS → RAS: SDRAMs U[10:7], U[19:16], U[28:25], U[37:34]
WCAS → CAS: SDRAMs U[6:2], U[15:11], U[24:20], U[33:29]
ECAS → CAS: SDRAMs U[10:7], U[19:16], U[28:25], U[37:34]
WWE → WE: SDRAMs U[6:2], U[15:11], U[24:20], U[33:29]
EWE → WE: SDRAMs U[10:7], U[19:16], U[28:25], U[37:34]
WCKE0 → CKE0: SDRAMs U[6:2], U[24:20]
ECKE0 → CKE0: SDRAMs U[10:7], U[28:25]
WCKE1 → CKE1: SDRAMs U[15:11], U[33:29]
ECKE1 → CKE1: SDRAMs U[19:16], U[37:34]
WODT0 → ODT0: SDRAMs U[6:2]
EODT0 → ODT0: SDRAMs U[10:7]
WODT0 → ODT1: SDRAMs U[24:20]
EODT0 → ODT1: SDRAMs U[28:25]
PCK0 → CK: SDRAMs U[6:2], U[15:11]
PCK1 → CK: SDRAMs U[10:7], U[28:25]
PCK2 → CK: SDRAMs U[24:20], U[33:29]
PCK3 → CK: SDRAMs U[19:16], U[37:34]
PCK0 → CK: SDRAMs U[6:2], U[15:11]
PCK1 → CK: SDRAMs U[10:7], U[28:25]
PCK2 → CK: SDRAMs U[24:20], U[33:29]
PCK3 → CK: SDRAMs U[19:16], U[37:34]
Err_Out
RESET
RST
RST: SDRAMs U[37:2]
Rev. 0.4 / Jul. 2009
21
VSS
DQS0
DQS0
VSS
DQ[3:0]
ZQ
DQS
DQS
DM
DQ [3:0]
Rev. 0.4 / Jul. 2009
D1
ZQ
DQS
DQS
DM
DQ [3:0]
D0
D53
ZQ
DQS
DQS
DM
DQ [3:0]
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
D52
ODT
D50
ODT
CK
CKE
ZQ
DQS
DQS
DM
DQ [3:0]
CK
CKE
D46
D48
A[N:O]/BA[N:O]
ODT
CK
CKE
CK
WE
A[N:O]/BA[N:O]
ODT
CK
CKE
CK
WE
CAS
RAS
CS
D44
A[N:O]/BA[N:O]
ODT
CK
CKE
ZQ
DQS
DQS
DM
DQ [3:0]
CK
WE
CAS
RAS
CS
ZQ
DQS
DQS
DM
DQ [3:0]
CK
WE
CAS
RAS
CS
A[N:O]/BA[N:O]
ODT
CK
CKE
ZQ
DQS
DQS
DM
DQ [3:0]
CK
WE
VSS
CAS
VSS
RAS
CS
VSS
CAS
VSS
RAS
D51
A[N:O]/BA[N:O]
ODT
CK
WE
CAS
RAS
VSS
CS
D49
A[N:O]/BA[N:O]
ODT
CK
CKE
D47
A[N:O]/BA[N:O]
ODT
CK
CKE
CK
WE
CAS
CS
D45
A[N:O]/BA[N:O]
ODT
ZQ
DQS
DQS
DM
DQ [3:0]
CK
CKE
ZQ
DQS
DQS
DM
DQ [3:0]
CK
CKE
ZQ
DQS
DQS
DM
DQ [3:0]
CK
WE
CAS
ZQ
DQS
DQS
DM
DQ [3:0]
CK
WE
CAS
RAS
CS
A[N:O]/BA[N:O]
ODT
CK
CKE
ZQ
DQS
DQS
DM
DQ [3:0]
CK
WE
VSS
CAS
VSS
RAS
CS
VSS
RAS
CS
VSS
RAS
D2
A[N:O]/BA[N:O]
ODT
CK
WE
VSS
CS
D4
A[N:O]/BA[N:O]
ODT
CK
CKE
CK
WE
D6
A[N:O]/BA[N:O]
ODT
CK
CKE
CK
WE
CAS
RAS
CS
D8
A[N:O]/BA[N:O]
ODT
ZQ
DQS
DQS
DM
DQ [3:0]
CK
CKE
ZQ
DQS
DQS
DM
DQ [3:0]
CK
WE
CAS
ZQ
DQS
DQS
DM
DQ [3:0]
CK
CKE
CAS
RAS
CS
A[N:O]/BA[N:O]
ODT
CK
CKE
CK
CAS
WE
ZQ
DQS
DQS
DM
DQ [3:0]
CK
WE
VSS
CAS
VSS
RAS
CS
VSS
RAS
CS
A[N:O]/BA[N:O]
ODT
CK
CKE
CK
CAS
WE
VSS
CAS
D3
A[N:O]/BA[N:O]
D5
A[N:O]/BA[N:O]
ODT
CK
CKE
CK
CAS
WE
D7
A[N:O]/BA[N:O]
ODT
CK
CKE
CK
CAS
WE
RAS
ZQ
DQS
DQS
DM
DQ [3:0]
D9
RAS
CS
VSS
DQS1
DQS1
VSS
DQ[11:8]
RAS
ZQ
DQS
DQS
DM
DQ [3:0]
VSS
CS
CS
VSS
DQS2
DQS2
VSS
DQ[19:16]
RAS
ZQ
DQS
DQS
DM
DQ [3:0]
ODT
CS
VSS
DQS3
DQS3
VSS
DQ[27:24]
RAS
ZQ
DQS
DQS
DM
DQ [3:0]
CK
CKE
CS
VSS
DQS8
DQS8
VSS
CB[3:0]
CK
CAS
WE
RAS
CS
VDD
BRCKE1A
BRS3A
BRA[N:O]A
/BRBA[N:O]A
BRODT1A
BPCK0A
BRCKE0A
BPCK0A
BRWEA
BRCASA
BRS2A
BRRASA
VDD
ARCKE1A
ARS1A
ARA[N:O]A
/ARBA[N:O]A
ARODT0A
APCK0A
ARCKE0A
APCK0A
ARWEA
ARCASA
ARS0A
ARRASA
3.6 8GB, 1Gx72 Module(4Rank of x4)-page1
Vtt
22
VSS
DQS9
DQS9
VSS
DQ[7:4]
ZQ
DQS
DQS
DM
DQ [3:0]
Rev. 0.4 / Jul. 2009
D19
ZQ
DQS
DQS
DM
DQ [3:0]
D18
D71
ZQ
DQS
DQS
DM
DQ [3:0]
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
D70
ODT
D68
ODT
CK
CKE
ZQ
DQS
DQS
DM
DQ [3:0]
CK
CKE
D64
D66
A[N:O]/BA[N:O]
ODT
CK
CKE
CK
WE
A[N:O]/BA[N:O]
ODT
CK
CKE
CK
WE
CAS
RAS
CS
D62
A[N:O]/BA[N:O]
ODT
CK
CKE
ZQ
DQS
DQS
DM
DQ [3:0]
CK
WE
CAS
RAS
CS
ZQ
DQS
DQS
DM
DQ [3:0]
CK
WE
CAS
RAS
CS
A[N:O]/BA[N:O]
ODT
CK
CKE
ZQ
DQS
DQS
DM
DQ [3:0]
CK
WE
VSS
CAS
VSS
RAS
CS
VSS
CAS
VSS
RAS
D69
A[N:O]/BA[N:O]
ODT
CK
WE
CAS
RAS
VSS
CS
D67
A[N:O]/BA[N:O]
ODT
CK
CKE
D65
A[N:O]/BA[N:O]
ODT
CK
CKE
CK
WE
CAS
CS
D63
A[N:O]/BA[N:O]
ODT
ZQ
DQS
DQS
DM
DQ [3:0]
CK
CKE
ZQ
DQS
DQS
DM
DQ [3:0]
CK
CKE
ZQ
DQS
DQS
DM
DQ [3:0]
CK
WE
CAS
ZQ
DQS
DQS
DM
DQ [3:0]
CK
WE
CAS
RAS
CS
A[N:O]/BA[N:O]
ODT
CK
CKE
ZQ
DQS
DQS
DM
DQ [3:0]
CK
WE
VSS
CAS
VSS
RAS
CS
VSS
RAS
CS
VSS
RAS
D20
A[N:O]/BA[N:O]
ODT
CK
WE
VSS
CS
D22
A[N:O]/BA[N:O]
ODT
CK
CKE
CK
WE
D24
A[N:O]/BA[N:O]
ODT
CK
CKE
CK
WE
CAS
RAS
CS
D26
A[N:O]/BA[N:O]
ODT
ZQ
DQS
DQS
DM
DQ [3:0]
CK
CKE
ZQ
DQS
DQS
DM
DQ [3:0]
CK
WE
CAS
ZQ
DQS
DQS
DM
DQ [3:0]
CK
CKE
CAS
RAS
CS
A[N:O]/BA[N:O]
ODT
CK
CKE
CK
CAS
WE
ZQ
DQS
DQS
DM
DQ [3:0]
CK
WE
VSS
CAS
VSS
RAS
CS
VSS
RAS
CS
A[N:O]/BA[N:O]
ODT
CK
CKE
CK
CAS
WE
VSS
CAS
D21
A[N:O]/BA[N:O]
D23
A[N:O]/BA[N:O]
ODT
CK
CKE
CK
CAS
WE
D25
A[N:O]/BA[N:O]
ODT
CK
CKE
CK
CAS
WE
RAS
ZQ
DQS
DQS
DM
DQ [3:0]
D27
RAS
CS
VSS
DQS10
DQS10
VSS
DQ[11:8]
RAS
ZQ
DQS
DQS
DM
DQ [3:0]
VSS
CS
CS
VSS
DQS11
DQS11
VSS
DQ[23:20]
RAS
ZQ
DQS
DQS
DM
DQ [3:0]
ODT
CS
VSS
DQS12
DQS12
VSS
DQ[31:28]
RAS
ZQ
DQS
DQS
DM
DQ [3:0]
CK
CKE
CS
VSS
DQS17
DQS17
VSS
CB[7:4]
CK
CAS
WE
RAS
CS
VDD
BRCKE1A
BRS3A
BRA[N:O]A
/BRBA[N:O]A
BRODT1A
BPCK0A
BRCKE0A
BPCK0A
BRWEA
BRCASA
BRS2A
BRRASA
VDD
ARCKE1A
ARS1A
ARA[N:O]A
/ARBA[N:O]A
ARODT0A
APCK0A
ARCKE0A
APCK0A
ARWEA
ARCASA
ARS0A
ARRASA
3.6 8GB, 1Gx72 Module(4Rank of x4)-page2
Vtt
23
VSS
DQS7
DQS7
VSS
DQ[59:56
ZQ
DQS
DQS
DM
DQ [3:0]
Rev. 0.4 / Jul. 2009
D17
D16
D37
ZQ
DQS
DQS
DM
DQ [3:0]
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
D36
ODT
CK
CKE
D38
ODT
CK
CKE
ZQ
DQS
DQS
DM
DQ [3:0]
D40
A[N:O]/BA[N:O]
ODT
CK
CKE
CK
WE
CAS
RAS
CS
D42
A[N:O]/BA[N:O]
ODT
CK
CKE
CK
WE
CAS
RAS
CS
ZQ
DQS
DQS
DM
DQ [3:0]
CK
WE
CAS
ZQ
DQS
DQS
DM
DQ [3:0]
CK
WE
VSS
RAS
CS
VSS
CAS
VSS
RAS
A[N:O]/BA[N:O]
ODT
CK
CKE
CK
VSS
CS
D39
A[N:O]/BA[N:O]
ODT
CK
CKE
D41
A[N:O]/BA[N:O]
ODT
CK
CKE
WE
CAS
RAS
CS
D13
A[N:O]/BA[N:O]
ODT
ZQ
DQS
DQS
DM
DQ [3:0]
CK
CKE
ZQ
DQS
DQS
DM
DQ [3:0]
CK
WE
CAS
ZQ
DQS
DQS
DM
DQ [3:0]
CK
WE
CAS
RAS
CS
ZQ
DQS
DQS
DM
DQ [3:0]
CK
WE
VSS
CAS
VSS
RAS
CS
VSS
RAS
A[N:O]/BA[N:O]
ODT
CK
CKE
CK
WE
VSS
CS
D14
A[N:O]/BA[N:O]
ODT
D12
A[N:O]/BA[N:O]
ODT
CK
CKE
CK
WE
CAS
RAS
CS
D10
A[N:O]/BA[N:O]
ODT
ZQ
DQS
DQS
DM
DQ [3:0]
CK
CKE
ZQ
DQS
DQS
DM
DQ [3:0]
CK
WE
CAS
ZQ
DQS
DQS
DM
DQ [3:0]
CK
CKE
CAS
RAS
CS
A[N:O]/BA[N:O]
ODT
CK
CKE
CK
CAS
WE
ZQ
DQS
DQS
DM
DQ [3:0]
CK
WE
VSS
CAS
VSS
RAS
CS
VSS
RAS
D15
A[N:O]/BA[N:O]
D13
A[N:O]/BA[N:O]
ODT
CK
CKE
CK
CAS
WE
D11
A[N:O]/BA[N:O]
ODT
CK
CKE
CK
CAS
WE
RAS
ZQ
DQS
DQS
DM
DQ [3:0]
VSS
CS
CS
VSS
DQS6
DQS6
VSS
DQ[51:48]
RAS
ZQ
DQS
DQS
DM
DQ [3:0]
ODT
CS
VSS
DQS5
DQS5
VSS
DQ[43:40]
RAS
ZQ
DQS
DQS
DM
DQ [3:0]
CK
CKE
CS
VSS
DQS4
DQS4
VSS
DQ[35:32]
CK
CAS
WE
RAS
CS
VDD
BRCKE1B
BRS3B
BRA[N:O]B
/BRBA[N:O]B
BRODT1B
BPCK0B
BRCKE0B
BPCK0B
BRWEB
BRCASB
BRS2B
BRRASB
VDD
ARCKE1B
ARS1B
ARA[N:O]B
/ARBA[N:O]B
ARODT0B
APCK0B
ARCKE0B
APCK0B
ARWEB
ARCASB
ARS0B
ARRASB
3.6 8GB, 1Gx72 Module(4Rank of x4)-page3
Vtt
24
BRCKE1B
VDD
A[N:O]/BA[N:O]
CK
CKE
CK
ODT
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
ODT
ODT
ODT
CK
CKE
CK
CKE
CK
CKE
CAS
WE
WE
CK
CK
WE
WE
D54
CK
CS
RAS
RAS
CS
CAS
CAS
RAS
CS
D56
ZQ
DQS
DQS
DM
DQ [3:0]
CS
A[N:O]/BA[N:O]
D58
ZQ
DQS
DQS
DM
DQ [3:0]
CAS
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
ODT
ODT
CK
CKE
WE
D55
D60
ZQ
DQS
DQS
DM
DQ [3:0]
RAS
A[N:O]/BA[N:O]
CK
CKE
CK
ODT
ODT
CK
CKE
VSS
ZQ
DQS
DQS
DM
DQ [3:0]
CAS
CK
CKE
D57
ZQ
DQS
DQS
DM
DQ [3:0]
A[N:O]/BA[N:O]
BRS3B
BRA[N:O]B
/BRBA[N:O]B
BPCK0B
BRCKE0B
BRODT1B
BRWEB
BPCK0B
BRCASB
WE
VSS
WE
CAS
RAS
CK
WE
D59
CK
CAS
RAS
CS
VSS
CK
BRS2B
BRRASB
CAS
RAS
CS
D61
ZQ
DQS
DQS
DM
DQ [3:0]
CS
ODT
CK
CKE
CK
WE
CAS
D34
A[N:O]/BA[N:O]
VSS
ZQ
DQS
DQS
DM
DQ [3:0]
VSS
ZQ
DQS
DQS
DM
DQ [3:0]
CS
A[N:O]/BA[N:O]
ODT
CK
CKE
CK
WE
D32
ZQ
DQS
DQS
DM
DQ [3:0]
RAS
VDD
ODT
CK
CKE
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
ODT
CK
CKE
VSS
CAS
CS
CK
WE
D30
CAS
RAS
CS
VSS
ZQ
DQS
DQS
DM
DQ [3:0]
CS
CK
WE
D28
CAS
RAS
CS
VSS
ZQ
DQS
DQS
DM
DQ [3:0]
RAS
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
ZQ
DQS
DQS
DM
DQ [3:0]
RAS
A[N:O]/BA[N:O]
CK
CKE
ODT
ODT
CK
CKE
VSS
D35
ARCKE1B
ARS1B
ARA[N:O]B
/ARBA[N:O]B
APCK0B
ARCKE0B
ARODT0B
ARWEB
CAS
WE
CK
CAS
WE
CK
CAS
WE
D33
CAS
WE
RAS
CS
CS
RAS
RAS
CS
VSS
ODT
ZQ
DQS
DQS
DM
DQ [3:0]
D31
CK
CKE
VSS
DQS16
DQS16
VSS
DQ[63:60]
VSS
ODT
ZQ
DQS
DQS
DM
DQ [3:0]
D29
CK
CKE
VSS
DQS15
DQS15
VSS
DQ[55:52]
APCK0B
ARCASB
ZQ
DQS
DQS
DM
DQ [3:0]
VSS
CK
VSS
DQS14
DQS14
VSS
DQ[47:44]
RAS
ZQ
DQS
DQS
DM
DQ [3:0]
CS
VSS
DQS13
DQS13
VSS
DQ[39:36]
CK
ARS0B
ARRASB
3.6 8GB, 1Gx72 Module(4Rank of x4)-page4
Vtt
VDDSPD
VDD
SPD
D0–D71
VTT
VREFCA
D0–D71
VREFDQ
D0–D71
VSS
D0–D71
VDDSPD
EVENT
SCL
SDA
VDDSPD
SA0
SA0
EVENT SPD with SA1
Integrated SA2
SCL
TS
SDA
VSS
SA1
SA2
VSS
Plan to use SPD with Integrated TS of Class B and
might be changed on customer’s requests. For more
details of SPD and Thermal sensor, please contact
local Hynix sales representative
Note:
1. DQ-to-I/O wiring may be changed within a nibble.
2. Unless otherwise noted, resistor values are 15 Ohms ± 5%.
3. See the wiring diagrams for all resistors associated with the command, address and
control bus.
4. ZQ resistors are 240 Ohms ± 1%. For all other resistor values refer to the appropriate
wiring diagram.
Rev. 0.4 / Jul. 2009
25
3.6 8GB, 1Gx72 Module(4Rank of x4)-page5
S0
ARS0A → CS1: SDRAMs D1,D3,D5,D7 D9,
D19, D21, D23, D25, D27
ARS0B → CS1: SDRAMs D11, D13, D15, D17,
D29, D31, D33, D35
1:2
WE
R
E
G
I
S
T
E
R
/
P
L
L
CKE0
A
S1
BA[N:0]
A[N:0]
RAS
CAS
ODT0
CK0
120Ω
± 5%
CK0
RESET
1:2
S3
ARS1A → CS0: SDRAMs D0, D2, D4, D6, D8,
D18, D20, D22, D24, D26
ARS1B → CS0: SDRAMs D10, D12, D14, D16,
D28, D30, D32, D34
ARBA[N:0]A → BA[N:0]: SDRAMs D[9:0],D[27:18] BA[N:0]
ARBA[N:0]B → BA[N:0]: SDRAMs D[17:10],D[35:28]
ARA[N:0]A → A[N:0]: SDRAMs D[9:0],D[27:18]
A[N:0]
ARA[N:0]B → A[N:0]: SDRAMs D[17:10],D[35:28]
RAS
ARRASA → RAS: SDRAMs D[9:0],D[27:18]
ARRASB → RAS: SDRAMs D[17:10],D[35:28]
ARCASA → CAS: SDRAMs D[9:0],D[27:18]
CAS
ARCASB → CAS: SDRAMs D[17:10],D[35:28]
ARWEA → WE: SDRAMs D[9:0],D[27:18]
WE
ARWEB → WE: SDRAMs D[17:10],D[35:28]
ARCKE0A → CKE1: SDRAMs D1,D3,D5,D7,D9,
CKE0
D19, D21, D23, D25, D27
ARCKE0B → CKE1: SDRAMs D11,D13,D15,D17,
D29, D31, D33, D35
CKE1
ARCKE1A → CKE0: SDRAMs D0,D2,D4,D6,D8,
D18, D20, D22, D24, D26
ARCKE1B → CKE0: SDRAMs D10,D12,D14,D16,
D28, D30, D32, D34
ARODT0A → ODT1: SDRAMs D1,D3,D5,D7,D9,
ODT1
D19, D21, D23, D25, D27
ARODT0B → ODT0: SDRAMs D11,D13,D15,D17,
D29, D31, D33, D35
APCK0A → CK: SDRAMs D[9:0]
CK0
APCK0B → CK: SDRAMs D[17:10]
120Ω
APCK1A → CK: SDRAMs D[27:18]
± 5%
APCK1B → CK: SDRAMs D[35:28]
APCK0A → CK: SDRAMs D[9:0]
CK0
APCK0B → CK: SDRAMs D[17:10]
APCK1A → CK: SDRAMs D[27:18]
APCK1B → CK: SDRAMs D[35:28]
CKE1
PAR_IN
S2
Err_Out
RST
R
E
G
I
S
T
E
R
/
P
L
L
B
PAR_IN
RESET
BRS2A → CS1: SDRAMs D45,D47,D49,D51,D53
D63,D65,D67,D69,D71
BRS2B → CS1: SDRAMs D37,D39,D41,D43,
D55,D57,D59,D61
BRS3A → CS0: SDRAMs D44.D46,D48,D50,D52,
D62,D64,D66,D68,D70
BRS3B → CS0: SDRAMs D36,D38,D40,D42,
D54,D56,D58,D60
BRBA[N:0]A → BA[N:0]: SDRAMs D[53:44],D[71:62]
BRBA[N:0]B → BA[N:0]: SDRAMs D[43:36],D[61:54]
BRA[N:0]A → A[N:0]: SDRAMs D[55:44],D[71:62]
BRA[N:0]B → A[N:0]: SDRAMs D[43:36],D[61:54]
BRRASA → RAS: SDRAMs D[53:44],D[71:62]
BRRASB → RAS: SDRAMs D[43:36],D[61:54]
BRCASA → CAS: SDRAMs D[53:44],D[71:62]
BRCASB → CAS: SDRAMs D[43:36],D[61:54]
BRWEA → WE: SDRAMs D[53:44],D[71:62]
BRWEB → WE: SDRAMs D[43:36],D[61:54]
BRCKE0A → CKE1: SDRAMs D45,D47,D49,D51,D53,
D63,D65,D67,D69,D71
BRCKE0B → CKE1: SDRAMs D37,D39,D41,D43,
D55,D57,D59,D61
BRCKE1A → CKE0: SDRAMs D44.D46,D48,D50,D52,
D62,D64,D66,D68,D70
BRCKE1B → CKE0: SDRAMs D36,D38,D40,D42,
D54,D56,D58,D60
BRODT1A → ODT1: SDRAMs D45,D47,D49,D51,D53
D63,D65,D67,D69,D71
BRODT1B → ODT0: SDRAMs D37,D39,D41,D43
D55,D57,D59,D61
BPCK0A → CK: SDRAMs D[53:44]
BPCK0B → CK: SDRAMs D[43:36]
BPCK1A → CK: SDRAMs D[71:62]
BPCK1B → CK: SDRAMs D[61:54]
BPCK0A → CK: SDRAMs D[53:44]
BPCK0B → CK: SDRAMs D[43:36]
BPCK1A → CK: SDRAMs D[71:62]
BPCK1B → CK: SDRAMs D[61:54]
Err_Out
RST
RST: SDRAMs D[35:0]
* S[3:2], CK1 and CK1 are NC
CK1
CK1
120Ω
± 5%
Rev. 0.4 / Jul. 2009
26
4. Environmental Parameter
Environmental Parameters
Symbol
Parameter
Rating
TOPR
Operating temperature
See Note
HOPR
Operating humidity (relative)
10 to 90
TSTG
Storage temperature
HSTG
Storage humidity (without condensation)
PBAR
Barometric Pressure (operating & storage)
Units
Notes
3
%
1
o
C
1
5 to 95
%
1
105 to 69
K Pascal
1, 2
-50 to +100
Note:
1. Stress greater than those listed may cause permanent damage to the device. This is a stress rating only, and device functional
operation at or above the conditions indicated is not implied. Expousure to absolute maximum rating conditions for extended
periods may affect reliablility.
2. Up to 9850 ft.
3. The designer must meet the case temperature specifications for individual module components.
Rev. 0.4 / Jul. 2009
27
5. Pin Capacitance (VDD=1.5V, VDDQ=1.5V)
1GB: HMT112R7AFP8C
Pin
Symbol
Min
Max
Unit
CK0, CK0
CCK
TBD
TBD
pF
CKE, ODT
CI1
TBD
TBD
pF
CS
CI2
TBD
TBD
pF
CI3
TBD
TBD
pF
CIO
TBD
TBD
pF
Symbol
Min
Max
Unit
CK0, CK0
CCK
TBD
TBD
pF
CKE, ODT
CI1
TBD
TBD
pF
CS
CI2
TBD
TBD
pF
Address, RAS, CAS, WE
CI3
TBD
TBD
pF
DQ, DM, DQS, DQS
CIO
TBD
TBD
pF
Symbol
Min
Max
Unit
CK0, CK0
CCK
TBD
TBD
pF
CKE, ODT
CI1
TBD
TBD
pF
CS
CI2
TBD
TBD
pF
Address, RAS, CAS, WE
CI3
TBD
TBD
pF
DQ, DM, DQS, DQS
CIO
TBD
TBD
pF
Symbol
Min
Max
Unit
CK0, CK0
CCK
TBD
TBD
pF
CKE, ODT
CI1
TBD
TBD
pF
CS
CI2
TBD
TBD
pF
Address, RAS, CAS, WE
CI3
TBD
TBD
pF
DQ, DM, DQS, DQS
CIO
TBD
TBD
pF
Address, RAS, CAS, WE
DQ, DM, DQS, DQS
2GB: HMT125R7AFP8C
Pin
2GB: HMT125R7AFP4C
Pin
4GB: HMT151R7AFP4C
Pin
Rev. 0.4 / Jul. 2009
28
4GB: HMT151R7AFP8C
Symbol
Min
Max
Unit
CK0, CK0
CCK
TBD
TBD
pF
CKE, ODT
CI1
TBD
TBD
pF
CS
CI2
TBD
TBD
pF
Address, RAS, CAS, WE
CI3
TBD
TBD
pF
DQ, DM, DQS, DQS
CIO
TBD
TBD
pF
Symbol
Min
Max
Unit
CK0, CK0
CCK
TBD
TBD
pF
CKE, ODT
CI1
TBD
TBD
pF
CS
CI2
TBD
TBD
pF
Address, RAS, CAS, WE
CI3
TBD
TBD
pF
DQ, DM, DQS, DQS
CIO
TBD
TBD
pF
Pin
8GB: HMT31GR7AMP4C
Pin
Note:
1. Pins not under test are tied to GND.
2. These value are guaranteed by design and tested on a sample basis only.
Rev. 0.4 / Jul. 2009
29
6. IDD Specifications (Tcase: 0 to 95oC)
1GB, 128M x 72 R-DIMM: HMT112R7AFP8C
Symbol
IDD0
IDD1
IDD2N
IDD2NT
IDDQ2NT
IDD2P0
IDD2P1
IDD2Q
IDD3N
IDD3P
IDD4R
IDDQ4R
IDD4W
IDD5B
IDD6
IDD6ET
IDD6TC
IDD7
DDR3 800
1484
1664
1259
1304
1502
318
462
1259
1349
498
2024
1304
2204
2474
318
336
336
2654
DDR3 1066
1592
1799
1349
1394
1502
318
480
1349
1439
588
2294
1304
2564
2564
318
336
336
3014
DDR3 1333
1664
1889
1439
1484
1502
318
498
1439
1529
633
2654
1304
2834
2654
318
336
336
3464
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
note
note
2GB, 256M x 72 R-DIMM: HMT125R7AFP8C
Symbol
IDD0
IDD1
IDD2N
IDD2NT
IDDQ2NT
IDD2P0
IDD2P1
IDD2Q
IDD3N
IDD3P
DDR3 800
1979
2159
1754
1844
2240
408
696
1754
1934
798
DDR3 1066
2177
2384
1934
2024
2240
408
732
1934
2114
948
DDR3 1333
2399
2564
2114
2204
2240
408
768
2114
2294
1038
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD4R
IDDQ4R
IDD4W
IDD5B
IDD6
IDD6ET
IDD6TC
IDD7
2519
1799
2699
2969
408
444
444
3149
2879
1889
3149
3149
408
444
444
3599
3329
1979
3509
3329
408
444
444
4139
mA
mA
mA
mA
mA
mA
mA
mA
Rev. 0.4 / Jul. 2009
30
2GB, 256M x 72 R-DIMM: HMT125R7AFP4C
Symbol
IDD0
IDD1
IDD2N
IDD2NT
IDDQ2NT
IDD2P0
IDD2P1
IDD2Q
IDD3N
IDD3P
IDD4R
IDDQ4R
IDD4W
IDD5B
IDD6
IDDET
IDD6TC
IDD7
DDR3 800
2204
2564
1754
1844
2240
408
696
1754
1934
768
3284
1844
3644
4184
408
444
444
4544
DDR3 1066
2420
2834
1934
2024
2240
408
732
1934
2114
948
3824
1844
4364
4364
408
444
444
5264
DDR3 1333
2564
3014
2114
2204
2240
408
768
2114
2294
1038
4544
1844
4904
4544
408
444
444
6164
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
note
DDR3 1066
3590
4004
3104
3284
3716
588
1236
3104
3464
1668
4994
3014
5534
5534
588
660
660
6434
DDR3 1333
3914
4364
3464
3644
3716
588
1308
3464
3824
1848
5894
3194
6254
5894
588
660
660
7514
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
note
4GB, 512M x 72 R-DIMM: HMT151R7AFP4C
Symbol
IDD0
IDD1
IDD2N
IDD2NT
IDDQ2NT
IDD2P0
IDD2P1
IDD2Q
IDD3N
IDD3P
IDD4R
IDDQ4R
IDD4W
IDD5B
IDD6
IDDET
IDD6TC
IDD7
Rev. 0.4 / Jul. 2009
DDR3 800
3194
3554
2744
2924
3716
588
1164
2744
3104
1308
4274
2834
4634
5174
588
660
660
5534
31
4GB, 512M x 72 R-DIMM: HMT151R7AFP8C
Symbol
IDD0
IDD1
IDD2N
IDD2NT
IDDQ2NT
IDD2P0
IDD2P1
IDD2Q
IDD3N
IDD3P
IDD4R
IDDQ4R
IDD4W
IDD5B
IDD6
IDDET
IDD6TC
IDD7
DDR3 800
2969
3149
2744
2924
3716
588
1164
2744
3104
1308
3509
2789
3689
3959
588
660
660
4139
DDR3 1066
3347
3554
3104
3284
3716
588
1236
3104
3464
1668
4049
3059
4319
4319
588
660
660
4769
DDR3 1333
3689
3914
3464
3644
3716
588
1308
3464
3824
1848
4679
3329
4859
4679
588
660
660
5489
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
note
DDR3 1066
5930
6344
5444
5804
6668
948
2244
5444
6164
3108
7334
5354
7874
7874
948
1092
1092
8774
DDR3 1333
6614
7064
6164
6524
6668
948
2388
6164
6884
3468
8594
5894
8954
8594
948
1092
1092
10214
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
note
8GB, 1G x 72 R-DIMM: HMT31GR7AMP4C
Symbol
IDD0
IDD1
IDD2N
IDD2NT
IDDQ2NT
IDD2P0
IDD2P1
IDD2Q
IDD3N
IDD3P
IDD4R
IDDQ4R
IDD4W
IDD5B
IDD6
IDDET
IDD6TC
IDD7
Rev. 0.4 / Jul. 2009
DDR3 800
5174
5534
4724
5084
6668
948
2100
4724
5444
2388
6254
4814
6614
7154
948
1092
1092
7514
32
7.1 128Mx72 - HMT112R7AFP8C
Front
133.35
128.95
Detail A
Detail B
1
Detail C
120
1
2X3.00 ± 0.10
47.00
5.175
30.00
Registering
Clock Driver
4X3.00 ± 0.10
9.50
17.30
SPD/TS
2.10 ± 0.15
71.00
5.0
Back
121
240
1
Side
3.43mm max
0.80 ± 0.05
2.50 ± 0.20
3.80
2.50
2.50 ± 0.20
0.20
3 ± 0.1
Detail of Contacts C
Detail of Contacts B
1.20 ± 0.15
0.3 ± 0.15
Detail of Contacts A
0.3~0.1
1.00
1.50 ± 0.10
5.00
1.27 ± 010mm
max
Rev. 0.4 / Jul. 2009
33
7.2 256Mx72 - HMT125R7AFP8C
Front
133.35
128.95
Detail A
Detail C
Detail B
1
120
1
2X3.00 ± 0.10
47.00
5.175
30.00
Registering
Clock Driver
4X3.00 ± 0.10
9.50
17.30
SPD/TS
2.10 ± 0.15
71.00
5.0
Back
121
240
1
Side
3.43mm max
0.80 ± 0.05
2.50 ± 0.20
3.80
2.50
2.50 ± 0.20
0.20
3 ± 0.1
Detail of Contacts C
Detail of Contacts B
1.20 ± 0.15
0.3 ± 0.15
Detail of Contacts A
0.3+0.1
1.00
1.50 ± 0.10
5.00
1.27 ± 010mm
max
6.3 256Mx72 - HMT125R7AFP4C
Rev. 0.4 / Jul. 2009
34
7.3 256Mx72 - HMT125R7AFP4C
Front
133.35
128.95
Detail A
Detail C
Detail B
1
120
1
2X3.00 ± 0.10
47.00
5.175
30.00
Registering
Clock Driver
4X3.00 ± 0.10
9.50
17.30
SPD/TS
2.10 ± 0.15
71.00
5.0
Back
121
240
1
Side
3.43mm max
0.80 ± 0.05
2.50 ± 0.20
3.80
2.50
2.50 ± 0.20
0.20
3 ± 0.1
Detail of Contacts C
Detail of Contacts B
1.20 ± 0.15
0.3 ± 0.15
Detail of Contacts A
0.3~0.1
1.00
1.50 ± 0.10
5.00
1.27 ± 010mm
max
Rev. 0.4 / Jul. 2009
35
7.4 512Mx72 - HMT151R7AFP4C
Front
133.35
Detail B
128.95
Detail A
1
2X3.00 ± 0.10
120
1
47.00
Detail C
5.175
9.50
17.30
Registering
Clock Driver
4X3.00 ± 0.10
30.00
SPD/TS
2.10 ± 0.15
71.00
5.0 Detail D
Back
121
240
1
Side
Detail of Contacts C
0.80 ± 0.05
2.50
14.90
2.50 ± 0.20
0.20
3 ± 0.1
3.80
0.4
13.60
2.50 ± 0.20
Detail of Contacts B
1.20 ± 0.15
3.46mm max
Detail of Contacts D
0.3 ± 0.15
Detail of Contacts A
0.3~0.1
1.00
1.50 ± 0.10
5.00
1.27 ± 010mm
max
Rev. 0.4 / Jul. 2009
36
7.4 512Mx72 - HMT151R7AFP4C - Heat Spreader
Front
133.75
133.35
127
42.7
2.786
8
36.7
22.00
30.00
6.3
2.15
7.74
14.214
Registering
Clock Driver
3.69
5.39
10
20.9
6.35
120
1
7.36
33.4
33.4
46.46
80.54
119.64
Back
57.2
15.36
Registering
Clock Driver
121
22.00
2.7
240
Side
7.19mm max
1.27 ± 010mm
max
Rev. 0.4 / Jul. 2009
37
7.5 512Mx72 - HMT151R7AFP8C
Front
Detail B
14.90
2.10 ± 0.15
13.60
SPD/TS
3 ± 0.1
Min 1.45
9.50
17.30
23.30
30.00
Registering
Clock Driver
3 ± 0.1
Detail A
1
2X3.0 ± 0.10
120
1
47.00
5.175
5.0
Detail C
71.00
Detail D
128.95
133.35
Back
121
240
1
Side
3.46mm max
Detail of Contacts D
Detail of Contacts C
1.20 ± 0.15
0.80 ± 0.05
2.50
14.90
0.20
2.50 ± 0.20
13.60
3 ± 0.1
3.80
0.4
2.50 ± 0.20
Detail of Contacts B
0.3 ± 0.15
Detail of Contacts A
0.3~0.1
1.00
1.50 ± 0.10
5.00
1.27 ± 010mm
max
Rev. 0.4 / Jul. 2009
38
7.5 512Mx72 - HMT151R7AFP8C - Heat Spreader
Front
133.75
133.35
127
42.7
2.786
8
36.7
22.00
30.00
6.3
2.15
7.74
14.214
Registering
Clock Driver
3.69
5.39
10
20.9
6.35
120
1
7.36
33.4
33.4
46.46
80.54
119.64
Back
57.2
15.36
Registering
Clock Driver
121
22.00
2.7
240
Side
7.19mm max
1.27 ± 010mm
max
Rev. 0.4 / Jul. 2009
39
7.6
1Gx72 - HMT31GR7AMP4C
Front
133.35
128.95
Detail B
SPD/TS
120
1
47.00
Detail C
5.175
30.00
DDP
1
2X3.00 ± 0.10
9.50
17.30
DDP
DDP
DDP
DDP
DDP
DDP
DDP
DDP
DDP
DDP
4X3.00 ± 0.10
Detail A
DDP
Registering
Clock Driver
DDP
DDP
DDP
DDP
DDP
DDP
2.10 ± 0.15
71.00
5.0 Detail D
DDP
DDP
DDP
DDP
DDP
DDP
DDP
DDP
DDP
DDP
Registering
Clock Driver
DDP
DDP
DDP
DDP
DDP
DDP
DDP
Back
DDP
121
240
1
Side
Detail of Contacts C
0.80 ± 0.05
2.50
14.90
0.20
2.50 ± 0.20
13.60
3 ± 0.1
3.80
0.4
2.50 ± 0.20
Detail of Contacts B
1.20 ± 0.15
0.3 ± 0.15
Detail of Contacts A
3.69mm max
Detail of Contacts D
0.3~0.1
1.00
1.50 ± 0.10
5.00
1.27 ± 010mm
max
Rev. 0.4 / Jul. 2009
40
7.6
1Gx72 - HMT31GR7AMP4C - Heat Spreader
Front
133.75
133.35
127
42.7
7.74
6.8
22.00
36.7
10.1
14.214
10
2.15
Registering
Clock Driver
1.1
12.02
8.2
17.2
4.06
5.16
6.1
2.786
20.9
6.35
120
1
7.36
33.4
33.4
46.46
80.54
119.64
Back
57.2
15.36
Registering
Clock Driver
121
22.00
2.7
240
Side
7.35mm max
1.27 ± 010mm
max
Rev. 0.4 / Jul. 2009
41
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