Intersil HS1-303ARH-8 Radiation hardened cmos dual spdt analog switch Datasheet

HS-303ARH, HS-303BRH
®
Data Sheet
July 7, 2008
Radiation Hardened
CMOS Dual SPDT Analog Switch
FN6411.1
Features
• QML, Per MIL-PRF-38535
The HS-303ARH and HS-303BRH analog switches are
monolithic devices fabricated using Intersil’s dielectrically
isolated Radiation Hardened Silicon Gate (RSG) process
technology to insure latch-up free operation. They are pinout
compatible and functionally equivalent to the HS-303RH, but
offer improved 300kRAD(Si) total dose capability. These
switches offers low-resistance switching performance for
analog voltages up to the supply rails. “ON” resistance is low
and stays reasonably constant over the full range of
operating voltage and current. “ON” resistance also stays
reasonably constant when exposed to radiation.
Break-before-make switching is controlled by 5V digital
inputs. The HS-303ARH should be operated with nominal
±15V supplies, while the HS-303BRH should be operated
with nominal ±12V supplies.
Specifications
Specifications for Rad Hard QML devices are controlled by
the Defense Supply Center in Columbus (DSCC). The SMD
numbers listed below must be used when ordering.
• Radiation Performance
- Total Dose: 3x105 RAD(Si)
- SEE: For LET = 60MeV-mg/cm2 at 60° Incident Angle,
<150pC Charge Transferred to the Output of an Off
Switch
• No Latch-Up, Dielectrically Isolated Device Islands
• Pinout and Functionally Compatible with Intersil
HS-303RH and HI-303 Series Analog Switches
• Analog Signal Range Equal to the Supply Voltage Range
• Low Leakage . . . . . . . . . . . . . . . . 100nA (Max, Post-Rad)
• Low rON . . . . . . . . . . . . . . . . . . . . . . 70Ω (Max, Post-Rad)
• Low Standby Supply Current . . . . . . . . . . +150µA/-100µA
(Max, Post-Rad)
Pinouts
HS1-303ARH, HS-303BRH (SBDIP), CDIP2-T14
TOP VIEW
Detailed Electrical Specifications for the HS-303ARH and
HS-303BRH are contained in SMD 5962-95813. A “hot-link”
is provided from our website for downloading
NC
1
14 V+
S3
2
13 S4
D3
3
12 D4
D1
4
11 D2
S1
5
10 S2
IN1
6
9 IN2
GND
7
8 V-
HS9-303ARH, HS-303BRH (FLATPACK) CDFP3-F14
TOP VIEW
NC
S3
D3
D1
S1
IN1
GND
1
1
14
2
13
3
12
4
11
5
10
6
9
7
8
V+
S4
D4
D2
S2
IN2
V-
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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All other trademarks mentioned are the property of their respective owners.
HS-303ARH, HS-303BRH
Ordering Information
ORDERING NUMBER
PART NUMBER
TEMP. RANGE
(°C)
PKG.
PKG.
DWG. #
5962F9581304QCC
HS1-303ARH-8
-55 to +125
14 LD SBDIP
D14.3
5962F9581304QXC
HS9-303ARH-8
-55 to +125
14 LD Flatpack
K14.A
5962F9581304V9A
HS0-303ARH-Q
-55 to +125
14 Ld SBDIP
D14.3
5962F9581304VCC
HS1-303ARH-Q
-55 to +125
14 LD SBDIP
D14.3
5962F9581304VXC
HS9-303ARH-Q
-55 to +125
14 LD Flatpack
K14.A
HS0-303ARH/SAMPLE
HS0-303ARH/SAMPLE
-55 to +125
HS1-303ARH/PROTO
HS1-303ARH/PROTO
-55 to +125
14 LD SBDIP
D14.3
HS9-303ARH/PROTO
HS9-303ARH/PROTO
-55 to +125
14 LD Flatpack
K14.A
5962F9581305QCC
HS1-303BRH-8
-55 to +125
14 LD SBDIP
D14.3
5962F9581305QXC
HS9-303BRH-8
-55 to +125
14 LD Flatpack
K14.A
5962F9581305V9A
HS0-303BRH-Q
-55 to +125
14 LD SBDIP
D14.3
5962F9581305VCC
HS1-303BRH-Q
-55 to +125
14 LD SBDIP
D14.3
5962F9581305VXC
HS9-303BRH-Q
-55 to +125
14 LD Flatpack
K14.A
HS0-303BRH/SAMPLE
HS0-303BRH/SAMPLE
-55 to +125
HS1-303BRH/PROTO
HS1-303BRH/PROTO
-55 to +125
14 LD SBDIP
D14.3
HS9-303BRH/PROTO
HS9-303BRH/PROTO
-55 to +125
14 LD Flatpack
K14.A
2
FN6411.1
July 7, 2008
HS-303ARH, HS-303BRH
Functional Diagram
TRUTH TABLE
N
IN
P
LOGIC
SW1 AND SW2
SW3 AND SW4
0
OFF
ON
1
ON
OFF
D
Die Characteristics
DIE DIMENSIONS:
Backside Finish:
2690µm x 5200µm (106 milsx205 mils)
Thickness: 483µm ± 25.4µm (19 mils ± 1 mil)
INTERFACE MATERIALS:
Silicon
ASSEMBLY RELATED INFORMATION:
Substrate Potential:
Glassivation:
Unbiased (DI)
Type: PSG (Phosphorous Silicon Glass)
Thickness: 8.0kÅ ± 1.0kÅ
ADDITIONAL INFORMATION:
Worst Case Current Density:
Top Metallization:
<2.0 x 105 A/cm2
Type: AlSiCu
Thickness: 16.0kÅ ± 2kÅ
Transistor Count:
196
Substrate:
Radiation Hardened Silicon Gate,
Dielectric Isolation
Metallization Mask Layout
IN2
S2
D2
D4
S4
HS-303ARH, HS-303BRH
VV+
IN1
S1
D1
D3
S3
GND
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notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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3
FN6411.1
July 7, 2008
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