HS-6664RH TM Data Sheet August 2000 File Number Radiation Hardened 8kx8 CMOS PROM Features The Intersil HS-6664RH is a radiation hardened 64k CMOS • Electrically Screened to SMD # 5962-95626 [ /Title PROM, organized in an 8k word by 8-bit format. The chip is manufactured using a radiation hardened CMOS process, (HS6664R and utilizes synchronous circuit design techniques to achieve high speed performance with very low power H) dissipation. /Subjec On-chip address latches are provided, allowing easy t (Radiat interfacing with microprocessors that use a multiplexed address/data bus structure. The output enable control (G) ion simplifies system interfacing by allowing output data bus Harden control in addition to the chip enable control (E). All bits are ed 8K manufactured storing a logical “0” and can be selectively programmed for a logical “1” at any bit location. x8 CMOS Applications for the HS-6664RH CMOS PROM include low PROM power microprocessor based instrumentation and communications systems, remote data acquisition and ) /Autho processing systems, and processor control storage. r () Specifications for Rad Hard QML devices are controlled /Keyw by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed here must be used when ordering. ords (Intersi Detailed Electrical Specifications for these devices are contained in SMD 5962-95626. A “hot-link” is provided l Corpor on our homepage for downloading. www.intersil.com/spacedefense/space.htm ation, semico Ordering Information nducto INTERNAL TEMP. RANGE r, ORDERING NUMBER MKT. NUMBER (oC) Radiati 5962F9562601QXC HS1-6664RH-8 -55 to 125 on HS9-6664RH-8 -55 to 125 Harden 5962F9562601QYC 5962F9562601VXC HS1-6664RH-Q -55 to 125 ed, RH, 5962F9562601VYC HS9-6664RH-Q -55 to 125 Rad HS1-6664RH/PROTO HS1-6664RH/PROTO -55 to 125 Hard, HS9-6664RH/PROTO HS9-6664RH/PROTO -55 to 125 QML, Satellit e, SMD, Class V, 1 3197.4 • QML Qualified per MIL-PRF-38535 Requirements • 1.2 Micron Radiation Hardened Bulk CMOS • Total Dose . . . . . . . . . . . . . . . . . . . . . . 300 krad(Si) (Max) • Transient Output Upset . . . . . . . . . . . . . . >5x108 rad(Si)/s • LET >100 MEV-cm2/mg • Fast Access Time. . . . . . . . . . . . . . . . . . . . . . . 35ns (Typ) • Single 5V Power Supply • Single Pulse 10V Field Programmable • Synchronous Operation • On-Chip Address Latches • Three-State Outputs • NiCr Fuses • Low Standby Current . . . . . . . . . . . . . . <500μA (Pre-Rad) • Low Operating Current. . . . . . . . . . . . . . . . . . <15mA/MHz • Military Temperature Range. . . . . . . . . . . -55oC to 125oC CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000 HS-6664RH Pinouts 28 LEAD CERAMIC (SBDIP) CASE OUTLINE D28.6 MIL-STD-1835, CDIP2-T28 TOP VIEW 28 LEAD FLATPACK CASE OUTLINE K28.A MIL-STD-1835, CDFP3-F28 TOP VIEW 28 VDD NC 1 NC 1 28 VDD † A12 2 27 P A7 3 26 NC A7 3 26 NC A6 4 25 A8 A6 4 25 A8 A5 5 24 A9 A5 5 24 A9 A4 23 A11 23 A11 A4 6 6 A3 7 22 G A3 7 22 G A2 8 21 A10 A2 8 21 A10 A1 9 20 E A1 9 20 E A0 10 19 DQ7 DQ0 11 A12 2 27 P A0 10 19 DQ7 DQ0 11 18 DQ6 DQ1 17 DQ5 18 DQ6 12 DQ2 13 16 DQ4 DQ1 12 17 DQ5 GND 14 15 DQ3 DQ2 13 16 DQ4 GND 14 15 DQ3 † P must be hardwired at all times to VDD, except during programming. Functional Diagram MSB A2 A3 A4 A5 A6 A7 A8 LSB A LATCHED ADDRESS REGISTER 8 A 256 GATED ROW DECODER 256x256 MATRIX 1 OF 8 8 E E 32 32 †P E E 32 32 32 32 32 32 GATED COLUMN DECODER PROGRAMMING, AND DATA OUTPUT CONTROL 8 A A 5 8 5 G E LATCHED ADDRESS REGISTER MSB LSB A0 NOTE: † A1 A10 A9 † P must be hardwired at all times to VDD, except during programming. TRUTH TABLE 2 E G MODE 0 0 Enabled 0 1 Output Disabled 1 X Disabled A11 A12 Q0 - Q7 HS-6664RH Burn-In Circuits HS1-6664RH 28 LEAD (8kx8 PROM DIP) HS9-6664RH 28 LEAD (8kx8 PROM FLATPACK) HS1-6664RH 28 LEAD (8kx8 PROM DIP) HS9-6664RH 28 LEAD (8kx8 PROM FLATPACK) VDD NC NC A12 A7 A6 A5 A4 A3 A2 A1 A0 NC NC NC DQ0 DQ1 DQ2 VSS 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 VDD VDD NC P NC A8 A12 F13 NC NC A7 F8 A6 F7 A9 A5 F6 A11 A4 F5 G A3 F4 A10 E1 DQ7 DQ6 DQ5 DQ4 DQ3 A2 F3 A1 F2 NC A0 F1 NC LOAD NC LOAD NC LOAD NC DQ0 DQ1 DQ2 VSS 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 20 9 10 19 11 18 12 17 13 16 14 15 OUT STATIC CONFIGURATION P NC A8 NC F9 A9 F10 A11 F12 G F0 A10 F11 E1 F0 DQ7 DQ6 DQ5 DQ4 DQ3 LOAD LOAD LOAD LOAD LOAD LOAD: 10kΩ VSS = GND VSS = GND VDD VDD/2 DYNAMIC CONFIGURATION NOTES: NOTES: 1. Power Supply: VDD = 5.5V (Min) 3. Power Supply: VDD = 5.5V (Min) 2. Resistors = 10kΩ ± 10% 4. VIH = VDD to VDD-1.0V 5. VIL = 0.0V to 0.8V 6. Resistors = 10kΩ ± 10% 7. F0 = 100kHz ± 10%, 50% Duty Cycle 8. F1 = F0/2; F2 = F1/2; F3 = F2/2; F4 = F3/2; F5 = F4/2; . . . F13 = F12/2 Irradiation Circuit HS1-6664RH 28 LEAD (8kx8 PROM DIP) VDD NC NC 1 A12 2 A7 3 A6 4 A5 5 A4 6 A3 7 A2 8 A1 9 A0 10 DQ0 11 DQ1 12 DQ2 13 VSS 14 VDD = GND NOTES: 9. Power Supply: VDD = 5.5V ± ±0.5V 10. All Resistors = 47kΩ ± 10% 3 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD P NC A8 NC A9 A11 G A10 E1 DQ7 DQ6 DQ5 DQ4 DQ3 HS-6664RH Die Characteristics DIE DIMENSIONS: ASSEMBLY RELATED INFORMATION: 271milsx307milsx19mils ±1mils Substrate Potential: INTERFACE MATERIALS: VDD Glassivation: ADDITIONAL INFORMATION: Type: SiO2 Thickness: 8kÅ ± 1kÅ Worst Case Current Density: 2x105 A/cm2 Top Metallization: Transistor Count: M1:6kÅ ±±1kÅ Si/Al/Cu 2kÅ ±±500Å TiW M2:10kÅ ± 2kÅSi/Al/Cu 110, 874 Metallization Mask Layout 4 VDD VSS (23) A11 (24) A9 (22) G A10 (21) E (20) DQ7 (19) (26) NC (27) P (28) VDD (25) A8 DQ6 (18) DQ5 (17) DQ4 (16) DQ3 (15) GND (14) (3) A7 (4) A6 (2) A12 DQ2 (13) DQ1 (12) (5) A5 DQ0 (11) (6) A4 A0 (10) A1 (9) A2 (8) VDD VSS (7) A3 HS-6664RH HS-6664RH All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. 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