Intersil HS9-82C37ARH-Q Radiation hardened cmos high performance programmable dma controller Datasheet

HS-82C37ARH
Radiation Hardened CMOS High
Performance Programmable DMA Controller
August 1995
Features
Description
• Radiation Hardened
- Total Dose >105 RAD (Si)
- Transient Upset > 108 RAD (Si)/s
- Latch Up Free EPI-CMOS
The Intersil HS-82C37ARH is an enhanced, radiation
hardened CMOS version of the industry standard 8237A
Direct Memory Access (DMA) controller, fabricated using the
Intersil hardened field, self-aligned silicon gate CMOS
process. The HS-82C37ARH offers increased functionality,
improved performance, and dramatically reduced power
consumption for the radiation environment. The high speed,
radiation hardness, and industry standard configuration of
the HS-82C37ARH make it compatible with radiation
hardened microprocessors such as the HS-80C85RH and
the HS-80C86RH.
• Low Power Consumption
- IDDSB = 50µA Maximum
- IDDOP = 4.0mA/MHz Maximum
• Pin Compatible with NMOS 8237A and the Intersil
82C37A
• High Speed Data Transfers Up To 2.5 MBPS With 5MHz
Clock
• Four Independent Maskable Channels With Autoinitialization Capability
• Expandable to Any Number of Channels
• Memory-to-Memory Transfer Capability
• CMOS Compatible
• Hardened Field, Self-Aligned, Junction Isolated CMOS
Process
• Single 5V Supply
• Military Temperature Range -55oC to +125oC
The HS-82C37ARH can improve system performance by
allowing external devices to transfer data directly to or from
system memory. Memory-to-memory transfer capability is
also provided, along with a memory block initialization
feature. DMA requests may be generated by either
hardware or software, and each channel is independently
programmable with a variety of features for flexible
operation.
Static CMOS circuit design insures low operating power and
allows gated clock operation for an even further reduction of
power. Multimode programmability allows the user to select
from three basic types of DMA services, and reconfiguration
under program control is possible even with the clock to the
controller stopped. Each channel has a full 64K address and
word count range, and may be programmed to autoinitialize
these registers following DMA termination (end of process).
The Intersil hardened field CMOS process results in
performance equal to or greater than existing radiation resistant products at a fraction of the power.
Ordering Information
PART NUMBER
TEMPERATURE RANGE
PACKAGE
HS1-82C37ARH-Q
-55oC to +125oC
40 Lead SBDIP
HS1-82C37ARH-8
-55oC
40 Lead SBDIP
HS1-82C37ARH-Sample
to
+125oC
+25oC
40 Lead SBDIP
HS9-82C37ARH-Q
-55oC to +125oC
42 Lead Ceramic Flatpack
HS9-82C37ARH-8
-55oC to +125oC
42 Lead Ceramic Flatpack
+25oC
42 Lead Ceramic Flatpack
DB NA
HS9-82C37ARH/Sample
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
918
Spec Number
File Number
518058
3042.1
HS-82C37ARH
Pinouts
40 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE
(SBDIP) MIL-STD-1835 CDIP2-T40
TOP VIEW
IOR
1
40
A7
IOW
2
39
A6
MEMR
3
38
A5
MEMW
4
37
A4
NC
5
36
EOP
READY
6
35
A3
HLDA
7
34
A2
ADSTB
8
33
A1
AEN
9
32
A0
HRQ
10
31
VDD
CS
11
30
DB0
CLK
12
29
DB1
RESET 13
28
DB2
DACK2 14
27
DB3
42 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
(FLATPACK) INTERSIL OUTLINE K42.A
TOP VIEW
IOR
IOW
MEMR
MEMW
1
2
3
4
42
41
40
39
NC
READY
5
6
38
37
HLDA
ADSTB
7
8
36
35
AEN
9
34
A1
A0
HRQ
CS
10
11
33
32
VDD
DB0
CLK
RESET
DACK2
DACK3
12
13
14
15
31
30
29
28
DB1
DB2
DB3
NC
16
27
17
18
19
20
26
25
24
23
NC
DACK0
21
22
DACK3 15
26
DB4
DREQ3 16
25
DACK0
DREQ2 17
24
DACK1
DREQ1 18
23
DB5
DREQ3
DREQ2
DREQ1
DREQ0
DREQ0 19
22
DB6
GND
20
21
DB7
(GND)
VSS
A7
A6
A5
A4
EOP
A3
A2
DB4
DACK1
DB5
DB6
DB7
Functional Diagram
DECREMENTOR
EOP
TEMP WORD
COUNT REG (16)
RESET
CS
A0-A3
INC DECREMENTOR
I/O BUFFER
TEMP ADDRESS
REG (16)
16 BIT BUS
16 BIT BUS
READY
TIMING
AND
CONTROL
ADSTB
MEMR
READ BUFFER
BASE
WORD
COUNT
(16)
BASE
ADDRESS
(16)
BASE
ADDRESS
(16)
BASE
WORD
COUNT
(16)
MEMW
A8-A15
CLOCK
AEN
A4-A7
OUTPUT
BUFFER
COMMAND
CONTROL
IOR
IOW
WRITE
BUFFER
DREQ0DREQ3
HLDA
HDQ
DACK0DACK3
READ
BUFFER
D0-D1
DB0-DB7
4
4
PRIORITY
ENCODER
AND
ROTATING
PRIORITY
LOGIC
COMMAND (8)
I/O BUFFER
INTERNAL DATA BUS
MASK (4)
REQUEST (4)
MODE
(4 x 6)
STATUS (8)
TEMPORARY
(8)
Spec Number
919
518058
HS-82C37ARH
Pin Descriptions
SYMBOL
PIN
NUMBER
VDD
31
VDD: is the +5V power supply pin. A 0.1µF capacitor between pins 31 and 20 is recommended for decoupling.
GND
20
Ground
CLK
12
I
CLOCK INPUT: The Clock Input is used to generate the timing signals which control HS-82C37ARH
operations. This input may be driven from DC to 5MHz and may be stopped in either high or low state
for standby operation.
CS
11
I
CHIP SELECT: Chip Select is an active low input used to enable the controller onto the data bus for
CPU communications.
RESET
13
I
RESET: This is an active high input which clears the Command, Status, Request and Temporary Registers, the First/Last Flip-Flop, and the Mode Register Counter. The Mask Register is Set to ignore requests. Following a Reset, the controller is in an idle cycle.
READY
6
I
READY: This signal can be sued to extend the memory read and write pulses from the HS-82C37ARH
to accommodate slow memories or I/O devices. Ready must not make transitions during its specified
set-up and hold times. Ready is ignored in Verify Transfer mode.
HLDA
7
I
HOLD ACKNOWLEDGE: The active high Hold Acknowledge from the CPU indicates that is has relinquished control of the system busses.
DREQ0DREQ3
16-19
I
DMA REQUEST: The DMA Request (DREQ) lines are individual asynchronous channel request inputs
used by peripheral circuits to obtain DMA service. In Fixed Priority, DREQ0 has the highest priority and
DREQ3 has the lowest priority. A request is generated by activating the DREQ line of a channel. DACK
will acknowledge the recognition of DREQ signal. Polarity of DREQ is programmable. Reset initializes
these lines to active. DREQ will not be recognized while the clock is stopped. Unused DREQ inputs
should be pulled High or Low (inactive) and the corresponding mask bit set.
DB0DB7
21-23
26-30
I/O
DATA BUS: The Data Bus lines are bidirectional three-state signals connected to the system data bus.
The outputs are enabled in the Program Condition during the I/O Read to output the contents of a register to the CPU. The outputs are disabled and the inputs are read during an I/O Write cycle when the
CPU is programming the HS-82C37ARH Control Registers. During DMA cycles, the most significant 8
bits of the address are output onto the data bus to be strobed into an external latch by ADSTB. In Memory-to-Memory operations, data from the memory enters the HS-82C37ARH on the data bus during the
read-from-memory transfer, then during the write-to-memory transfer, the data bus outputs write the
data into the new memory location.
IOR
1
I/O
I/O READ: I/O Read is a bidirectional active low three-state line. In the Idle cycle, it is an input control
signal used by the CPU to read the internal registers. In the Active cycle, it is an output control signal
used by the HS-82C37ARH to access data from a peripheral during a DMA Write transfer.
IOW
2
I/O
I/O WRITE: I/O Write is a bidirectional active low three-state line. In the Idle cycle, it is an input control
signal used by the CPU to load information into the HS-82C37ARH. In the Active cycle, it is an output
control signal used by the HS-82C37ARH to load data to the peripheral during a DMA Read transfer.
EOP
36
I/O
END OF PROCESS: End of Process (EOP) is an active low bidirectional signal. Information concerning
the completion of DMA services is available at the bidirectional EOP pin.
The HS-82C37ARH allows an external signal to terminate an active DMA service by pulling the EOP
pin low. A pulse is generated by the HS-82C37ARH when terminal count (TC) for any channel is
reached, except for channel 0 in Memory-to-Memory mode. During Memory-to-Memory transfers, EOP
will be output when the TC for channel 1 occurs.
The EOP pin is driven by an open drain transistor on-chip, and requires an external pull-up resistor.
When an EOP pulse occurs, whether internally or externally generated, the HS-82C37ARH will terminate the service, and if Autoinitialize is enabled, the base registers will be written to the current registers
of that channel. The mask bit and TC bit in the Status Register will be set for the currently active channel
by EOP unless the channel is programmed for Autoinitialize. In that case, the mask bit remains clear.
A0-A3
32-35
I/O
Address: The four least significant address lines are bidirectional three-state signals. In the Idle cycle,
they are inputs and are used by the HS-80C86RH to address the internal registers to be loaded or read.
In the Active cycle, they are outputs and provide the lower 4 bits of the output address.
TYPE
DESCRIPTION
Spec Number
920
518058
HS-82C37ARH
Pin Descriptions
(Continued)
SYMBOL
PIN
NUMBER
TYPE
DESCRIPTION
A4-A7
37-40
O
Address: The four most significant address lines are three-state outputs and provide 4 bits of address.
These lines are enabled only during the Active cycle.
HRQ
10
O
Hold Request: The Hold Request (HRQ) output is used to request control of the system bus. When a
DREQ occurs and the corresponding mask bit is clear, or a software DMA request is made, the HS82C37ARH issues HRQ. The HLDA signal then informs the controller when access to the system busses is permitted. For stand-alone operation where the HS-82C37ARH always controls the busses, HRQ
may be tied to HLDA. This will result in one S0 state before the transfer.
DACK0DACK3
14,15, 24,
25
O
DMA Acknowledge: DMA acknowledge is used to notify the individual peripherals when one has been
granted a DMA cycle. The sense of these lines is programmable. Reset initializes them to active low.
AEN
9
O
Address Enable: Address Enable enables the 8-bit latch containing the upper 8 address bits onto the
system address bus. AEN can also be used to disable other system bus drivers during DMA transfers.
AEN is active HIGH.
ADSTB
8
O
Address Strobe: This is an active high signal used to control latching of the upper address byte. It will
drive directly the strobe input of external transparent octal latches, such as the 82C82. During block operations, ADSTB will only be issued when the upper address byte must be updated, thus speeding operation through elimination of S1 states. (See Note 2).
MEMR
3
O
Memory Read: The Memory Read signal is an active low three-state output used to access data from
the selected memory location during a DMA Read or a Memory-to-Memory transfer.
MEMW
4
O
Memory Write: The Memory Write is an active low three-state output used to write data to the selected
memory location during a DMA Write or a Memory-to-Memory transfer.
NC
5
No connect. Pin 5 is open and should not be tested for continuity.
Spec Number
921
518058
Specifications HS-82C37ARH
Absolute Maximum Ratings
Reliability Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.5V
Input or Output Voltage Applied . . . . . . . .VSS - 0.3V to VDD + 0.3V
for All Grades
Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC
Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300oC
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
Typical Derating Factor. . . . . . . . . . . . 4mA/MHz Increase in IDDOP
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Resistance
θJA
θJC
SBDIP Package. . . . . . . . . . . . . . . . . . . .
38oC/W
5oC/W
Ceramic Flatpack Package . . . . . . . . . . .
72oC/W
10oC/W
Maximum Package Power Dissipation at +125oC Ambient
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.32W
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.69W
If device power exceeds package dissipation capability, provide heat
sinking or derate linearly at the following rate:
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26.3mW/C
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . .13.9mW/C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Supply Voltage Range (VDD) . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range (TA) . . . . . . . . . . . . -55oC to +125oC
Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to +0.8V
Input High Voltage. . . . . . . . . . . . . . . . . . . . . . . . VDD -1.5V to VDD
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
SYMBOL
GROUP A
SUBGROUP
CONDITIONS
TEMPERATURE
MIN
MAX
UNITS
TTL Output High Voltage
VOH1
VDD = 4.5V, IO = -2.5mA,
VIN = 0V or 4.0V
1, 2, 3
+25oC, +125oC,
-55oC
3.0
-
V
CMOS Output High Voltage
VOH2
VDD = 4.5V, IO = -100µA,
VIN = 0V or 4.0V
1, 2, 3
+25oC, +125oC,
-55oC
VDD0.4
-
V
Output Low Voltage
VOL1
VDD = 4.5V, IO = +2.5mA,
VIN = 0V or 4.0V
1, 2, 3
+25oC, +125oC,
-55oC
-
0.4
V
Input Leakage Current
IIL or IIH
VDD = 5.5V, VIN = 0V or
5.5V Pins: 6, 7, 11-13, 16-19
1, 2, 3
+25oC, +125oC,
-55oC
-1.0
1.0
µA
Output Leakage Current
IOZL or
IOZH
VDD = 5.5V, VIN = 0V or
5.5V Pins: 1-4, 21-23, 2630, 32-40
1, 2, 3
+25oC, +125oC,
-55oC
-10
10
µA
Standby Power Supply
Current
IDDSB
VDD = 5.5V, IO = 0mA,
VIN = GND or VDD
1, 2, 3
+25oC, +125oC,
-55oC
-
+50
µA
Operating Power Supply
Current
IDDOP
VDD = 5.5V, IO = 0mA,
VIN = GND or VDD,
f = 5MHz
1, 2, 3
+25oC, +125oC,
-55oC
-
20
mA
Functional Tests
FT
VDD = 4.5V and 5.5V,
VIN = GND or VDD,
f = 1MHz
7, 8A, 8B
+25oC, +125oC,
-55oC
-
-
-
Noise Immunity Functional
Test
FN
VDD = 4.5V and 5.5V, VIN =
GND or VDD - 1.5V and
VDD = 4.5V, VIN = 0.8V or
VDD
7, 8A, 8B
+25oC, +125oC,
-55oC
-
-
-
Spec Number
922
518058
Specifications HS-82C37ARH
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
VCC = +5V ±10%, GND = 0V, AC’s Tested at Worst Case VDD, Guaranteed Over Full Operating Range.
LIMITS
PARAMETER
SYMBOL
(NOTES 1, 2)
CONDITIONS
TEMPERATURE
SUBGROUP
VDD = 4.5V
+25oC, +125oC,
-55oC
9, 10, 11
MIN
MAX
UNITS
175
ns
DMA (MASTER) MODE
AEN HIGH from CLK LOW (S1)
Delay Time
TCLAEH
DMA (MASTER) MODE (Continued)
AEN LOW from CLK HIGH (SI)
Delay Time
TCHAEL
VDD = 4.5V
+25oC, +125oC,
-55oC
9, 10, 11
-
130
ns
ADR from READ HIGH Hold
Time
TRHAX
VDD = 4.5V
+25oC, +125oC,
-55oC
9, 10, 11
TCLCL100
-
ns
DB from ADSTB LOW Hold
Time
TSLDZ
VDD = 4.5V
+25oC, +125oC,
-55oC
9, 10, 11
TCLCH18
-
ns
ADR from WRITE HIGH Hold
Time
TWHAX
VDD = 4.5V
+25oC, +125oC,
-55oC
9, 10, 11
TCLCL50
-
ns
DACK Valid from CLK LOW
Delay Time
TCLDAV
VDD = 4.5V
+25oC, +125oC,
-55oC
9, 10, 11
-
170
ns
EOP HIGH from CLK HIGH
Delay Time
TCHIPH
VDD = 4.5V
+25oC, +125oC,
-55oC
9, 10, 11
-
170
ns
EOP LOW from CLK HIGH
Delay Time
TCHIPL
VDD = 4.5V
+25oC, +125oC,
-55oC
9, 10, 11
-
100
ns
ADR Stable from CLK HIGH
TCHAV
VDD = 4.5V
+25oC, +125oC,
-55oC
9, 10, 11
-
110
ns
DB to ADSTB LOW Setup Time
TDVSL
VDD = 4.5V
+25oC, +125oC,
-55oC
9, 10, 11
TCHCL
+10
-
ns
Clock HIGH Time
(Transitions 10ns)
TCHCL
VDD = 4.5V
+25oC, +125oC,
-55oC
9, 10, 11
70
-
ns
Clock LOW Time
(Transitions 10ns)
TCLCH
VDD = 4.5V
+25oC, +125oC,
-55oC
9, 10, 11
50
-
ns
CLK Cycle Time
TCLCL
VDD = 4.5V
+25oC, +125oC,
-55oC
9, 10, 11
200
-
ns
TCHRWL
VDD = 4.5V
+25oC, +125oC,
-55oC
9, 10, 11
-
190
ns
READ HIGH from CLK HIGH
(S4) Delay Time
TCHRH
VDD = 4.5V
+25oC, +125oC,
-55oC
9, 10, 11
-
190
ns
WRITE HIGH from CLK HIGH
(S4) Delay Time
TCHWH
VDD = 4.5V
+25oC, +125oC,
-55oC
9, 10, 11
-
130
ns
HRQ Valid from CLK HIGH
Delay Time
TCHRQV
VDD = 4.5V
+25oC, +125oC,
-55oC
9, 10, 11
-
120
ns
EOP LOW to CLK LOW Setup
Time
TEPLCL
VDD = 4.5V
+25oC, +125oC,
-55oC
9, 10, 11
40
-
ns
EOP Pulse Width
TEPLEPH
VDD = 4.5V
+25oC, +125oC,
-55oC
9, 10, 11
220
-
ns
READ or WRITE Active from
CLK HIGH
TCHRWV
VDD = 4.5V
+25oC, +125oC,
-55oC
9, 10, 11
-
150
ns
CLK HIGH to READ or WRITE
LOW Delay
Spec Number
923
518058
Specifications HS-82C37ARH
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
VCC = +5V ±10%, GND = 0V, AC’s Tested at Worst Case VDD, Guaranteed Over Full Operating Range.
LIMITS
PARAMETER
SYMBOL
(NOTES 1, 2)
CONDITIONS
TEMPERATURE
SUBGROUP
MIN
MAX
UNITS
DMA (MASTER) MODE (Continued)
TCHDV
VDD = 4.5V
+25oC, +125oC,
-55oC
9, 10, 11
-
110
ns
HLDA Valid to CLK HIGH Setup
Time
TRAVCH
VDD = 4.5V
+25oC, +125oC,
-55oC
9, 10, 11
75
-
ns
Input Data from MEMR HIGH
Hold Time
TMRHDX
VDD = 4.5V
+25oC, +125oC,
-55oC
9, 10, 11
0
ns
Input Data to MEMR HIGH
Setup Time
TDVMRH
VDD = 4.5V
+25oC, +125oC,
-55oC
9, 10, 11
155
ns
Output Data from MEMW HIGH
HOLD Time
TMWHDZ
VDD = 4.5V
+25oC, +125oC,
-55oC
9, 10, 11
15
ns
Output Data Valid to MEMW
HIGH
TDVMWH
VDD = 4.5V
+25oC, +125oC,
-55oC
9, 10, 11
TCLCL35
-
ns
DREQ to CLK LOW (SI, S4)
Setup Time
TDQVCL
VDD = 4.5V
+25oC, +125oC,
-55oC
9, 10, 11
0
-
ns
CLK LOW to READY Hold Time
TCLRYX
VDD = 4.5V
+25oC, +125oC,
-55oC
9, 10, 11
20
-
ns
READY to CLK LOW Setup
Time
TRYVCL
VDD = 4.5V
+25oC, +125oC,
-55oC
9, 10, 11
60
-
ns
ADSTB HIGH from CLK LOW
Delay Time
TCLSH
VDD = 4.5V
+25oC, +125oC,
-55oC
9, 10, 11
-
80
ns
ADSTB LOW from CLK LOW
Delay Time
TCLSL
VDD = 4.5V
+25oC, +125oC,
-55oC
9, 10, 11
-
120
ns
READ HIGH Delay from WRITE
HIGH
TWHRH
VDD = 4.5V
+25oC, +125oC,
-55oC
9, 10, 11
0
-
ns
READ Pulse Width, Normal
Timing
TRLRH1
VDD = 4.5V
+25oC, +125oC,
-55oC
9, 10, 11
2TCLCL
-50
-
ns
TSHSL
VDD = 4.5V
+25oC, +125oC,
-55oC
9, 10, 11
TCLCL 80
-
ns
Extended WRITE Pulse Width
TWLWH1
VDD = 4.5V
+25oC, +125oC,
-55oC
9, 10, 11
2TCLCL
-100
-
ns
WRITE Pulse Width
TWLWH2
VDD = 4.5V
+25oC, +125oC,
-55oC
9, 10, 11
TCLCL 100
-
ns
READ Pulse Width,
Compressed
TRLRH2
VDD = 4.5V
+25oC, +125oC,
-55oC
9, 10, 11
TCLCL 50
-
ns
ADR Valid or CS LOW to IOR
LOW
TAVIRL
VDD = 4.5V
+25oC, +125oC,
-55oC
9, 10, 11
10
-
ns
ADR Valid or CS LOW to IOW
LOW Setup Time 0
TAVIWL
VDD = 4.5V
+25oC, +125oC,
-55oC
9, 10, 11
0
-
ns
Data Valid to IOW HIGH Setup
Time
TDVIWH
VDD = 4.5V
+25oC, +125oC,
-55oC
9, 10, 11
150
-
ns
DB Float to Active Delay from
CLK HIGH
ADSTB Pulse Width
PERIPHERAL (SLAVE) MODE
Spec Number
924
518058
Specifications HS-82C37ARH
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
VCC = +5V ±10%, GND = 0V, AC’s Tested at Worst Case VDD, Guaranteed Over Full Operating Range.
LIMITS
PARAMETER
(NOTES 1, 2)
CONDITIONS
SYMBOL
TEMPERATURE
SUBGROUP
MIN
MAX
UNITS
PERIPHERAL (SLAVE) MODE (Continued)
ADR or CS Hold from IOR HIGH
TIRHAX
VDD = 4.5V
+25oC, +125oC,
-55oC
9, 10, 11
0
-
ns
Data Access from IOR
TIRLDV
VDD = 4.5V
+25oC, +125oC,
-55oC
9, 10, 11
-
150
ns
RESET to First IOW or IOR
TRSLIRWL
VDD = 4.5V
+25oC, +125oC,
-55oC
9, 10, 11
2TCLCL
-
ns
RESET Pulse Width
TRSHRSL
VDD = 4.5V
+25oC, +125oC,
-55oC
9, 10, 11
300
-
IOR Width
TIRLIRH
VDD = 4.5V
+25oC, +125oC,
-55oC
9, 10, 11
200
-
ns
ADR or CS HIGH from IOW
HIGH Hold Time
TIWHAX
VDD = 4.5V
+25oC, +125oC,
-55oC
9, 10, 11
0
-
ns
Data from IOW HIGH Hold Time
TIWHDX
VDD = 4.5V
+25oC, +125oC,
-55oC
9, 10, 11
10
-
ns
IOW Width
TIWLIWH
VDD = 4.5V
+25oC, +125oC,
-55oC
9, 10, 11
150
-
ns
NOTES:
1. READ refers to both IOR and MEMR, and WRITE refers to both IOW and MEMW, during memory to I/O and I/O to memory transfers
2. AC’s Tested at Worst Case VDD But Guaranteed Over Full Operating Range
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Input Capacitance
Output Capacitance
I/O Capacitance
ADR Active to Float Delay from CLK HIGH
READ or WRITE Float Delay from CLK
HIGH
DB Active to Float Delay from CLK HIGH
DB Float Delay from IOR HIGH
Power Supply HIGH to RESET LOW
Setup Time
SYMBOL
CONDITIONS
TEMPERATURE
MIN
MAX
UNITS
+25oC
-
15
pF
CIN
VDD = Open, f = 1MHz,
All measurements referenced to device ground.
TA =
COUT
VDD = Open, f = 1MHz,
All measurements referenced to device ground.
TA = +25oC
-
15
pF
CI/O
VDD = Open, f = 1MHz,
All measurements referenced to device ground.
TA = +25oC
-
20
pF
VDD = 4.5V and 5.5V
-55oC < TA < +125oC
-
90
ns
TCHRWZ
VDD = 4.5V and 5.5V
-55oC
+125oC
-
120
ns
TCHDZ
VDD = 4.5V and 5.5V
-55oC < TA < +125oC
VDD = 4.5V and 5.5V
-55oC
VDD = 4.5V and 5.5V
-55oC
TCHAZ
TIRHDZ
TPHRSL
< TA <
-
170
ns
< TA <
+125oC
10
85
ns
< TA <
+125oC
500
-
ns
NOTE: The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are
characterized upon initial design release and upon design changes which would affect these characteristics.
Spec Number
925
518058
Specifications HS-82C37ARH
TABLE 4. POST 100K RAD ELECTRICAL PERFORMANCE CHARACTERISTICS
NOTE:
See +25oC limits in Table 1 and Table 2 for Post RAD limits (Subgroups 1, 7 and 9).
TABLE 5. BURN-IN DELTA PARAMETERS (+25oC)
PARAMETER
SYMBOL
DELTA LIMITS
IDDSB
± 20µA
IOZL, IOZH
± 2µA
IIH, IIL
± 200nA
VOL
± 80mV
TTL Output High Voltage
VOH1
± 600mV
CMOS Output High Voltage
VOH2
± 150mV
Standby Power Supply Current
Output Leakage Current
Input Leakage Current
Output Low Voltage
TABLE 6. APPLICABLE SUBGROUPS
GROUP A SUBGROUPS
CONFORMANCE
GROUP
MIL-STD-883
METHOD
TESTED FOR -Q
RECORDED
FOR -Q
TESTED FOR -8
Initial Test
100% 5004
1, 7, 9
1 (Note 2)
1, 7, 9
Interim Test
100% 5004
1, 7, 9, ∆
1, ∆ (Note 2)
1, 7, 9
PDA
100% 5004
1, 7, ∆
-
1, 7
Final Test
100% 5004
2, 3, 8A, 8B, 10, 11
-
2, 3, 8A, 8B, 10, 11
Group A (Note 1)
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
-
1, 2, 3, 7, 8A, 8B, 9,
10, 11
Subgroup B5
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, ∆
1, 2, 3, ∆ (Note 2)
N/A
Subgroup B6
Sample 5005
1, 7, 9
-
N/A
Group C
Sample 5005
N/A
N/A
1, 2, 3, 7, 8A, 8B, 9,
10, 11
Group D
Sample 5005
1, 7, 9
-
1, 7, 9
Group E, Subgroup 2
Sample 5005
1, 7, 9
-
1, 7, 9
RECORDED
FOR -8
NOTES:
1. Alternate Group A testing in accordance with MIL-STD-883 method 5005 may be exercised.
2. Table 5 parameters only
Spec Number
926
518058
HS-82C37ARH
Intersil Space Level Product Flow -Q
Wafer Lot Acceptance (All Lots) Method 5007
(Includes SEM)
100% Interim Electrical Test 1 (T1)
GAMMA Radiation Verification (Each Wafer) Method 1019,
2 Samples/Wafer, 0 Rejects
100% PDA 1, Method 5004 (Note 1)
100% Delta Calculation (T0-T1)
100% Die Attach
100% Dynamic Burn-In, Condition D, 240 Hours, +125oC or
Equivalent, Method 1015
100% Nondestructive Bond Pull, Method 2023
100% Interim Electrical Test 2(T2)
Sample - Wire Bond Pull Monitor, Method 2011
100% Delta Calculation (T0-T2)
Sample - Die Shear Monitor, Method 2019 or 2027
100% PDA 2, Method 5004 (Note 1)
100% Internal Visual Inspection, Method 2010, Condition A
100% Final Electrical Test
CSI and/or GSI PreCap (Note 6)
100% Fine/Gross Leak, Method 1014
100% Temperature Cycle, Method 1010, Condition C,
10 Cycles
100% Radiographic (X-Ray), Method 2012 (Note 2)
100% Constant Acceleration, Method 2001, Condition per
Method 5004
Sample - Group A, Method 5005 (Note 3)
100% External Visual, Method 2009
Sample - Group B, Method 5005 (Note 4)
100% PIND, Method 2020, Condition A
Sample - Group D, Method 5005 (Notes 4 and 5)
100% External Visual
100% Data Package Generation (Note 7)
100% Serialization
CSI and/or GSI Final (Note 6)
100% Initial Electrical Test (T0)
100% Static Burn-In 1, Condition A or B, 72 Hours Min,
+125oC Min, Method 1015
NOTES:
1. Failures from subgroup 1, 7 and deltas are used for calculating PDA. The maximum allowable PDA = 5% with no more than 3% of the
failures from subgroup 7.
2. Radiographic (X-Ray) inspection may be performed at any point after serialization as allowed by Method 5004.
3. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005.
4. Group B and D inspections are optional and will not be performed unless required by the P.O. When required, the P.O. should include
separate line items for Group B Test, Group B Samples, Group D Test and Group D Samples.
5. Group D Generic Data, as defined by MIL-I-38535, is optional and will not be supplied unless required by the P.O. When required, the
P.O. should include a separate line item for Group D Generic Data. Generic data is not guaranteed to be available and is therefore not
available in all cases.
6. CSI and/or GSI inspections are optional and will not be performed unless required by theP.O. When required, the P.O. should include
separate line items for CSI PreCap inspection, CSI final inspection, GSI PreCap inspection, and/or GSI final inspection.
7. Data Package Contents:
• Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number, Quantity).
• Wafer Lot Acceptance Report (Method 5007). Includes reproductions of SEM photos with percent of step coverage.
• GAMMA Radiation Report. Contains Cover page, disposition, Rad Dose, Lot Number, Test Package used, Specification Numbers, Test
equipment, etc. Radiation Read and Record data on file at Intersil.
• X-Ray report and film. Includes penetrometer measurements.
• Screening, Electrical, and Group A attributes (Screening attributes begin after package seal).
• Lot Serial Number Sheet (Good units serial number and lot number).
• Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test.
• Group B and D attributes and/or Generic data is included when required by the P.O.
• The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed
by an authorized Quality Representative.
Spec Number
927
518058
HS-82C37ARH
Intersil Space Level Product Flow -8
GAMMA Radiation Verification (Each Wafer) Method 1019,
2 Samples/Wafer, 0 Rejects
100% Dynamic Burn-In, Condition D, 160 Hours, +125oC or
Equivalent, Method 1015
100% Die Attach
100% Interim Electrical Test
Periodic- Wire Bond Pull Monitor, Method 2011
100% PDA, Method 5004 (Note 1)
Periodic- Die Shear Monitor, Method 2019 or 2027
100% Final Electrical Test
100% Internal Visual Inspection, Method 2010, Condition B
100% Fine/Gross Leak, Method 1014
CSI an/or GSI PreCap (Note 5)
100% External Visual, Method 2009
100% Temperature Cycle, Method 1010, Condition C,
10 Cycles
Sample - Group A, Method 5005 (Note 2)
100% Constant Acceleration, Method 2001, Condition per
Method 5004
Sample - Group C, Method 5005 (Notes 3 and 4)
Sample - Group B, Method 5005 (Note 3)
100% External Visual
Sample - Group D, Method 5005 (Notes 3 and 4)
100% Data Package Generation (Note 6)
100% Initial Electrical Test
CSI and/or GSI Final (Note 5)
NOTES:
1. Failures from subgroup 1, 7 are used for calculating PDA. The maximum allowable PDA = 5%.
2. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005.
3. Group B, C and D inspections are optional and will not be performed unless required by the P.O. When required, the P.O. should include
separate line items for Group B Test, Group C Test, Group C Samples, Group D Test and Group D Samples.
4. Group C and/or Group D Generic Data, as defined by MIL-I-38535, is optional and will not be supplied unless required by the P.O. When
required, the P.O. should include a separate line item for Group C Generic Data and/or Group D Generic Data. Generic data is not guaranteed to be available and is therefore not available in all cases.
5. CSI and/or GSI inspections are optional and will not be performed unless required by theP.O. When required, the P.O. should include
separate line items for CSI PreCap inspection, CSI final inspection, GSI PreCap inspection, and/or GSI final inspection.
6. Data Package Contents:
• Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number, Quantity).
• GAMMA Radiation Report. Contains Cover page, disposition, Rad Dose, Lot Number, Test Package used, Specification Numbers, Test
equipment, etc. Radiation Read and Record data on file at Intersil.
• Screening, Electrical, and Group A attributes (Screening attributes begin after package seal).
• Group B, C and D attributes and/or Generic data is included when required by the P.O.
• The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed
by an authorized Quality Representative.
AC Test Circuit
AC Testing Input, Output Waveforms
V1
VOH
VDD -1.5V
1.5V
INPUT
R1
VIL -0.4V
OUTPUT FROM
DEVICE UNDER TEST
OUTPUT
VOL
TEST POINT
C1*
Z
OUTPUT
L OR H
VOH
2.0V
0.8V
*Includes Stray and Jig Capacitance
L OR H
VOH
VOH - 0.45V
0.45
Z
VOL
TEST CONDITION DEFINITION TABLE
PINS
V1
R1
C1
All Output Except EOP
1.7V
510Ω
100pF
EOP
VDD
1.6KΩ
50pF
Spec Number
928
518058
HS-82C37ARH
Waveforms
CS
TIWHAX
TIWLIWH
IOW
TAVIWL
A0-A3
TIWHAX
INPUT VALID
TIWHDX
TDVIWH
DB0-DB7
INPUT VALID
FIGURE 1. SLAVE MODE TIMING
NOTE: Host system must allow at least TCLCL as recovery time between successive write accesses
CS
A0-A3
ADDRESS MUST BE VALID
TAVIRL
TIRHAX
TIRLIRH
IOR
TIRLDV
TIRHDZ
DB0-DB7
DATA OUT VALID
FIGURE 2. SLAVE MODE READ
NOTE: Host system must allow at least TCLCL as recovery time between successive write accesses
S2
S3
SW
SW
S4
CLK
TCHRH
TCHRWL
READ*
TCHRWL
TCHRWL
WRITE*
EXTENDED
WRITE
TCLRYX
TCHWH
TCLRYX
TRYVCL
TRYVCL
READY
FIGURE 3. READY
* READ refers to both IOR and MEMR outputs. WRITE refers to both IOW and MEMW outputs
Spec Number
929
518058
HS-82C37ARH
Waveforms
SI
(Continued)
SI
S0
S1
S0
S2
S3
S4
S2
S3
S4
S1
SI
SI
CLK
TDQVCL
TDQVCL
TCLCL
TCLCH
DREQ
TCHRQV
TCHCL
TCHRQV
HRQ
TRAVCH
HLDA
TCLAEH
AEN
TCHAEL
TCLSL
TCLSH
TSHSL
TEPLCL
ADSTB
TDVSL
DB0-DB7
TCLDAV
TSLDZ
TCHDV
A8-A15
TCHAV
TCHAV
A0-A7
TWHAX
TCHDZ
ADDRESS VALID
TWHAZ
ADDRESS VALID
TCLDAV
TRHAX
TCHRH
DACK
TCHAZ
TRHAZ
TCHRWL
TCHRH
TCHRWV
TCHRWL
TWHRH
TCHRWZ
TRLRH1
READ*
TCHWH
TCHRWL
TCHWH
TWLWH2
WRITE*
TWLWH1
INT EOP
TCHRWL
TCHIPH
(FOR EXTENDED WRITE)
TEPLEPH
TCHIPL
EXT EOP
FIGURE 4. DMA TRANSFER
* READ refers to both IOR and MEMR outputs. WRITE refers to both IOW and MEMW outputs
Spec Number
930
518058
HS-82C37ARH
Waveforms
(Continued)
S0
S11
S12
S13
S14
S21
S22
S23
S24
SI
CLK
TCLSH
TCLSL
TCLSH
TCLSL
ADSTB
TSLDZ
TCHAV
TSLDZ
TCHAV
A0 - A7
ADDRESS VALID
TCHAZ
ADDRESS VALID
TCHDZ
TCHDV
DB0 - DB7
IN
A8 - A15
TCHRWL
A8 - A15
TCHDV
TCHRH
TDVMWH
TMRHDX
MEMR
OUT
TMWHDZ
TDVMRH
TCHWH
TCHRVW
TCHRWL
TCHRWL
TCHRWZ
EXTENDED
WRITE
TCHIPL
INT EOP
TCHIPH
TEPLCL
TEPLEPH
FIGURE 5. MEMORY-TO-MEMORY TRANSFER
VDD
TPHRSL
TRSHRSL
RESET
TRSLIRWL
IOR OR IOW
FIGURE 6. RESET
Spec Number
931
518058
HS-82C37ARH
Waveforms
(Continued)
S2
S4
S2
S4
CLK
TCHAV
TCHAV
VALID
A0 - A7
VALID
TCHRH
TCHRWL
TCHRWL
TCHRH
TRLRH2
READ*
TCHWH
TCHWH
WRITE*
TCLRYX
TRYVCL
TCLRYX
TRYVCL
READY
FIGURE 7. COMPRESSED TRANSFER
* READ refers to both IOR and MEMR outputs. WRITE refers to both IOW and MEMW outputs
Spec Number
932
518058
HS-82C37ARH
Burn-In Circuits
HS-82C37ARH 40 LEAD SBDIP
HS-82C37ARH 40 LEAD SBDIP
VDD
1
40
2
39
3
38
4
37
5
36
6
35
7
34
8
33
9
32
10
31
11
30
F0
12
29
F1
13
28
14
27
15
26
16
25
17
24
18
23
19
22
20
21
VDD
1
40
LOAD
2
39
LOAD
LOAD
3
38
LOAD
LOAD
4
37
LOAD
NC
5
36
F0
6
35
7
34
LOAD
8
33
LOAD
9
32
LOAD
10
31
11
30
F0
12
29
F5
13
28
F5
LOAD
14
27
F4
LOAD
15
26
F1
16
25
LOAD
F2
17
24
LOAD
F3
18
23
F2
19
22
F1
20
21
F0
F4
F3
VDD
2.7KΩ
STATIC CONFIGURATION
NOTES:
LOAD
1. VDD = +6.0V ± 5%
Part is Static Sensitive
2. TA = +125oC Minimum
Voltage Must be Ramped
2.7KΩ
3. Resistors:
R1 = 10kΩ ± 10% (Pins 6, 7, 11-13, 17 - 20)
R2 = 2.7kΩ ± 5% (Pins 1, 2, 21-23, 24, 28-32, 34-39)
F0
F1
START-UP TIMING
NOTES:
DYNAMIC CONFIGURATION
NOTES:
1. F0 is 50% duty cycle square wave pulse burst.
1. VDD = 6.5V ± 5% (Burn-In)
2. 1.0kHz ≤ F0 ≤ 100kHz
2. VDD = 6.0V ± 5% (Life Test)
F0 is left High after pulse burst
3. 10 cycles ≤ F0 Pulse Burst ≤ 1.0s
3. TA = +125oC Minimum
4. F1 = Single pulse with width equal to 2 cycles of F0
4. Part is Static Sensitive, Voltage Must be Ramped
5. F1 is left Low after pulse burst
5. Resistors:
R1 = 10kΩ ± 10% (Pins 6, 7, 11-13, 17 - 20)
R2 = 2.7kΩ ± 10% (Pins 1, 2, 22-24, 28-32, 34-37, and LOADS)
6. F1 pulse occurs after start of F0 and ends before F0.
Input levels: 0.9VDD ≤ VIH ≤ VDD, -0.3V ≤ VIL ≤ 0.7V
Spec Number
933
518058
HS-82C37ARH
Burn-In Circuits
(Continued)
HS-82C37ARH 42 LEAD CERAMIC FLATPACK
HS-82C37ARH 42 LEAD CERAMIC FLATPACK
VDD
1
42
1
42
LOAD
2
41
2
41
LOAD
3
40
LOAD
3
40
LOAD
4
39
LOAD
4
39
LOAD
5
38
OPEN
5
38
6
37
6
37
7
36
7
36
8
35
LOAD
8
35
9
34
LOAD
9
34
LOAD
10
33
11
32
F0
10
33
11
32
F0
12
31
F0
12
31
F1
13
30
F5
13
30
F5
29
F4
VDD
14
29
LOAD
14
15
28
LOAD
15
28
16
27
OPEN
16
27
OPEN
17
26
F1
17
26
LOAD
18
25
F2
18
25
LOAD
19
24
F3
19
24
F2
20
23
F4
20
23
F1
21
22
21
22
F0
F3
VDD
STATIC CONFIGURATION
2.7KΩ
NOTES:
1. VDD = +6.0V ± 5%
Part is Static Sensitive
2. TA = +125oC Minimum
Voltage Must be Ramped
LOAD
2.7KΩ
3. Resistors:
R1 = 10kΩ ± 10% (Pins 6, 7, 11-13, 16-19)
R2 = 2.7kΩ ± 5% (Pins 1, 2, 21-23, 26-30, 32-36)
F0
F1
START-UP TIMING
NOTES:
DYNAMIC CONFIGURATION
NOTES:
1. F0 is 50% duty cycle square wave pulse burst.
1. VDD = 6.5V ± 5% (Burn-In)
2. 1.0kHz ≤ F0 ≤ 100kHz
2. VDD = 6.0V ± 5% (Life Test)
F0 is left High after pulse burst
3. 10 cycles ≤ F0 Pulse Burst ≤ 1.0s
3. TA = +125oC Minimum
4. F1 = Single pulse with width equal to 2 cycles of F0
4. Part is Static Sensitive, Voltage Must be Ramped
5. F1 is left Low after pulse burst
5. Resistors:
R1 = 10kΩ ± 10% (Pins 6, 7, 11-13, 16-19)
R2 = 2.7kΩ ± 10% (Pins 1, 2, 21-23, 26-30, 32-36, and LOADS)
6. F1 pulse occurs after start of F0 and ends before F0.
Input levels: 0.9VDD ≤ VIH ≤ VDD, -0.3V ≤ VIL ≤ 0.7V
Spec Number
934
518058
HS-82C37ARH
Irradiation Circuit
R
1
40
LOAD
2
39
LOAD
LOAD
3
38
LOAD
LOAD
4
37
LOAD
R
NC
R
5
36
6
35
R
LOAD
VCC
2.7KΩ
OUT
R
2.7KΩ
R
R
7
34
LOAD
8
33
LOAD
9
32
LOAD
R
10
31
VSS
R
R
TOGGLE
CLOCK
RESET
TOGGLE
VCC
11
30
LOAD 2
12
29
LOAD 2
13
28
LOAD 2
LOAD 2
14
27
LOAD 2
LOAD 2
R
15
26
LOAD 2
16
25
LOAD 2
17
24
LOAD 2
18
23
LOAD 2
19
22
LOAD 2
20
21
LOAD 2
R
R
R
R
R
VSS
5.5V
LOAD 2
OUT
2.7KΩ
VSS
NOTES:
1. R = 47kΩ
2. Pins with Load: 3, 4, 8, 9, 10, 37-40
Pins with Load2: 14, 15, 21-30
Pins Brought Out: 12 (Clock), 13 (Reset)
3. VDD = 5.5V ± 0.5V
Spec Number
935
518058
HS-82C37ARH
Functional Description
The HS-82C37ARH Direct Memory Access Controller is
designed to improve the data transfer rate in systems which
must transfer data from an I/O device to memory, or move a
block of memory to an I/O device. It will also perform memory-to-memory block moves, or fill a block of memory with
data from a single location. Operating modes are provided to
handle single byte transfers as well as discontinuous data
streams, which allows the HS-82C37ARH to control data
movement with software transparency.
The DMA controller is a state-driven address and control signal generator, which permits data to be transferred directly
from an I/O device to memory or vice versa without ever
being stored in a temporary register. This can greatly
increase the data transfer rate for sequential operations,
compared with processor moves or repeated string instructions. Memory-to-Memory operations require temporary
internal storage of the data byte between generation of the
source and destination addresses, so Memory-to-Memory
transfers take place at less than half the rate of I/O operations, but still much faster than with central processor techniques. The maximum data transfer rate obtainable with the
HS-82C37ARH is approximately 2.5 Mbytes/second, for an I/O
operation using the compressed timing option and 5MHz clock.
The block diagram of the HS-82C37ARH is shown on page
2. The Timing and Control Block, Priority Block, and internal
registers are the main components. Figure 8 lists the name
and size of the internal registers. The Timing and Control
Block derives internal timing from the CLOCK input, and
generates external control signals. The Priority Encoder
Block resolves priority contention between DMA channels
requesting service simultaneously.
NAME
SIZE
NUMBER
Base Address Registers
16 Bits
4
Base Word Count Registers
16 Bits
4
Current Address Registers
16 bits
4
Current Word Count Registers
16 bits
4
Temporary Address Register
16 bits
1
Temporary Word Count Register
16 bits
1
Status Register
8 bits
1
Command Register
8 bits
1
Temporary Register
8 bits
1
Mode Registers
6 bits
4
Mask Registers
4 bits
1
Request Register
4 bits
1
address byte. While inactive, the controller’s outputs are in a
high impedance state. When activated by a DMA request
and bus control is relinquished by the host, the HS82C37ARH drives the busses and generates the control signals to perform the data transfer. The operation performed
by activating one of the four DMA request inputs has previously been programmed into the controller via the Command, Mode, Address, and Word Count Registers.
For example, if a block of data is to be transferred from RAM
to an I/O device, the starting address of the data is loaded
into the HS-82C37ARH Current and Base Address Registers
for a particular channel, and the length of the block is loaded
into that channel’s Word Count Register. The corresponding
Mode Register is programmed for a Memory-to-I/O operation (read transfer), and various options are selected by the
Command Register and other Mode Register bits. The channel’s mask bit is cleared to enable recognition of a DMA
request (DREQ). The DREQ can either be a hardware signal
or a software command.
Once initiated, the block DMA transfer will proceed as the
controller outputs the data address, simultaneous MEMR
and IOW pulses, and selects an I/O device via the DMA
acknowledge (DACK) outputs. The data byte flows directly
from the RAM to the I/O device. After each byte is transferred, the address is automatically incremented (or decremented) and the word count is decremented. The operation
is then repeated for the next byte. The controller stops transferring data when the Word Count Register underflows, or
an external EOP is applied.
To further understand HS-82C37ARH operation, the states
generated by each clock cycle must be considered. The
DMA controller operates in two major cycles, Active and Idle.
After being programmed, the controller is normally Idle until
a DMA request occurs on an unmasked channel, or a software request is given. The HS-82C37ARH will then request
control of the system busses and enter the Active cycle. The
Active cycle is composed of several internal states, depending on what options have been selected and what type of
operation has been requested.
The HS-82C37ARH can assume seven separate states,
each composed of one full clock period. State I (SI) is the
Idle state. It is entered when the HS-82C37ARH has no valid
DMA requests pending, at the end of a transfer sequence, or
when a Reset or Master Clear has occurred. While in SI, the
DMA controller is inactive but may be in the Program Condition (being programmed by the processor.)
FIGURE 8 . HS-82C37ARH INTERNAL REGISTERS
DMA Operation
In a system, the HS-82C37ARH address and control outputs
and data bus pins are basically connected in parallel with the
system busses. An external latch is required for the upper
State 0 (S0) is the first state of a DMA service. The HS82C37ARH has requested a hold but the processor has not
yet returned an acknowledge. The HS-82C37ARH may still
be programmed until it has received HLDA from the CPU. An
acknowledge from the CPU will signal that DMA transfers
may begin. S1, S2, S3 and S4 are the working states of the
DMA service. If more time is needed to complete a transfer
than is available with normal timing, wait states (SW) can be
inserted between S2 or S3 and S4 by the use of the Ready
line on the HS-82C37ARH.
Spec Number
936
518058
HS-82C37ARH
Note that the data is transferred directly from the I/O device
to memory (or vice versa) with IOR and MEMW (or MEMR
and IOW) being active at the same time. The data is not read
into or driven out of the HS-82C37ARH in I/O-to-memory or
memory-to-I/O DMA transfers.
Memory-to-Memory transfers require a read-from and a
write-to-memory to complete each transfer. The states,
which resemble the normal working states, use two-digit
numbers for identification. Eight states are required for a single transfer. The first four states (S11, S12, S13, S14 are
used for the read-from-memory half and the last four states
(S21, S22, S23, S24) for the write-to-memory half of the
transfer.
Idle Cycle
When no channel is requesting service, the HS-82C37ARH
will enter the Idle cycle and perform “SI” states. In this cycle,
the HS-82C37ARH will sample the DREQ lines on the falling
edge of every clock cycle to determine if any channel is
requesting a DMA service.
Note that for standby operation where the clock has been
stopped, DMA requests will be ignored. The device will
respond to CS (chip select), in case of an attempt by the
microprocessor to write or read the internal registers of the
HS-82C37ARH. When CS is low and HLDA is low, the HS82C37ARH enters the Program Condition. The CPU can
now establish, change or inspect the internal definition of the
part by reading from or writing to the internal registers.
The HS-82C37ARH may be programmed with the clock
stopped, provided that HLDA is low and at least one rising
clock edge has occurred after HLDA was driven low, so the
controller is in an SI state. Address lines A0-A3 are inputs to
the device and select which registers will be read or written.
The IOR and IOW lines are used to select and time the read
or write operations. Due to the number and size of the internal registers, an internal flip-flop is used to generate an additional bit of address. The bit is used to determine the upper
or lower byte of the 16-bit Address and Word Count Registers. The flip-flop is reset by Master Clear or Reset. Separate
software commands can also set or reset this flip-flop.
Special software commands can be executed by the HS82C37ARH in the Program Condition. These commands are
decoded as sets of addresses with CS, IOR, and IOW. The
commands do not make use of the data bus. Instructions
include Set and Clear First/Last Flip-Flop, Master Clear,
Clear Mode Register Counter, and Clear Mask Register.
Active Cycle
When the HS-82C37ARH is in the Idle cycle, and a software
request or an unmasked channel requests a DMA service,
the device will output an HRQ to the microprocessor and
enter the Active cycle. It is in this cycle that the DMA service
will take place, in one of four modes:
Single Transfer Mode - In Single Transfer mode, the device
is programmed to make one transfer only. The word count
will be decremented and the address decremented or incremented following each transfer. When the word count “rolls
over” from zero to FFFFH, a terminal count (TC) bit in the
Status Register is set, an EOP pulse is generated, and the
channel will Autoinitialize if this option has been selected. If
not programmed to Autoinitialize, the mask bit will be set,
along with the TC bit and EOP pulse.
DREQ must be held active until DACK becomes active. If
DREQ is held active throughout the single transfer (there-by
triggering a second transfer), HRQ will still go inactive and
release the bus to the system. Then it will again go active
and, upon receipt of a new HLDA, another single transfer will
be performed, unless a higher priority channel takes over. In
HS-80C85RH or HS-80C86RH systems, this will ensure one
full machine cycle execution between DMA transfers. Details
of timing between the HS-82C37ARH and other bus control
protocols will depend upon the characteristics of the microprocessor involved.
Block Transfer Mode - In Block Transfer Mode, the device
is activated by DREQ or software request and continues
making transfers during the service until a TC, caused by
word count going to FFFFH, or an external End of Process
(EOP) is encountered. DREQ need only beheld active until
DACK becomes active. Again, an Autoinitialization will occur
at the end of the service if the channel has been programmed for that option.
Demand Transfer Mode - In Demand Transfer Mode the
device continues making transfers until a TC or external
EOP is encountered, or until DREQ goes inactive. Thus,
transfers may continue until the I/O device has exhaust edits
data capacity. After the I/O device has had a chance to catch
up, the DMA service is reestablished by means of a DREQ.
During the time between services when the micro-processor
is allowed to operate, the intermediate values of address
and word count are stored in the HS-82C37ARH Current
Address and Current Word Count Registers. Higher priority
channels may intervene in the demand process, once DREQ
has gone inactive. Only an EOP can cause an Autoinitialization at the end of the service. EOP is generated either by TC
or by an external signal.
Cascade Mode - This mode is used to cascade more than
one HS-82C37ARH for simple system expansion. The HRQ
and HLDA signals from the additional HS-82C37ARH are
connected to the DREQ and DACK signals respectively of a
channel for the initial HS-82C37ARH. This allows the DMA
requests of the additional device to propagate through the
priority network circuitry of the preceding device. The priority
chain is preserved and the new device must wait for its turn
to acknowledge requests. Since the cascade channel of the
initial HS-82C37ARH is used only for prioritizing the additional device, it does not output an address or control signals
of its own so that there is no conflict with the cascaded
device. The HS-82C37ARH will respond to DREQ and generate DACK but all other outputs except HRQ will be disabled. An external EOP will be ignored by the initial device,
but will have the usual effect on the added device.
Figure 9 shows two additional devices cascaded with an initial device using two of the previous channels. This forms a
two-level DMA system. More HS-82C37ARHs could be
added at the second level by using the remaining channels
of the first level. Additional devices can also be added by
cascading into the channels of the second level devices,
forming a third level.
Spec Number
937
518058
HS-82C37ARH
HS-80C86RH
MICROPROCESSOR
2ND LEVEL
gram effort and time, the HS-82C37ARH includes a Memory-to-Memory transfer feature. Programming a bit in the
Command Register selects channels 0 and 1 to operate as
Memory-to-Memory transfer channels.
HS-82C37ARH
The transfer is initiated by setting the software or hardware
DREQ for channel 0. The HS-82C37ARH requests a DMA
service in the normal manner. After HLDA is true, the device,
using four-state transfers in Block Transfer Mode, reads data
from the memory. The channel 0 Current Address Register is
the source for the address used and is decremented or
incremented in the normal manner. The data byte read from
the memory is stored in the HS-82C37ARH internal Temporary Register. Another four-state transfer moves the data to
memory using the address in channel 1’s Current Address
Register and incrementing or decrementing it in the normal
manner. The channel 1 Current Word Count Register is decremented.
1ST LEVEL
HRQ
HLDA
DREQ
DACK
HRQ
HLDA
HS-82C37ARH
DREQ
DACK
HRQ
HLDA
INITIAL DEVICE
HS-82C37ARH
ADDITIONAL
DEVICES
FIGURE 9. CASCADED HS-82C37ARHs
When programming cascaded controllers, start with the first
level (closest to the microprocessor). After RESET, the
DACK outputs are programmed to be active low and are
held in the high state. If they are used to drive HLDA directly,
the second level device(s) cannot be programmed until
DACK polarity is selected as active high on the initial device.
Also, the initial device’s mask bits function normally on cascaded channels, so they may be used to inhibit second-level
services.
Transfer Types
Each of the three active transfer modes can perform three
different types of transfers. These are Read, Write and Verify. Write transfers move data from an I/O device to the memory by activating MEMW and IOR. Read transfers move data
from memory to an I/O device by activating MEMR and IOW.
Verify transfers are pseudo-transfers. The HS-82C37ARH
operates as in Read or Write transfers generating addresses
and responding to EOP, etc., however the memory and I/O
control lines all remain inactive. Verify mode is not permitted
for Memory-to-Memory operation. Ready is ignored during
Verify transfers.
Autoinitialize - By programming a bit in the Mode Register,
a channel may be set up as an Autoinitialize channel. During
Autoinitialization, the original values of the Current Address
and Current Word Count Registers are automatically
restored from the Base Address and Base Word Count Registers of that channel following EOP. The base registers are
loaded simultaneously with the current registers by the
microprocessor and remain unchanged throughout the DMA
service. The mask bit is not set when the channel is in Autoinitialize. Following Autoinitialization, the channel is ready to
perform another DMA service, without CPU intervention, as
soon as a valid DREQ is detected, or software request made.
Memory-to-Memory - To perform block moves of data from
one memory address space to another with minimum of pro-
When the word count of channel 1 goes to FFFFH, a TC is
generated causing an EOP output terminating the service.
Channel 0 word count decrementing to FFFFH will not set
the channel 0 TC bit in the Status Register or generate an
EOP in this mode. It will cause an Autoinitialization of channel 0, if that option has been selected.
If full Autoinitialization for a Memory-to-Memory operation is
desired, the channel 0 and channel 1 word counts must be
set equal before the transfer begins. Otherwise, if channel 0
underflows before channel 1, it will Autoinitialize and set the
data source address back to the beginning of the block. If
the channel 1 word count underflows before channel 0, the
Memory-to-Memory DMA service will terminate, and channel
1 will Autoinitialize but channel 0 will not.
In Memory-to-Memory Mode, Channel 0 may be programmed to retain the same address for all transfers. This
allows a single byte to be written to a block of memory. This
channel 0 address hold feature is selected by bit 1 in the
Command Register.
The HS-82C37ARH will respond to external EOP signals
during Memory-to-Memory transfers, but will only relinquish
the system busses after the transfer is complete (i.e., after
an S24 state). Data comparators in block search schemes
may use this input to terminate the service when a match is
found. The timing of Memory-to-Memory transfers is found in
Figure 5. Memory-to-Memory operations can be detected as
an active AEN with no DACK outputs.
Priority - The HS-82C37ARH has two types of priority
encoding available as software selectable options. The first
is Fixed Priority which fixes the channels in priority order
based upon the descending value of their numbers. The
channel with the lowest priority is 3 followed by 2, 1 and the
highest priority channel, 0. After the recognition of any one
channel for service, the other channels are prevented from
interfering with the service until it is completed.
The second scheme is Rotating Priority. The last channel to
get service becomes the lowest priority channel with the others rotating accordingly. The next lower channel from the
channel serviced has highest priority on the following
request: Priority rotates every time control of the system
busses is returned to the processor.
Spec Number
938
518058
HS-82C37ARH
Programming
Rotating Priority
1sr
Highest 0
1
service
The HS-82C37ARH will accept programming from the host
processor anytime that HLDA is inactive, and at least one
rising clock edge has occurred after HLDA went low. It is the
responsibility of the host to assure that programming and
HLDA are mutually exclusive.
3rd
Service
2nd
Service
Service
2
service
3
3
request
0
2
0
1
Lowest 3
1
2
service
With Rotating Priority in a single chip DMA system, any
device requesting service is guaranteed to be recognized
after no more than three higher priority services have
occurred. This prevents any one channel from monopolizing
the system.
Regardless of which priority scheme is chosen, priority is
evaluated every time a HLDA is returned to the
HS-82C37ARH.
Compressed Timing - In order to achieve even greater
throughput where system characteristics permit, the HS82C37ARH can compress the transfer time to two clock
cycles. From Figure 4 it can be seen that state S3 is used to
extend the access time of the read pulse. By removing state
S3, the read pulse width is made equal to the write pulse
width and a transfer consists only of state S2 to change the
address and state S4 to perform the read/write. S1 states
will still occur when A8-A15 need updating (see Address
Generation). Timing for compressed transfers is found in
Figure 7. EOP will be output in S2 if compressed timing is
selected. Compressed Timing is not allowed for Memory-toMemory transfers.
Address Generation - In order to reduce pin count, the HS82C37ARH multiplexes the eight higher order address bits
on the data lines. State S1 is used to output the higher order
address bits to an external latch from which they may be
placed on the address bus. The falling edge of Address
Strobe (ADSTB) is used to load these bits from the data
lines to the latch. Address Enable (AEN) is used to enable
the bits onto the address bus through a three-state enable.
The lower order address bits are output by the HS82C37ARH directly. Lines A0-A7 should be connected to the
address bus. Figure 4 shows the time relationships between
CLK, AEN, ADSTB, DB0-DB7 and A0-A7.
During Block and Demand Transfer Mode service, which
include multiple transfers, the addresses generated will be
sequential. For many transfers the data held in the external
address latch will remain the same. This data need only
change when a carry or borrow from A7 to A8 takes place in
the normal sequence of addresses. To save time and speed
transfers, the HS-82C37ARH executes S1 states only when
updating of A8-A15 in the latch is necessary. This means for
long services, S1 states and Address Strobes may occur
only once every 256 transfers, a savings
of 255 clock
cycles for each 256 transfers.
Note that a problem can occur if a DMA request occurs on
an unmasked channel while the HS-82C37ARH is being programmed. For instance, the CPU may be starting to reprogram the two byte Address Register of channel 1 when
channel 1 receives a DMA request. If the HS-82C37ARH is
enabled (bit 2 in the command register is 0), and channel 1
is unmasked, a DMA service will occur after only one byte of
the Address Register has been reprogrammed. This condition can be avoided by disabling the controller (setting bit 2
in the Command Register) or masking the channel before
programming any of its registers. Once the programming is
complete, the controller can be enabled/unmasked.
After power-up it is suggested that all internal locations be
loaded with some known value, even if some channels are
unused. This will aid in debugging.
Register Description
Current Address Register - Each channel has a 16-bit Current Address Register. This register holds the value of the
address used during DMA transfers. The address is automatically incremented or decremented after each transfer
and the values of the address are stored in the Current
Address Register during the transfer. This register is written
or read by the microprocessor in successive 8-bit bytes. It
may also be reinitialized by an Autoinitialize back to its original value. Autoinitialize takes place only after an EOP. In
Memory-to-Memory Mode, the channel 0 Current Address
Register can be prevented from incrementing or decrementing by setting the address hold bit in the Command Register.
Current Word Register - Each channel has a 16-Bit Current
Word Count Register. This register determines the number
of transfers to be performed. The actual number of transfers
will be one more than the number programmed in the Current Word Count Register (i.e., programming a count of 100
will result in 101 transfers). The word count is decremented
after each transfer. When the value in the register goes from
zero to FFFFH, a TC will be generated. This register is
loaded or read in successive 8-bit bytes by the microprocessor in the Program Condition. Following the end of a DMA
service it may also be reinitialized by an Autoinitialization
back to its original value. Autoinitialization can occur only
when an EOP occurs. If it is not Autoinitialized, this register
will have a count of FFFFH after TC.
Base Address and Base Word Count Registers - Each
channel has a pair of Base Address and Base Word Count
Registers. These 16-bit registers store the original value of
their associated current registers. During Autoinitialization,
these values are used to restore the current registers to their
original values. The base registers are written simultaneously with their corresponding current register in 8-bit
bytes in the Program Condition by the microprocessor.
These registers cannot be read by the microprocessor.
Spec Number
939
518058
HS-82C37ARH
Mask Register - Each channel has associated with it a
mask bit which can be set to disable an incoming DREQ.
Each mask bit is set when its associated channel produces
an EOP if the channel is not programmed to Autoinitialize.
Each bit of the 4-bit Mask Register may also be set or
cleared separately or simultaneously under soft-ware control. The entire register is also set by a Reset or Master
Clear. This disables all hardware DMA requests until a clear
Mask Register instruction allows them to occur. The instruction to separately set or clear the mask bits is similar in form
to that used with the Request Register. Refer to the following
table and Figure 10 for details. When reading the Mask Register, bits 4-7 will always read as logical ones, and bits 0-3
will display the mask bits of channel 0-3, respectively. The 4
bits of the Mask Register may be cleared simultaneously by
using the Clear Mask Register command (see software commands section).
Mode Register - Each channel has a 6-bit Mode Register
associated with it. When the register is being written to by
the microprocessor in the Program Condition, bits 0 and 1
determine which channel Mode Register is to be written.
When the processor reads a Mode Register, bits 0 and 1 will
both be ones. See the adjacent table and Figure 10 for Mode
Register functions and addresses.
Mode Register
7
6
5
4
3
2
1
Mask Register
7
6
5
4
3
2
1
BIT NUMBER
0
DON’T CARE
6
5
4
DON’T CARE,
WRITE ALL
ONES,
READ
3
2
1
0
00
01
10
11
XX
CHANNEL 0 SELECT
CHANNEL 1 SELECTT
CHANNEL 2 SELECT
CHANNEL 3 SELECT
READBACK
00
01
10
11
XX
VERIFY TRANSFER
WRITE TRANSFER
READ TRANSFER
ILLEGAL
IF BITS 6 AND 7 = 11
0
1
AUTOINITIALIZATION DISABLE
AUTOINITIALIZATION ENABLE
00
01
10
11
SELECT CHANNEL 0 MASK BIT
SELECT CHANNEL 1 MASK BIT
SELECT CHANNEL 2 MASK BIT
SELECT CHANNEL 3 MASK BIT
0
1
ADDRESS INCREMENT SELECT
ADDRESS DECREMENT SELECT
0
1
CLEAR MASK BIT
SET MASK BIT
00
01
10
11
DEMAND MODE SELECT
SINGLE MODE SELECT
BLOCK MODE SELECT
CASCADE MODE SELECT
All four bits of the Mask Register may also be written with a
single command.
7
BIT NUMBER
0
BIT NUMBER
0 CLEAR CHANNEL 0 MASK BIT
1 SET CHANNEL 0 MASK BIT
0 CLEAR CHANNEL 1 MASK BIT
1 SET CHANNEL 1 MASK BIT
0 CLEAR CHANNEL 2 MASK BIT
1 SET CHANNEL 2 MASK BIT
0 CLEAR CHANNEL 3 MASK BIT
1 SET CHANNEL 3 MASK BIT
Request Register - The HS-82C37ARH can respond to
requests for DMA service which are initiated by software as
well as by a DREQ. Each channel has a request bit associated with it in the 4-bit Request Register. These are nonmaskable and subject to prioritization by the Priority Encoder
network. Each register bit is set or reset separately under
software control. The entire register is cleared by a Reset. To
set or reset a bit, the software loads the proper form of the
data word. See Figure 10 for register address coding, and
the following table for Request Register format. A software
request for DMA operation can be made in Block or Single
Modes. For Memory-to-Memory transfers, the software
request for channel 0 should be set. When reading the
Request Register, bits 4-7 will always read as ones, and bits
0-3 will display the request bits of channels 0-3 respectively.
Request Register
7
6
5
4
3
DON’T CARE,
WRITE BITS 4-7
ALL ONES, READ
2
1
BIT NUMBER
0
00
01
10
11
SELECT CHANNEL 0
SELECT CHANNEL 1
SELECT CHANNEL 2
SELECT CHANNEL 3
0
1
RESET REQUEST BIT
SET REQUEST BIT
Spec Number
940
518058
HS-82C37ARH
Command Register - This 8-bit register controls the
operation of the HS-82C37ARH. It is programmed by the
microprocessor and is cleared by Reset or a Master Clear
instruction. The adjacent table lists the function of the
command bits. See Figure 10 for Read and Write addresses.
Command Register
7
6
5
4
3
2
1
BIT NUMBER
0
0 MEM-TO-MEM DISABLE
1 MEM-TO-MEM ENABLE
0 CH. 0 ADDR. HOLD DISABLE
1 CH. 0 ADDR. HOLD ENABLE
X IF BIT 0 = 0
0 CONTROLLER ENABLE
1 CONTROLLER DISABLE
Status Register - The Status Register contains information
about the present status of the HS-82C37ARH and can be
read by the microprocessor. This information includes which
channels have reached a terminal count and which channels
have pending DMA requests. Bits 0-3 are set every time a
TC is reached by that channel or an external EOP is applied.
These bits are cleared upon Reset, Master Clear, and on
each Status Read. Bits 4-7 are set whenever their corresponding channel is requesting service, regardless of the
mask bit state. If the mask bits are set, software can poll the
Status Register to determine which channels have DREQs,
and selectively clear a mask bit, thus allowing user defined
service priority. Status bits 4-7 are updated while the clock is
high, and latched on the falling edge. Status Bits 4-7 are
cleared upon Reset or Master Clear.
Status Register
0 NORMAL TIMING
1 COMPRESSED TIMING
X IF BIT 0 = 1
7
6
5
4
3
2
1
BIT NUMBER
0
0 FIXED PRIORITY
1 ROTATING PRIORITY
0 LATE WRITE SELECTION
1 EXTENDED WRITE SEL.
X IF BIT 3 = 1
0 DREQ SENSE ACTIVE HIGH
1 DREQ SENSE ACTIVE LOW
0 DACK SENSE ACTIVE LOW
1 DACK SENSE ACTIVE HIGH
1
1
1
1
CHANNEL 0 HAS REACHED TC
CHANNEL 1 HAS REACHED TC
CHANNEL 2 HAS REACHED TC
CHANNEL 3 HAS REACHED TC
1
1
1
1
CHANNEL 0 REQUEST
CHANNEL 1 REQUEST
CHANNEL 2 REQUEST
CHANNEL 3 REQUEST
Temporary Register - The Temporary Register is used to
hold data during Memory-to-Memory transfers. Following the
completion of the transfer, the last word moved can be read
by the microprocessor by accessing this register. The Temporary Register always contains the last byte transferred in
the previous Memory-to-Memory operation, unless cleared
by a Reset or Master Clear.
A3
A2
A1
A0
IOR
IOW
Read Status Register
OPERATION
1
0
0
0
0
1
Write Command Register
1
0
0
0
1
0
Read Request Register
1
0
0
1
0
1
Write Request Register
1
0
0
1
1
0
Read Command Register
1
0
1
0
0
1
Write Single Mask Bit
1
0
1
0
1
0
Read Mode Register
1
0
1
1
0
1
Write Mode Register
1
0
1
1
1
0
Set Byte Pointer F/F
1
1
0
0
0
1
Clear Byte Pointer F/F
1
1
0
0
1
0
Read Temporary Register
1
1
0
1
0
1
Master Clear
1
1
0
1
1
0
Clear Mode Reg. Counter
1
1
1
0
0
1
Clear Mask Register
1
1
1
0
1
0
Read All Mask Bits
1
1
1
1
0
1
1
1
1
1
1
0
Write All Mask Bits
FIGURE 10. SOFTWARE COMMAND CODES AND REGISTER CODES
Spec Number
941
518058
HS-82C37ARH
Software Commands
There are special software commands which can be executed by reading or writing to the HS-82C37ARH. These
commands do not depend on the specific data pattern on the
data bus, but are activated by the I/O operation itself. On
read type commands, the data value is not guaranteed.
These commands are:
Clear First/Last Flip-Flop: This command is executed prior
to writing or reading new address or word count information
to the HS-82C37ARH. This initializes the flip-flop to a known
state so that subsequent accesses to register contents by
the microprocessor will address upper and lower bytes in the
correct sequence.
Set First/Last Flip-Flop: This command will set the flip-flop
to select the high byte first on read and write operations to
Address and Word Count registers.
Master Clear: This software instruction has the same effect
as the hardware Reset. The Command, Status, Request,
and Temporary Registers, and Internal First/Last Flip-Flop
and Mode Register Counter are cleared and the Mask Register is set. The HS-82C37ARH will enter the Idle cycle.
Clear Mask Register: This command clears the mask bits of
all four channels, enabling them to accept DMA requests.
CHANNEL
0
1
2
3
REGISTER
OPERA
TION
Clear Mode Register Counter: Since only one address
location is available for reading the Mode Registers, an internal two-bit counter has been included to select Mode Registers during read operations. To read the Mode Registers,
first execute the Clear Mode Register Counter command,
then do consecutive reads until the desired channel is read.
Read order is channel 0 first, channel 3 last. The lower two
bits on all Mode Registers will read as ones.
External EOP Operation
The EOP pin is a bidirectional, open drain pin which may be
driven by external signals to terminate DMA operation.
Because EOP is an open drain pin an external pull-up resistor is required. The value of the external pull-up resistor used
should guarantee a rise time of less than 125ns. It is important to note that the HS-82C37ARH will not accept external
EOP signals when it is in an SI (Idle)state. The controller
must be active to latch EXT EOP. Once latched, the EXT
EOP will be acted upon during the next S2 state, unless the
HS-82C37ARH enters an Idle state first. In the latter case
the latched EOP is cleared. External EOP pulses occurring
between active DMA transfers in demand mode will not be
recognized, since the HS-82C37ARH is in an SI state.
SIGNALS
CS
IOR
IOW
A3
A2
A1
A0
INTERNAL
FLIP-FLOP
DATA BUS
DB0-DB7
Base and Current
Address
Write
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
A0-A7
A8-A15
Current Address
Read
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
1
A0-A7
A8-A15
Base and Current Word
Count
Write
0
0
1
1
0
0
0
0
0
0
0
0
1
1
0
1
W0-W7
W8-W15
Current Word Count
Read
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
1
W0-W7
W8-W15
Base and Current
Address
Write
0
0
1
1
0
0
0
0
0
0
1
1
0
0
0
1
A0-A7
A8-A15
Current Address
Read
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
1
A0-A7
A8-A15
Base and Current Word
Count
Write
0
0
1
1
0
0
0
0
0
0
1
1
1
1
0
1
W0-W7
W8-W15
Current Word Count
Read
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
1
W0-W7
W8-W15
Base and Current
Address
Write
0
0
1
1
0
0
0
0
1
1
0
0
0
0
0
1
A0-A7
A8-A15
Current Address
Read
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
1
A0-A7
A8-A15
Base and Current Word
Count
Write
0
0
1
1
0
0
0
0
1
1
0
0
1
1
0
1
W0-W7
W8-W15
Current Word Count
Read
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
W0-W7
W8-W15
Base and Current
Address
Write
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
1
A0-A7
A8-A15
Current Address
Read
0
0
0
0
1
1
0
0
1
1
1
1
0
0
0
1
A0-A7
A8-A15
Base and Current Word
Count
Write
0
0
1
1
0
0
0
0
1
1
1
1
1
1
0
1
W0-W7
W8-W15
Current Word Count
Read
0
0
0
0
1
1
0
0
1
1
1
1
1
1
0
1
W0-W7
W8-W15
FIGURE 11. WORD COUNT AND ADDRESS REGISTER COMMAND CODES
Spec Number
942
518058
HS-82C37ARH
Application Information
Figure 12 shows an application for a DMA system utilizing
the HS-82C37ARH DMA controller and the HS-80C86RH
Microprocessor. In this application, the HS-82C37ARH DMA
controller is used to improve system performance by allowing an I/O device to transfer data directly to or from system
memory.
Components
The system clock is generated by the HS-82C85RH clock
controllers generator and is inverted to meet the clock high
and low times required by the HS-82C37ARH DMA controller. The four OR gates are used to support the HS-80C86RH
Microprocessor in minimum mode by producing the control
signals used by the processor to access memory or I/O. A
decoder is used to generate chip select for the DMA controller and memory. The HS-82C37ARH multiplexes the most
significant bits of the address on its data outputs (DB0 - 7),
so the 82C82 octal latch is used to demultiplex the address.
A three-state inverter is used to generate the BHE signal
using the A0 output of the HS-82C37ARH. Hold Acknowl-
edge (HLDA) and Address Enable (AEN) are “ORed”
together and used to deactivate the microprocessors 82C82
transceiver to insure that the DMA controller does not have
bus contention with the microprocessor.
Operation
A DMA request (DREQ) is generated by the I/O device. After
receiving the DMA request, the DMA controller will issue a
Hold Request (HRQ) to the processor. The system busses
are not released to the DMA controller until a Hold Acknowledge (HLDA) signal is returned to the DMA controller from
the HS-80C86RH processor. After the Hold Acknowledge
has been received, addresses and control signals are generated by the DMA controller to accomplish the DMA transfers.
Data is transferred directly from the I/O device to memory (or
vice versa) with IOR and MEMW (or MEMR and IOW) being
active. Note that data is not read into or driven out of the
DMA controller in I/O-to-Memory or Memory-to-I/O data
transfers.
MEMCS
HLDA
VDD
DECODER
HS-82C37ARH
HS-82C85RH
HLDA
HRQ
ALE
STB
ADDRESS
BUS
AD0
CLK
CLK
CS
ADSTB
AEN
OE
EOP
HLDA
IOR
IOW
AD15
MEMR
STB
82C82
M/10
RD
WR
BHE
OE
VDD
MEMW
HRQ
82C82
A0-7
DATA BUS
MN/MX
DB0-7
DREQ0
DACK0
HS-80C86RH
BHE
A0
MEMR
MEMW
ADDRESS BUS
I/O
DEVICE
IOR
CS
MEMORY
IOW
DREQ
MEMCS
DATA BUS
IOR
MEMR
MEMW
IOW
FIGURE 12. APPLICATION FOR DMA SYSTEM
Spec Number
943
518058
HS-82C37ARH
Metallization Topology
DIE DIMENSIONS:
215 x 232 mils x 19 ± 1 mil
METALLIZATION:
Type: Al/Si
Thickness: 11kÅ ± 2kÅ
GLASSIVATION:
Thickness: 8kÅ ± 1kÅ
WORST CASE CURRENT DENSITY:
7.9 x 104 A/cm2
Metallization Mask Layout
(35) A3
(36) EOP
(37) A4
(38) A5
(39) A6
(40) A7
(1) IOR
(2) IOW
(3) MEMR
(4) MEMW
(5) NC
(6) READY
HS-82C37ARH
HLDA (7)
(34) A2
ADSTB (8)
(33) A1
AEN (9)
(32) A0
HRQ (10)
(31) VDD
CS (11)
(30) DB0
(29) DB1
CLK (12)
(28) DB2
RESET (13)
(27) DB3
DACK2 (14)
DACK0 (25)
DACK1 (24)
DB5 (23)
DB6 (22)
DB7 (21)
VSS (20)
DREQ0 (19)
DREQ1 (18)
DREQ2 (17)
DREQ3 (16)
DACK3 (15)
(26) DB4
Spec Number
944
518058
HS-82C37ARH
Packaging
E
1
K42.A TOP BRAZED
42 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
N
e
INCHES
A
A
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.100
-
2.54
-
b
0.017
0.025
0.43
0.64
-
S1
b1
0.017
0.023
0.43
0.58
-
c
0.007
0.013
0.18
0.33
-
C
c1
0.007
0.010
0.18
0.25
-
D
b
E1
L
A
Q
E2
c1
LEAD FINISH
BASE
METAL
(c)
b1
M
M
MILLIMETERS
(b)
SECTION A-A
NOTES:
1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark. Alternately, a tab (dimension k)
may be used to identify pin one.
D
1.045
1.075
26.54
27.31
3
E
0.630
0.650
16.00
16.51
-
17.27
3
13.97
-
E1
-
0.680
E2
0.530
0.550
e
0.050 BSC
k
-
-
13.46
1.27 BSC
-
11
-
-
L
0.320
0.350
8.13
8.89
-
Q
0.045
0.065
1.14
1.65
8
S1
0.000
-
0.00
-
6
M
-
0.0015
-
0.04
-
N
42
42
Rev. 0 6/17/94
2. If a pin one identification mark is used in addition to a tab, the limits of dimension k do not apply.
3. This dimension allows for off-center lid, meniscus, and glass
overrun.
4. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate
lead finish is applied.
5. N is the maximum number of terminal positions.
6. Measure dimension S1 at all four corners.
7. For bottom-brazed lead packages, no organic or polymeric materials shall be molded to the bottom of the package to cover the
leads.
8. Dimension Q shall be measured at the point of exit (beyond the
meniscus) of the lead from the body. Dimension Q minimum
shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
11. The basic lead spacing is 0.050 inch (1.27mm) between center
lines. Each lead centerline shall be located within ±0.005 inch
(0.13mm) of its exact longitudinal position relative to lead 1 and
the highest numbered (N) lead.
Spec Number
945
518058
HS-82C37ARH
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (407) 724-7000
FAX: (407) 724-7240
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
Intersil (Taiwan) Ltd.
Taiwan Limited
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
Spec Number
946
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