HANBit HSD32M64F8V/VA Synchronous DRAM Module, 256Mbyte ( 32M x 64-Bit ) SMM based on 32Mx8, 4Banks, 8K Ref., 3.3V Part No. HSD32M64F8V/VA GENERAL DESCRIPTION The HSD32M64F8V/VA is a 32M x 64 bit Synchronous Dynamic RAM high density memory module. The module consists of eight CMOS 8M x 8 bit with 4banks Synchronous DRAMs in TSOP-II packages is mounted on a 120-pin, double-sided, FR-4-printed circuit board., Two 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The HSD32M64F8V/VA is a SMM (Stackable Memory Module) designed and is intended for mounting into two 60-pin connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications All module components may be powered from a single 3.3V DC power supply and all inputs and outputs are LVTTL-compatible. PIN ASSIGNMENT FEATURES • Part Identification HSD32M64F8V : Stacking Height ( T = 11.3mm ) HSD32M64F8VA : Stacking Height ( T = 7.3mm ) • Burst mode operation • Auto & self refresh capability (8192 Cycles/64ms) • LVTTL compatible inputs and outputs • Single 3.3V ±0.3V power supply • MRS cycle with address key programs - Latency (Access from column address) - Burst length (1, 2, 4, 8 & Full page) - Data scramble (Sequential & Interleave) • All inputs are sampled at the positive going edge of the system clock • 120pin-SMM type FR4-PCB design • The used device is 32Mx8bit SRAM • Pin assignment is compatible with - HSD8M64F8V - HSD16M64F8V 60-PIN P1 Connector 60-PIN P2 Connector PIN Symbol PIN Symbol PIN Symbol PIN Symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Vcc DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 Vcc DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 Vcc DQM4 DQM5 NC CKE0 CKE1 Vcc NC NC /CE2 NC Vcc 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Vss DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 Vss DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 Vss DQM0 DQM1 /WE CLK0 CLK1 Vss /CAS /RAS /CE0 NC Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Vss DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 Vss DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 Vss DQM2 DQM3 NC BA0 BA1 A10/AP A0 A1 A2 A3 Vss 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Vcc DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 Vcc DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 Vcc DQM6 DQM7 A12 A11 A9 A8 A7 A6 A5 A4 Vcc Stackable Memory Module TOP VIEW URL:www.hbe.co.kr REV.1.0 (August.2002) 1 HANBit Electronics Co.,Ltd. HANBit HSD32M64F8V/VA FUNCTIONAL BLOCK DIAGRAM DQ0-63 CKE0 /CAS CKE CAS /RAS RAS /CE0 CE U1 WE A0-A12 CKE CAS CE U2 WE A0-A12 CKE CAS U3 WE A0-A12 CKE CAS U4 WE A0-A12 CKE CAS U5 WE A0-A12 CKE CAS U6 WE A0-A12 CKE CAS U7 WE A0-A12 CKE CAS DQM2 BA0-1 DQM6 DQM6 BA0-1 DQM1 DQM1 BA0-1 DQM5 DQM5 BA0-1 DQM3 DQM3 BA0-1 CLK DQ56-63 U8 RAS CE DQM2 CLK DQ24-31 RAS CE DQM4 BA0-1 CLK DQ40-47 RAS CE DQM4 CLK1 CLK DQ8-15 RAS CE DQM0 CLK DQ48-55 RAS CE DQM0 BA0-1 CLK DQ16-23 RAS CE CLK0 CLK DQ32-39 RAS /CE2 CLK DQ0-7 WE A0-A12 DQM7 DQM7 BA0-1 /WE A0 - A12 BA0-1 Vcc Two 0.1uF Capacitors per each SDRAM Vss URL:www.hbe.co.kr REV.1.0 (August.2002) 2 HANBit Electronics Co.,Ltd. HANBit HSD32M64F8V/VA PIN FUNCTION DESCRIPTION Pin Name Input Function CLK System clock Active on the positive going edge to sample all inputs. /CE Chip enable Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM CKE Clock enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+tSS prior to valid command. A0 ~ A12 Address Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA12, Column address : CA0 ~ CA9 BA0 ~ BA1 Bank select address Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. /RAS Row address strobe Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. /CAS /WE Column address Latches column addresses on the positive going edge of the CLK with CAS low. strobe Enables column access. Write enable Enables write operation and row precharge. Latches data in starting from CAS, WE active. DQM0 ~ 7 Data input/output Makes data output Hi-Z, tSHZ after the clock and masks the output. mask Blocks data input when DQM active. (Byte masking) DQ0 ~ 63 Data input/output Data inputs/outputs are multiplexed on the same pins. Vcc/Vss Power Power and ground for the input buffers and the core logic. supply/ground ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING VIN ,OUT -1V to 4.6V Voltage on Vcc Supply Relative to Vss Vcc -1V to 4.6V Power Dissipation PD 8W TSTG -55oC to 150oC Voltage on Any Pin Relative to Vss Storage Temperature Short Circuit Output Current IOS 400mA Notes : Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. URL:www.hbe.co.kr REV.1.0 (August.2002) 3 HANBit Electronics Co.,Ltd. HANBit HSD32M64F8V/VA DC OPERATING CONDITIONS (Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70° C) ) PARAMETER SYMBOL MIN TYP. MAX UNIT NOTE Supply Voltage Vcc 3.0 3.3 3.6 V Input High Voltage VIH 2.0 3.0 Vcc+0.3 V 1 Input Low Voltage VIL -0.3 0 0.8 V 2 Output High Voltage VOH 2.4 - - V IOH = -2mA Output Low Voltage VOL - - 0.4 V IOL = 2mA Input leakage current I LI -10 10 uA Notes : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns. 3. Any input 0V ≤ VIN ≤ VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. 3 CAPACITANCE (VCC = 3.3V, TA = 23° C, f = 1MHz, VREF =1.4V ± 200 mV) DESCRIPTION SYMBOL MIN MAX UNITS Clock CCLK 20 32 pF Address CADD 20 40 pF /RAS, /CAS, /WE, /CS, CKE, DQM C IN 20 40 pF DQ (DQ0 ~ DQ15) COUT 32 52 pF URL:www.hbe.co.kr REV.1.0 (August.2002) 4 HANBit Electronics Co.,Ltd. HANBit HSD32M64F8V/VA DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, TA = 0 to 70° C) TEST PARAMETER VERSION SYMBOL CONDITION -13 -12 -10 -10L 960 960 880 880 UNIT NOTE mA 1 Burst length = 1 Operating current ICC1 (One bank active) tRC ≥ tRC(min) IO = 0mA Precharge standby current in ICC2P power-down mode ICC2PS CKE ≤ VIL(max) 16 mA 16 mA tCC=10ns CKE & CLK ≤ VIL(max) tCC=∞ CKE ≥ VIH(min) ICC2N CS* ≥ VIH(min), tCC=10ns 128 Input signals are changed Precharge standby current in one time during 20ns non power-down mode mA CKE ≥ VIH(min) ICC2NS CLK ≤ VIL(max), tCC=∞ 112 Input signals are stable Active standby current power-down mode in ICC3P ICC3PS CKE ≤ VIL(max), tCC=10ns 48 CKE&CLK ≤ VIL(max) mA 48 tCC=∞ CKE≥VIH(min), Active standby current in ICC3N CS*≥VIH(min), tCC=10ns non power-down mode one time during 20ns (One bank active) CKE≥VIH(min) ICC3NS 240 Input signals are changed CLK ≤VIL(max), mA tCC=∞ 200 Input signals are stable IO = 0 mA Operating current (Burst mode) Page burst ICC4 1120 1120 920 920 mA 1 1680 1680 1600 1600 mA 2 4Banks Activated tCCD = 2CLKs Refresh current ICC5 Self refresh current ICC6 tRC ≥ tRC(min) CKE ≤ 0.2V 40 mA 16 mA Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Unless otherwise noticed, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ). URL:www.hbe.co.kr REV.1.0 (August.2002) 5 HANBit Electronics Co.,Ltd. HANBit HSD32M64F8V/VA AC OPERATING TEST CONDITIONS (vcc = 3.3V ± 0.3V, TA = 0 to 70° C) PARAMETER Value UNIT 2.4/0.4 V 1.4 V tr/tf = 1/1 ns 1.4 V AC Input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition See Fig. 2 +3.3V Vtt=1.4V 1200Ω 50Ω DOUT 870Ω DOUT Z0=50Ω 50pF* 50pF VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA (Fig. 2) AC output load circuit (Fig. 1) DC output load circuit OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) VERSION PARAMETER SYMBOL -13 -12 -10 -10L UNIT NOTE Row active to row active delay tRRD(min) 15 16 20 20 ns 1 RAS to CAS delay tRP(min) 20 20 20 20 ns 1 Row precharge time tRP(min) 20 20 20 20 ns 1 tRAS(min) 45 48 50 50 ns 1 Row active time Row cycle time tRAS(max) tRC(min) 100 65 68 ns 70 70 ns 1 Last data in to row precharge tRDL(min) 2 CLK 2.5 Last data in to Active delay tDAL(min) 2 CLK + 20 ns - 5 Last data in to new col. address delay tCDL(min) 1 CLK 2 Last data in to burst stop tBDL(min) 1 CLK 2 Col. address to col. address delay tCCD(min) 1 CLK 3 ea 4 CAS latency=3 2 Number of valid output data CAS latency=2 URL:www.hbe.co.kr REV.1.0 (August.2002) - 6 1 HANBit Electronics Co.,Ltd. HANBit HSD32M64F8V/VA Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. 5. For -8/H/L, tRDL=1CLK and tDAL=1CLK+20ns is also supported . (Recommand : tRDL=2CLK and tDAL=2CLK & 20ns.) AC CHARACTERISTICS (AC operating conditions unless otherwise noted) -13 PARAMETER MIN CLK cycle time -12 -10 -10L SYMBOL MAX MIN MAX MIN MAX MIN UNIT NOTE ns 1 ns 1,2 ns 2 MAX CAS 7.5 8 10 10 latency=3 tCC 1000 1000 1000 1000 CAS - - 10 12 latency=2 CLK to valid CAS output delay latency=3 5.4 6 6 6 tSAC CAS - - 6 7 latency=2 Output data CAS hold time latency=3 2.7 3 3 3 tOH CAS - - 3 3 latency=2 CLK high pulse width tCH 2.5 3 3 3 ns 3 CLK low pulse width tCL 2.5 3 3 3 ns 3 Input setup time tSS 1.5 2 2 2 ns 3 Input hold time tSH 0.8 1 1 1 ns 3 CLK to output in Low-Z tSLZ 1 1 1 1 ns 3 2 CLK to output CAS in Hi-Z latency=3 5.4 6 6 6 ns - - 6 7 ns tSHZ CAS latency=2 Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, ie., [(tr + tf)/2-1]ns should be added to the parameter. URL:www.hbe.co.kr REV.1.0 (August.2002) 7 HANBit Electronics Co.,Ltd. HANBit HSD32M64F8V/VA SIMPLIFIED TRUTH TABLE COMMAND Register Mode register set Auto refresh Refresh Entry Self refresh Exit Bank active & row addr. Read & column address Write & column address Auto CKE n /C S /R A S /C A S /W E D Q M H X L L L L X OP code L L L H X X L H H H H X X X X X L L H H H H L L H H X X BA 0,1 V precharge disable Auto CKE n-1 precharge H X L H L H X Auto H X L H L L X Precharge H Clock suspend or active power down Precharge power down mode X H X Entry H L Exit L H All banks Entry Exit DQM No operation command 3 3 3 3 Column H (A0 ~ A9) L Address 4,5 H L L H L L L L H L L H X X X L V V V X X X X H X X X L H H H H X X X L V V V H H H X X H X X X L H H H X X X 8 4 (A0 ~ A9) 4,5 X V L X H 6 X X X X X X V X X X (V=Valid, X=Don't care, H=Logic high, L=Logic low) Notes : 1. OP Code : Operand code A0 ~ A12 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2) URL:www.hbe.co.kr REV.1.0 (August.2002) 4 Address H disable Bank selection 1,2 L V precharge Burst Stop NOTE Column precharge disable A11,A12, A9~A0 Row address V disable Auto A10/ AP HANBit Electronics Co.,Ltd. 7 HANBit HSD32M64F8V/VA TIMING DIAGRAMS Please refer to timing diagram chart (II) PACKAGING INFORMATION Unit : mm HSD32M64F8V 82.68. 5.00 5.00 0.90 31 31 1 0.90 1 30.00 60 60 P1 30 P2 30 0.90 0.90 Bottom View 1.30 PM 9.00 8.00 4.60 T = 11.3 PB MAIN BOARD 7.75 Connector Configuration - Module PCB Bottom (PM) : 177986-2, 0.8mm Free Height Plugs, 60pins - Main Board top (PB) : 5-179180-2,0.8mm Free Height Receptacles , 60pins URL:www.hbe.co.kr REV.1.0 (August.2002) 9 HANBit Electronics Co.,Ltd. HANBit HSD32M64F8V/VA HSD32M64F8VA 82.68. 5.00 5.00 0.90 31 31 1 0.90 1 30.00 60 30 P2 60 30 P1 0.90 0.90 Bottom View 1.30 PM 5.00 4.00 T = 7.3 4.60 PB MAIN BOARD 3.75 Connector Configuration - Module PCB Bottom (PM) : 177984-2, 0.8mm Free Height Plugs, 60pins - Main Board top (PB) : 177983-2,0.8mm Free Height Receptacles , 60pins URL:www.hbe.co.kr REV.1.0 (August.2002) 10 HANBit Electronics Co.,Ltd. HANBit HSD32M64F8V/VA ORDERING INFORMATION Part Number Density Org. HSD32M64F8V-13 256MByte 32Mx 64 HSD32M64F8V-F13 256Mbyte 32Mx 64 HSD32M64F8V-12 256Mbyte 256Mbyte 32Mx 64 HSD32M64F8V-10 256Mbyte 32Mx 64 HSD32M64F8V-F10 256Mbyte 32Mx 64 HSD32M64F8VA-13 256MByte 32Mx 64 256Mbyte 120 Pin SMM 120 Pin SMM 120 Pin 32Mx 64 HSD32M64F8V-F12 HSD32M64F8VA-F13 Package SMM 120 Pin SMM 120 Pin SMM 120 Pin SMM 120 Pin SMM 120 Pin 32Mx 64 HSD32M64F8VA-12 256Mbyte 32Mx 64 HSD32M64F8VA-F12 256Mbyte 32Mx 64 HSD32M64F8VA-10 256Mbyte 32Mx 64 HSD32M64F8VA-F10 256Mbyte 32Mx 64 SMM 120 Pin SMM 120 Pin SMM 120 Pin SMM 120 Pin SMM Ref. Vcc 8K 3.3V 8K 3.3V 8K 3.3V 8K 3.3V 8K 3.3V 8K 3.3V 3.3V 8K 3.3V 8K 3.3V 8K 3.3V 8K 3.3V MAX.frq 133MHz (CL=3) Low Power 133MHz (CL=3) 125MHz 3.3V 8K 8K Feature (CL=3) Low 125MHz Power (CL=3) 100MHz (CL=2) Low 100MHz Power (CL=2) 133MHz (CL=3) Low Power 133MHz (CL=3) 125MHz (CL=3) Low 125MHz Power (CL=3) 100MHz (CL=2) Low 100MHz Power (CL=2) * F means Auto & Self refresh with Low-Power (3.3V) * HSD32M64F8V : T = 11.3mm * HSD32M64F8VA : URL:www.hbe.co.kr REV.1.0 (August.2002) T = 7.3mm 11 HANBit Electronics Co.,Ltd.