HT27C512 OTP CMOS 64K×8-Bit EPROM Features • • • • • • • • • • • • • Operating voltage: +5.0V Programming voltage – VPP=12.2V±0.2V – VCC=5.8V±0.2V High-reliability CMOS technology Latch-up immunity to 100mA from -1.0V to VCC+1.0V CMOS and TTL compatible I/O Low power consumption – Active: 30mA max. – Standby: 1µA typ. • 64K×8-bit organization Fast read access time: 70ns, 90ns and 120ns Fast programming algorithm Programming time 75µs typ. Two line control (OE & CE) Standard product identification code Package type – 28-pin DIP/SOP – 32-pin PLCC Commercial temperature range (0°C to +70°C) General Description The HT27C512 chip family is a low-power, 512K bit, +5V electrically one-time programmable (OTP) read-only memories (EPROM). Organized into 64K words with 8 bits per word, it features a fast single address location programming, typically at 75µs per byte. Any byte can be accessed in less than 70ns/90ns with respect to Spec. This eliminates the need for WAIT states in high-performance microprocessor systems. The HT27C512 has separate Output Enable (OE) and Chip Enable (CE) controls which eliminate bus contention issues. Block Diagram 1 6th May ’99 HT27C512 Pin Assignment Pin Description Pin Name A0~A15 DQ0~DQ7 CE OE/VPP I/O/C/P I I/O C C/P Description Address inputs Data inputs/outputs Chip enable Output enable/program voltage supply NC — No connection VCC I Positve power supply VSS I Negative power supply 2 6th May ’99 HT27C512 Absolute Maximum Ratings Operation Temperature Commercial ...................................................................................0°C to +70°C Storage Temperature......................................................................................................... –65°C to 125°C Applied VCC Voltage with Respect to VSS ........................................................................ –0.6V to 7.0V Applied Voltage on Input Pin with Respect to VSS........................................................... –0.6V to 7.0V Applied Voltage on Output Pin with Respect to VSS............................................... –0.6V to VCC+0.5V Applied Voltage on A9 Pin with Respect to VSS.............................................................. –0.6V to 13.5V Applied VPP Voltage with Respect to VSS .......................................................................–0.6V to 13.5V Applied READ Voltage (Functionality is guaranteed between these limits) ................ +4.5V to +5.5V Note: These are stress ratings only. Stresses exceeding the range specified under “Absolute Maximum Ratings” may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. D.C. Characteristics Read operation Symbol Test Conditions Parameter VCC Min. Typ. Max. Unit Conditions VOH Output High Level 5V IOH=–0.4mA 2.4 — — V VOL Output Low Level 5V IOL=2.1mA — — 0.45 V VIH Input High Level 5V — 2.0 — VCC+0.5 V VIL Input Low Level 5V — –0.3 — 0.8 V ILI Input Leakage Current 5V VIN=0 to 5.5V –5 — 5 µA ILO Output Leakage Current 5V VOUT=0 to 5.5V –10 — 10 µA ICC VCC Active Current 5V CE=VIL, f=5MHz, IOUT=0mA — — 30 mA ISB1 Standby Current (CMOS) 5V CE=VCC±0.3V — 1.0 10 µA ISB2 Standby Current (TTL) 5V CE=VIH — — 1.0 mA IPP VPP Read/Standby Current 5V CE=OE=VIL, VPP=VCC — — 100 µA 3 6th May ’99 HT27C512 Programming operation Symbol Test Conditions Parameter VCC Min. Typ. Max. Unit Conditions VOH Output High Level 5.8V IOH=–0.4mA 2.4 — — V VOL Output Low Level 5.8V IOL=2.1mA — — 0.45 V VIH Input High Level 5.8V — 0.7VCC — VCC+0.5 V VIL Input Low Level 5.8V — –0.5 — 0.8 V ILI Input Load Current 5.8V VIN=VIL, VIH — — 5.0 µA VH A9 Product ID Voltage 5.8V — 11.5 — 12.5 V ICC VCC Supply Current 5.8V — — — 40 mA IPP VPP Supply Current 5.8V CE=VIL — — 10 mA Capacitance Symbol Test Conditions Parameter VCC Min. Typ. Max. Unit Conditions CIN Input Capacitance 5V VIN=0V — 8 12 pF COUT Output Capacitance 5V VOUT=0V — 8 12 pF CVPP VPP Capacitance 5V VPP=0V — 18 25 pF A.C. Characteristics Read operation Symbol Parameter Test Conditions VCC Conditions –70 –90 Unit Min. Max. Min. Max. tACC Address to Output Delay 5V CE=OE=VIL — 70 — 90 ns tCE Chip Enable to Output Delay 5V OE=VIL — 70 — 90 ns tOE Output Enable to Output Delay 5V CE=VIL — 30 — 35 ns tDF CE or OE High to Output Float, Whichever Occurred First 5V — — 25 — 25 ns tOH Output Hold from Address, CE or OE, Whichever Occurred First 5V — 0 — 0 — ns 4 6th May ’99 HT27C512 Ta=+25°C±5°C Programming operation Symbol Test Conditions Parameter VCC Conditions Min. Typ. Max. Unit tAS Address Setup Time 5.8V — 2 — — µs tOES CE/VPP Setup Time 5.8V — 2 — — µs tOEH OE/VPP Hold Time 5.8V — 2 — — µs tDS Data Setup Time 5.8V — 2 — — µs tAH Address Hold Time 5.8V — 0 — — µs tDH Data Hold Time 5.8V — 2 — — µs tDFP Output Enable to Output Float Delay 5.8V — 0 — 130 ns tPW PGM Program Pulse Width 5.8V — 30 75 105 µs tVCS VCC Setup Time 5.8V — 2 — — µs tDV Data Valid From CE 5.8V — — — 150 ns tVR OE/VPP Recovery Time 5.8V — 2 — — µs Test waveforms and measurements For -70, -90 devices: tR, tF< 20ns (10% to 90%) Output test load 1.3V (1N914) 3.3kΩ Output Pin CL Note: CL=100pF including jig capacitance, except for the -45 devices, where CL=30pF. 5 6th May ’99 HT27C512 Functional Description be performed with OE/VPP and CE at VIL. Data should be verified at tDV after the falling edge of CE. Programming of the HT27C512 When the HT27C512 is delivered, the chip has all 512K bits in the “ONE”, or HIGH state. “ZEROs” are loaded into the HT27C512 through the procedure of programming. Auto product identification The Auto Product Identification mode allows the reading out of a binary code from an EPROM that will identify its manufacturer and type. This mode is intended for use by the programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional in the 25°C±5°C ambient temperature range that is required when programming the HT27C512. The programming mode is entered when 12.2±0.2V is applied to the OE/VPP pin and CE is at VIL. For programming, the data to be programmed is applied with 8 bits in parallel to the data pins. The programming flowchart in Figure 3. shows the fast interactive programming algorithm. The interactive algorithm reduces programming time by using 30µs to 105µs programming pulses and giving each address only as many pulses as is necessary in order to reliably program the data. After each pulse is applied to a given address, the data in that address is verified. If the data is not verified, additional pulses are given until it is verified or until the maximum number of pulses is reached. This process is repeated while sequencing through each address of the HT27C512. This part of the programming algorithm is carried at VCC=5.8V to assure that each EPROM bit is programmed to a sufficiently high threshold voltage. This ensures that all bits have sufficient margin. After the final address is completed, the entire EPROM memory is read at VCC=VPP=5.25±0.25V to verify the entire memory. To activate this mode, the programming equipment must force 12.0±0.5V on the address line A9 of the HT27C512. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0 from VIL to VIH, when A1=VIH. All other address lines must be held at VIH during Auto Product Identification mode. Byte 0 (A0=VIL) represents the manufacturer code, and byte 1 (A0=VIH), the device code. For HT27C512, these two identifier bytes are shown in the Operation mode truth table. All identifiers for the manufacturer and device codes will possess odd parity, with the MSB (DQ7) defined as the parity bit. When A1=VIL, the HT27C512 will read out the binary code of 7F, continuation code, to signify the unavailability of manufacturer ID codes. Program inhibit mode Programming of multiple HT27C512 in parallel with different data is also easily accomplished by using the Program Inhibit Mode. Except for CE, all like inputs of the parallel HT27C512 may be common. A TTL low-level program pulse applied to an HT27C512 CE input with OE/VPP=12.2±0.2V will program that HT27C512. A high-level CE input inhibits the other HT27C512 from being programmed. Read mode The HT27C512 has two control functions, both of which must be logically satisfied in order to obtain data at outputs. Chip Enable (CE) is the power control and should be used for device selection. Output Enable (OE) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that addresses are stable, address access time (tACC) is equal to the delay from CE to output (tCE). Data is available at the outputs (tOE) after the falling edge of OE, assuming the CE has been LOW and addresses have been Program verify mode Verification should be performed on the programmed bits to determine whether they were correctly programmed. The verification should 6 6th May ’99 HT27C512 from the system control bus. This assures that all deselected memory devices are in their lowpower standby mode and that the output pins are only active when data is desired from a particular memory device. stable for at least tACC-tOE. Standby mode The HT27C512 has CMOS standby mode which reduces the maximum VCC current to 10µA. It is placed in CMOS standby when CE is at VCC±0.3V. The HT27C512 also has a TTLstandby mode which reduces the maximum VCC current to 1.0mA. It is placed in TTLstandby when CE is at VIH. When in standby mode, the outputs are in a high-impedance state, independent of the OE input. System considerations During the switch between active and standby conditions, transient current peaks are produced on the rising and falling edges of Chip Enable. The magnitude of these transient current peaks is dependent on the output capacitance loading of the device. At a minimum, a 0.1µF ceramic capacitor (high frequency, low inherent inductance) should be used on each device between VCC and VPP to minimize transient effects. In addition, to overcome the voltage drop caused by the inductive effects of the printed circuit board traces on EPROM arrays, a 4.7µF bulk electrolytic capacitor should be used between VCC and VPP for each eight devices. The location of the capacitor should be close to where the power supply is connected to the array. Two-line output control function To accommodate multiple memory connections, a two-line control function is provided to allow for: • Low memory power consumption • Assurance that output bus contention will not occur. It is recommended that CE be decoded and used as the primary device-selection function, while OE be made a common connection to all devices in the array and connected to the READ line Operation mode truth table All the operation modes are shown in the table following. Mode CE OE/VPP A0 A9 Output Read VIL VIL X (2) X Dout Output Disable VIL VIH X X High Z Standby (TTL) VIH X X X High Z VCC± 0.3V X X X High Z Program VIL VPP X X DIN Program Verify VIL VIL X X DOUT Product Inhibit VIH VPP X X High Z Manufacturer Code (3) VIL VIL VIL VH (1) 1C Device Type Code (3) VIL VIL VIH VH (1) 83 Standby (CMOS) Notes: (1) VH = 12.0V ± 0.5V (2) X=Either VIH or VIL (3) For Manufacturer Code and Device Code, A1=VIH, When A1=VIL, both codes will read 7F 7 6th May ’99 HT27C512 Product Identification Code Pins A0 A1 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 Hex Data Manufacturer 0 1 0 0 0 1 1 1 0 0 1C Device Type 1 1 1 0 0 0 0 0 1 1 83 0 0 0 1 1 1 1 1 1 1 7F 1 0 0 1 1 1 1 1 1 1 7F Code Continuation Figure 1. A.C. waveforms for read operation Figure 2. Programming waveforms 8 6th May ’99 HT27C512 Figure 3. Fast programming flowchart 9 6th May ’99 HT27C512 Holtek Semiconductor Inc. (Headquarters) No.3 Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan, R.O.C. Tel: 886-3-563-1999 Fax: 886-3-563-1189 Holtek Semiconductor Inc. (Taipei Office) 5F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan, R.O.C. Tel: 886-2-2782-9635 Fax: 886-2-2782-9636 Fax: 886-2-2782-7128 (International sales hotline) Holtek Microelectronics Enterprises Ltd. RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong Tel: 852-2-745-8288 Fax: 852-2-742-8657 Copyright © 1999 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. 10 6th May ’99