HT27LC020 CMOS 256K´8-Bit OTP EPROM Features · Operating voltage: +3.3V · 256K´8-bit organization · Programming voltage · Fast read access time: 90ns - VPP=12.5V±0.2V - VCC=6.0V±0.2V · Fast programming algorithm · Programming time 75ms typ. · High-reliability CMOS technology · Two line controls (OE and CE) · Latch-up immunity to 100mA from -1.0V to · Standard product identification code VCC+1.0V · Commercial temperature ranges (0°C to +70°C) · CMOS and TTL compatible I/O · 32-pin DIP/SOP/TSOP/PLCC package · Low power consumption - Active: 15mA max. - Standby: 1mA typ. General Description with respect to Spec. This eliminates the need for WAIT states in high-performance microprocessor systems. The HT27LC020 has separate Output Enable (OE) and Chip Enable (CE) controls which eliminate bus contention issues. The HT27LC020 chip family is a low-power, 2048K (2,097,152) bit, +3.3V electrically one-time programmable (OTP) read-only memories (EPROM). Organized into 256K words with 8 bits per word, it features a fast single address location programming, typically at 75ms per byte. Any byte can be accessed in less than 90ns Block Diagram R o w A d d re s s C o lu m n A d d re s s C E O E P G M Rev. 1.50 X -D e c o d e r C e ll A r r a y V C C Y -D e c o d e r Y - G a tin g C E & O E & P G M & T E S T C o n tr o l L o g ic S A C K T & O u tp u t B u ffe r G N D V P P D Q 0 ~ D Q 7 1 December 8, 2003 HT27LC020 Pin Assignment P G M A 1 4 A 7 5 2 8 A 1 3 A 6 6 2 7 A 8 A 5 7 2 6 A 9 A 4 8 2 5 A 1 1 A 3 9 2 4 O E A 2 1 0 2 3 A 1 0 A 1 1 1 2 2 C E 1 5 1 8 D Q 4 G N D 1 6 1 7 D Q 3 8 2 6 A 9 A 3 9 2 5 A 1 1 A 2 1 0 2 4 A 1 1 1 2 3 O E A 1 0 A 0 D Q 0 1 2 2 2 1 3 2 1 H T 2 7 L C 0 2 0 3 2 P L C C -A C E D Q 7 D Q 6 D Q 2 A 8 A 4 2 0 D Q 5 2 7 1 9 D Q 6 1 9 7 D Q 5 D Q 4 D Q 3 2 0 1 4 A 5 1 8 1 3 D Q 1 A 1 4 A 1 3 1 7 D Q 0 2 8 1 6 D Q 7 2 9 6 G N D D Q 2 D Q 1 2 1 5 A 6 1 5 1 2 A 7 1 4 A 0 3 0 3 1 A 1 7 2 9 1 3 0 4 2 3 3 A 1 5 A 1 2 3 2 V C C 3 1 A 1 7 P G M V C C 3 2 2 4 1 A 1 6 V P P A 1 6 A 1 5 A 1 2 V P P A 1 1 A 9 A 8 A 1 3 A 1 4 A 1 7 P G M V C C V P P A 1 6 A 1 5 A 1 2 A 7 A 6 A 5 A 4 3 2 1 2 3 1 3 0 3 2 9 4 2 8 5 2 7 7 6 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 H T 2 7 L C 0 2 0 3 2 T S O P -A 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 O E A 1 C E D Q D Q D Q D Q D Q G N D Q D Q D Q A 0 A 1 A 2 A 3 0 7 6 5 4 3 D 2 1 0 H T 2 7 L C 0 2 0 3 2 D IP -A /S O P -A Pin Description Pin Name A0~A17 DQ0~DQ7 I/O/C/P I I/O Description Address inputs Data inputs/outputs CE C Chip enable OE C Output enable PGM C Program strobe NC ¾ No connection VPP P Program voltage supply Absolute Maximum Rating Operation Temperature Commercial ............................................................................................................0°C to 70°C Storage Temperature.............................................................................................................................-65°C to 125 °C Applied VCC Voltage with Respect to GND............................................................................................... -0.6V to 7.0V Applied Voltage on Input Pin with Respect to GND.................................................................................... -0.6V to 7.0V Applied Voltage on Output Pin with Respect to GND......................................................................... -0.6V to VCC+0.5V Applied Voltage on A9 Pin with Respect to GND ..................................................................................... -0.6V to 13.5V Applied VPP Voltage with Respect to GND ..............................................................................................-0.6V to 13.5V Applied READ Voltage (Functionality is guaranteed between these limits) ..................................................3.0V to 3.6V Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. Rev. 1.50 2 December 8, 2003 HT27LC020 D.C. Characteristics Symbol Parameter Test Conditions Conditions VCC Min. Typ. Max. Unit Read Operation VOH Output High Level 3.3V IOH=-0.4mA 2.4 ¾ ¾ V VOL Output Low Level 3.3V IOL=2.0mA ¾ ¾ 0.45 V VIH Input High Level 3.3V ¾ 2.0 ¾ VCC+0.5 V VIL Input Low Level 3.3V ¾ -0.3 ¾ 0.8 V ILI Input Leakage Current 3.3V VIN=0 to 3.6V -5 ¾ 5 mA ILO Output Leakage Current 3.3V VOUT=0 to 3.6V -10 ¾ 10 mA ICC VCC Active Current 3.3V ¾ ¾ 15 mA ISB1 Standby Current (CMOS) 3.3V CE=VCC±0.3V ¾ 1.0 10 mA ISB2 Standby Current (TTL) 3.3V CE=VIH ¾ ¾ 0.6 mA IPP VPP Read/Standby Current 3.3V CE=OE=VIL, VPP=VCC ¾ ¾ 100 mA CE=VIL, f=5MHz, IOUT=0mA Programming Operation VOH Output High Level 6V IOH=-0.4mA 2.4 ¾ ¾ V VOL Output Low Level 6V IOL=2.0mA ¾ ¾ 0.45 V VIH Input High Level 6V ¾ 0.7VCC ¾ VCC+0.5 V VIL Input Low Level 6V ¾ -0.5 ¾ 0.8 V ¾ ¾ 5.0 mA ¾ 11.5 ¾ 12.5 V ¾ ILI Input Load Current 6V VH A9 Product ID Voltage 6V ICC VCC Supply Current 6V IPP VPP Supply Current 6V VIN=VIL, VIH ¾ ¾ 40 mA CE=VIL ¾ ¾ 10 mA Capacitance CIN Input Capacitance 3.3V VIN=0V ¾ 8 12 pF COUT Output Capacitance 3.3V VOUT=0V ¾ 8 12 pF CVPP VPP Capacitance 3.3V VPP=0V ¾ 18 25 pF A.C. Characteristics Symbol Ta=+25°C±5°C Parameter Test Conditions VCC Conditions Min. Typ. Max. Unit Read Operation tACC Address to Output Delay 3.3V CE=OE=VIL ¾ ¾ 90 ns tCE Chip Enable to Output Delay 3.3V OE=VIL ¾ ¾ 90 ns tOE Output Enable to Output Delay 3.3V CE=VIL ¾ ¾ 45 ns tDF CE or OE High to Output Float, Whichever 3.3V Occurred First ¾ ¾ ¾ 40 ns tOH Output Hold from Address, CE or OE, Whichever Occurred First ¾ 0 ¾ ¾ ns Rev. 1.50 3.3V 3 December 8, 2003 HT27LC020 Symbol Test Conditions Parameter VCC Conditions Min. Typ. Max. Unit Programming Operation tAS Address Setup Time 6V ¾ 2 ¾ ¾ ms tOES OE Setup Time 6V ¾ 2 ¾ ¾ ms tDS Data Setup Time 6V ¾ 2 ¾ ¾ ms tAH Address Hold Time 6V ¾ 0 ¾ ¾ ms tDH Data Hold Time 6V ¾ 2 ¾ ¾ ms tDFP Output Enable to Output Float Delay 6V ¾ 0 ¾ 130 ns tVPS VPP Setup Time 6V ¾ 2 ¾ ¾ ms tPW PGM Program Pulse Width 6V ¾ 30 75 105 ms tVCS VCC Setup Time 6V ¾ 2 ¾ ¾ ms tCES CE Setup Time 6V ¾ 2 ¾ ¾ ms tOE Data Valid from OE 6V ¾ ¾ ¾ 150 ns tPRT VPP Pulse Rise Time During Programming 6V ¾ 2 ¾ ¾ ms Test Waveforms and Measurements 2 .4 V 2 .0 V A C D r iv in g L e v e ls A C M e a s u re m e n t L e v e l 0 .8 V 0 .4 5 V tR, tF<20ns (10% to 90%) Output Test Load 1 .3 V (1 N 9 1 4 ) 3 .3 k 9 O u tp u t P in C L Note: CL=100pF including jig capacitance. Product Identification Code Pins A0 A1 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 Hex Data Manufacturer 0 1 0 0 0 1 1 1 0 0 1C Device Type 1 1 0 0 0 0 0 0 1 0 02 0 0 0 1 1 1 1 1 1 1 7F 1 0 0 1 1 1 1 1 1 1 7F Code Continuation Rev. 1.50 4 December 8, 2003 HT27LC020 Functional Description Operation Mode All the operation modes are shown in the table following. Mode CE OE PGM A0 A1 A9 VPP Output VIL VIL X (2) X X X VCC Dout Output Disable VIL VIH X X X X VCC High Z Standby (TTL) VIH X X X X X VCC High Z Read VCC±0.3V X X X X X VCC High Z Program VIL VIH VIL X X X VPP DIN Program Verify VIL VIL VIH X X X VPP DOUT Product Inhibit VIH X X X X X VPP High Z Manufacturer Code (3) VIL VIL X VIL VIH VH (1) VCC 1C Device Code (3) VIL VIL X VIH VIH VH (1) VCC 02 Standby (CMOS) Notes: (1) VH = 12.0V±0.5V (2) X=Either VIH or VIL (3) For Manufacturer Code and Device Code, A1=VIH, When A1=VIL, both codes will read 7F Programming of the HT27LC020 12.5±0.2V, PGM Low, and OE High will program that HT27LC020. A high-level CE input inhibits the HT27LC020 from being programmed. When the HT27LC020 is delivered, the chip has all 2048K bits in the ²ONE², or HIGH state. ²ZEROs² are loaded into the HT27LC020 through programming. Program Verify Mode The programming mode is entered when 12.5±0.2V is applied to the VPP pin, OE is at VIH, and CE and PGM are VIL. For programming, the data to be programmed is applied with 8 bits in parallel to the data pins. Verification should be performed on the programmed bits to determine whether they were correctly programmed. The verification should be performed with OE and CE at VIL, PGM at VIH, and VPP at its programming voltage. The programming flowchart in Figure 3 shows the fast interactive programming algorithm. The interactive algorithm reduces programming time by using 30ms to 105ms programming pulses and giving each address only as many pulses as is necessary in order to reliably program the data. After each pulse is applied to a given address, the data in that address is verified. If the data is not verified, additional pulses are given until it is verified or until the maximum number of pulses is reached while sequencing through each address of the HT27LC020. This process is repeated while sequencing through each address of the HT27LC020. This part of the programming algorithm is done at VCC=6.0V to assure that each EPROM bit is programmed to a sufficiently high threshold voltage. This ensures that all bits have sufficient margin. After the final address is completed, the entire EPROM memory is read at VCC=VPP=3.3±0.3V to verify the entire memory. Auto Product Identification The Auto Product Identification mode allows the reading out of a binary code from an EPROM that will identify its manufacturer and the type. This mode is intended for programming to automatically match the device to be programmed with its corresponding programming algorithm. This mode is functional in the 25°C±5°C ambient temperature range that is required when programming the HT27LC020. To activate this mode, the programming equipment must force 12.0±0.5V on the address line A9 of the HT27LC020. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0 from VIL to VIH, when A1=VIH. All other address lines must be held at VIH during Auto Product Identification mode. Byte 0 (A0=VIL) represents the manufacturer code, and byte 1 (A0=VIH), the device code. For HT27LC020, these two identifier bytes are given in the Mode Select Table. All identifiers for the manufacturer and device codes will possess odd parity, with the MSB (DQ7) defined as the parity bit. When A1=VIL, the HT27LC020 will read out the binary code of 7F, continuation code, to signify the unavailability of manufacturer ID codes. Program inhibit Mode Programming of multiple HT27LC020 in parallel with different data is also easily accomplished by using the Program Inhibit Mode. Except for CE, all like inputs of the parallel HT27LC020 may be common. A TTL low-level program pulse applied to an HT27LC020 CE input with VPP= Rev. 1.50 5 December 8, 2003 HT27LC020 Read Mode It is recommended that CE be decoded and used as the primary device-selection function, while OE be made a common connection to the READ line from the system control bus. This assures that all deselected memory devices are in their low-power standby mode and that the output pins are only active when data is desired from a particular memory device. The HT27LC020 has two control functions, both of which must be logically satisfied in order to obtain data at outputs. Chip Enable (CE) is the power control and should be used for device selection. Output Enable (OE) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that addresses are stable, address access time (tACC) is equal to the delay from CE to output (tCE). Data is available at the outputs (tOE) after the falling edge of OE, assuming the CE has been LOW and addresses have been stable for at least tACC-tOE. System Considerations During the switch between active and standby conditions, transient current peaks are produced on the rising and falling edges of Chip Enable. The magnitude of these transient current peaks is dependent on the output capacitance loading of the device. At a minimum, a 0.1mF ceramic capacitor (high frequency, low inherent inductance) should be used on each device between VCC and VPP to minimize transient effects. In addition, to overcome the voltage drop caused by the inductive effects of the printed circuit board traces on EPROM arrays, a 4.7mF bulk electrolytic capacitor should be used between VCC and VPP for each eight devices. The location of the capacitor should be close to where the power supply is connected to the array. Standby Mode The HT27LC020 has CMOS standby mode which reduces the maximum VCC current to 10mA. It is placed in CMOS standby when CE is at V CC ±0.3V. The HT27LC020 also has a TTL-standby mode which reduces the maximum VCC current to 0.6mA. It is placed in TTL-standby when CE is at VIH. When in standby mode, the outputs are in a high-impedance state, independent of the OE input. Two-line Output Control Function To accommodate multiple memory connections, a two-line control function is provided to allow for: · Low memory power dissipation · Assurance that output bus contention will not occur A d d re s s A d d r e s s V a lid tC C E E tD tO O E tA O u tp u t H IG H F E tO C C H O u tp u t V a lid Z Figure 1. A.C. Waveforms for Read Operation Rev. 1.50 6 December 8, 2003 HT27LC020 R e a d ( V e r ify ) P ro g ra m A d d re s s V IH V V P P tA V IH D a ta V C C A d d r e s s S ta b le IL V tO S D a ta In IL tD tD S H tD 5 .0 V 1 2 .5 V 5 .0 V tP V tV C S tV P S H D a ta O u t V a lid 6 .0 V C E F P R T IH V IL tC V E S IH P G M V IL tP O E tA E V tO W E S IH V IL Figure 2. Programming Waveforms S T A R T A d d r e s s = F ir s t L o c a tio n V V C C P P = 6 .0 V = 1 2 .5 V X = 0 P ro g ra m In te r a c tiv e S e c tio n o n e 7 5 s P u ls e In c re m e n t X X = 2 5 ? Y e s N o F a il V e r ify B y te ? P a s s In c re m e n t A d d re s s L a s t A d d re s s N o F a il Y e s V V e r ify S e c tio n = V C C P P = 3 .3 V V e r ify a ll B y te s ? F a il D e v ic e F a ile d P a s s D e v ic e P a s s e d N o te : E ith e r 1 0 5 s o r 3 0 s p u ls e . Figure 3. Fast Programming Flowchart Rev. 1.50 7 December 8, 2003 HT27LC020 Package Information 32-pin DIP (600mil) Outline Dimensions A 1 7 3 2 B 1 6 1 H C D E Symbol A Rev. 1.50 F = G I Dimensions in mil Min. Nom. Max. 1635 ¾ 1665 B 535 ¾ 555 C 145 ¾ 155 D 125 ¾ 145 E 16 ¾ 20 70 F 50 ¾ G ¾ 100 ¾ H 595 ¾ 615 I 635 ¾ 670 a 0° ¾ 15° 8 December 8, 2003 HT27LC020 32-pin SOP (450mil) Outline Dimensions 3 2 1 7 A B 1 1 6 C C ' G H D E Symbol Rev. 1.50 = F Dimensions in mil Min. Nom. Max. A 543 ¾ 557 B 440 ¾ 450 C 14 ¾ 20 C¢ ¾ ¾ 817 D 100 ¾ 112 E ¾ 50 ¾ F 4 ¾ ¾ G 32 ¾ 38 H 4 ¾ 12 a 0° ¾ 10° 9 December 8, 2003 HT27LC020 32-pin TSOP (8´20) Outline Dimensions H D 1 3 2 E G 0 .0 1 0 L D e ta il F 1 6 1 7 D A 2 S e e D e ta il F L 1 S b S e a tin g P la n e Symbol Rev. 1.50 y e A A 1 Dimensions in mm Min. Nom. Max. A ¾ ¾ 1.20 A1 0.05 ¾ 0.15 A2 0.95 ¾ 1.05 b ¾ 0.22 ¾ D 18.30 ¾ 18.50 HD 19.80 ¾ 20.20 E 7.90 ¾ 8.10 e ¾ 0.50 ¾ L ¾ 0.60 ¾ L1 ¾ 0.80 ¾ q 0° ¾ 5° 10 December 8, 2003 HT27LC020 32-pin PLCC Outline Dimensions A B 4 1 3 2 3 0 5 2 9 D 1 3 C 2 1 1 4 2 0 K E J H F G I Symbol A Rev. 1.50 Dimensions in mil Min. Nom. Max. 485 ¾ 495 B 445 ¾ 455 C 585 ¾ 595 D 545 ¾ 555 E 105 ¾ 115 F ¾ ¾ 140 G 15 ¾ ¾ H ¾ 50 ¾ I 16 ¾ 22 J 24 ¾ 32 K 8 ¾ 12 a 0° ¾ 10° 11 December 8, 2003 HT27LC020 Product Tape and Reel Specifications Reel Dimensions D T 2 A C B T 1 SOP 32W Symbol Description Dimensions in mm A Reel Outer Diameter 330±1.0 B Reel Inner Diameter 100±0.1 C Spindle Hole Diameter 13.0+0.5 -0.2 D Key Slit Width 2.0±0.5 T1 Space Between Flange 32.8+0.3 -0.2 T2 Reel Thickness 38.2+0.2 PLCC 32 Symbol Description Dimensions in mm A Reel Outer Diameter 330±1.0 B Reel Inner Diameter 62±1.5 C Spindle Hole Diameter 13.0+0.5 -0.2 D Key Slit Width 2.0±0.5 T1 Space Between Flange 24.8+0.3 -0.2 T2 Reel Thickness 30.2±0.2 Rev. 1.50 12 December 8, 2003 HT27LC020 Carrier Tape Dimensions P 0 D P 1 t E F W D 1 C B 0 K 1 P K 2 A 0 SOP 32W Symbol Description Dimensions in mm W Carrier Tape Width 32.0+0.3 -0.1 P Cavity Pitch 16.0±0.1 E Perforation Position 1.75±0.1 F Cavity to Perforation (Width Direction) 14.2±0.1 D Perforation Diameter 1.55+0.1 D1 Cavity Hole Diameter 2.0+0.25 P0 Perforation Pitch 4.0±0.1 P1 Cavity to Perforation (Length Direction) 2.0±0.1 A0 Cavity Length 14.7±0.1 B0 Cavity Width 20.9±0.1 K1 Cavity Depth 3.0±0.1 K2 Cavity Depth 3.4±0.1 t Carrier Tape Thickness C Cover Tape Width Rev. 1.50 0.35±0.05 25.5 13 December 8, 2003 HT27LC020 P 0 D P 1 t E F W C D 1 B 0 P K 0 A 0 PLCC 32 Symbol Description Dimensions in mm W Carrier Tape Width 24.0±0.3 P Cavity Pitch 18.0±0.1 E Perforation Position 1.75±0.1 F Cavity to Perforation (Width Direction) 11.5±0.1 D Perforation Diameter 1.5+0.1 D1 Cavity Hole Diameter 1.55+1.0 -0.05 P0 Perforation Pitch 4.0±0.1 P1 Cavity to Perforation (Length Direction) 2.0±0.1 A0 Cavity Length 13.1±0.1 B0 Cavity Width 15.5±0.1 K0 Cavity Depth 3.9±0.1 t Carrier Tape Thickness C Cover Tape Width Rev. 1.50 0.30±0.05 21.3 14 December 8, 2003 HT27LC020 Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233 Tel: 021-6485-5560 Fax: 021-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 43F, SEG Plaza, Shen Nan Zhong Road, Shenzhen, China 518031 Tel: 0755-8346-5589 Fax: 0755-8346-5590 ISDN: 0755-8346-5591 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 010-6641-0030, 6641-7751, 6641-7752 Fax: 010-6641-0125 Holmate Semiconductor, Inc. (North America Sales Office) 46712 Fremont Blvd., Fremont, CA 94538 Tel: 510-252-9880 Fax: 510-252-9885 http://www.holmate.com Copyright Ó 2003 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.50 15 December 8, 2003