HV528 16-Channel Serial to Parallel Converter with High Voltage Backplane Driver and Push-Pull Outputs Features General Description ► ► ► ► ► ► The HV528 is a 200V, 16-channel serial to parallel converter. The high voltage outputs and the backplane driver are designed to source and sink ±1.0mA. HVCMOS® technology Output voltage up to +200V Shift register speed 500kHz @ VDD = 1.7V 16 high voltage outputs High voltage backplane driver CMOS input levels The high voltage outputs are controlled by a 16-bit serial shift register, followed by a 16-bit latch. Data is shifted through the shift registers during the low to high clock transition. A data output buffer is provided for cascading multiple devices. Data is transferred to the 16-bit latch when a logic level low is applied to the LE input. Data is stored in the latch when LE is high. Output states are controlled by the data in the latch and by the POL pin. Applications ► Multiple segment EL display ► Piezoelectric transducer driver ► Braille driver Typical Application Circuit Low Voltage Power Supply High Voltage VBIAS Power Supply HVOUT1 DIN CLK Micro Processor High Voltage Low Voltage 16 LE POL DOUT Shift Register Latches Level Translators & Push-Pull Output EL Segment Panel HVOUT16 BP Supertex HV528 to DIN of another HV528 for cascading (if needed) ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com HV528 Ordering Information Pin Configuration Package Option Device 32 32-Lead QFN 5.00x5.00mm body 1.00mm height (max) 0.50mm pitch HV528 1 HV528K6-G -G indicates package is RoHS compliant (‘Green’) 32-Lead QFN (K6) Absolute Maximum Ratings Parameter (top view) (Bottom side exposed center pad is at VPP potential) Value Logic supply, VDD -0.5V to 7.0V High voltage supply, VPP 215V Translator supply voltage, VBIAS Product Marking -0.5V to 7.0V Logic input levels -0.5V to VDD +0.5V Operating junction temperature -40°C to +125°C Storage temperature range -65°C to +150°C L = Lot Number YY = Year Sealed WW = Week Sealed A = Assembler ID C = Country of Origin = “Green” Packaging HV528 LLLLLL YYWW AAACCC Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. 32-Lead QFN (K6) Operating Supply Voltages and Conditions Sym Parameter Min Typ Max Units VDD Logic supply voltage 1.7 3.0 5.5 V --- VBIAS Level translator supply voltage 5.4 - 6.6 V --- VPP Positive high voltage supply 50 - 200 V --- VIH High-level input voltage 0.9VDD - VDD V --- VIL Low-level input voltage 0 - V --- TA Operating temperature 0 - °C --- +70 Conditions Notes: 1. External ground noise reduction circuit will be provided by design upon characterization. Power-up sequence should be the following*: 1. Apply ground 2. Apply VDD 3. Set all inputs (DIN, CLK, LE , POL) to a known state 4. Apply VBIAS 5. Apply VPP Power-down sequence should be the reverse of the above * This power up sequence requires an external high voltage diode between VDD and VPP. Without the diode, power up VPP to a VDD level first to bias the silicon substrate. After all other signals are powered, finish raising the VPP to its final level. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com 2 HV528 DC Electrical Characteristics Sym Parameter (Over operating supply voltages and temperature, unless otherwise noted) Min Typ Max Units Conditions IDD VDD supply current - - 1.0 mA fCLK = 500kHz IDDQ Quiescent VDD supply current - - 10 µA All logic inputs = VDD or 0V IBIAS VBIAS supply current - - 100 µA All HVOUTS switching at 1.0kHz. Peak IBIAS = 200mA with all channels switching IBIASQ Quiescent VBIAS current - - 10 µA No HVOUT switching IPPQ Quiescent VPP supply current - - 100 µA VPP = 200V, outputs are static IIH High-level logic input current - - 10 µA VIH = VDD IIL Low-level logic input current - - -10 µA VIL = 0V VPP -30V - - V IHVOUT = -1.0mA, 50V ≤ VPP ≤ 100V VPP -16V - - V IHVOUT = -1.0mA, 100V < VPP ≤ 200V VDD -1.0V - - V IDOUT = -1.0mA HVOUT & BP - - 6.0 V IHVOUT = 1.0mA VOH High level output HVOUT & BP DOUT VOL Low level output DOUT - - 1.0 V IDOUT = 1.0mA CDIN Logic input capacitance - - 10 pF --- Logic output capacitance - - 10 pF --- CDOUT AC Electrical Characteristics (Over operating supply voltages and temperature, unless otherwise noted) Sym fCLK Parameter Clock frequency Min Typ Max Units Conditions 0 - 500 kHz --- tC Clock high / low pulse width 1.0 - - µs --- tSU Data setup time before clock rises 50 - - ns --- tH Data hold time after clock rises 50 - - ns --- tCLE LE from CLK setup time 15 - - ns --- tWLE LE pulse width 100 - - ns --- tDD Clock negative edge to DOUT delay - - 150 ns CLDOUT = 50pF, (CLDOUT includes CDIN and CDOUT) tPHV Delay time from inputs for HVOUT / BP to start rise/fall - - 500 ns VPP = 200V, VBIAS = 5.4V tOR HVOUTPUT / BP rise time - - 300 µs CL = 1500pF, VPP = 200V tOF HVOUTPUT / BP fall time - - 300 µs CL = 1500pF, VBIAS = 5.4V, VPP = 200V tOC Width of POL pulses tPHV + tOR/tOF - - µs --- ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com 3 HV528 Input and Output Equivalent Circuits VDD VPP VDD Input Data Out HVOUT VBIAS GND GND Logic Inputs HVGND High Voltage Outputs Logic Data Output VBIAS SUPPLY The VBIAS supply operates from 5.4 to 6.6V. It is the gate drive voltage for all of the output N-channel MOSFETs. This allows the output peak current sink to be set by varying the VBIAS voltage. A higher VBIAS voltage will increase the current sinking capability. The operating VDD range is 1.7 to 5.5V. A plot showing the typical characteristics of ISINK vs VBIAS is shown below. Typical HVOUT ISINK vs VBIAS (VPP = 200V, CLOAD = 1.0nF) 20 ISINK (mA) 18 16 14 12 10 5.0 5.5 6.0 6.5 VBIAS (V) ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com 4 HV528 Switching Waveforms ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com 5 HV528 Functional Block Diagram VDD DIN Level Translator Logic GND CLK 16-bit Shift Register HVOUT1 HVGND 16-bit Latch Level Translator Logic HVGND GND DOUT HVOUT16 HVGND GND Level Translator & Buffer LE POL BP HVGND Function Table Inputs Function Load S/R Transfer data in latch Store data in latches Transparent mode Invert mode Outputs Shift Reg 1 2...16 DIN CLK LE POL H OR L ↑ H X X L L H * *..........* X L L L * *..........* X X H H ● ●...● X X H L ● ●...● L ↑ L H L H ↑ L H X X H X X H HV Outputs 1 2...16 BP DOUT ●...● X ● * *..........* L ● * *..........* (b) H ● ● ●...● L ● ● ●...● (b) H ● ●...● L ●...● L ● H ●...● H ●...● L ● L ● ●...● ● ●...● (b) H X H ● ●...● ● ●...● L X H or L ●...● ● Notes: H = high level, L = low level, X = irrelevant, ↑ = low-to-high transition ● = dependent on previous stage’s state before the last CLK or last LE low * = data at the last CLK ↑ (b) = bar over all symbols ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com 6 HV528 Pin Description Pin # Function 1 HVOUT12 2 HVOUT11 3 HVOUT10 4 HVOUT9 5 HVOUT8 6 HVOUT7 7 HVOUT6 8 HVOUT5 9 HVOUT4 10 HVOUT3 11 HVOUT2 12 HVOUT1 13 NC No connect 14 VPP High voltage supply 15 GND Logic ground 16 NC No connect 17 DIN Data in 18 NC No connect 19 CLK Clock input logic 20 VDD Logic supply voltage 21 POL Polarity bar input logic 22 LE Latch enable bar input logic 23 NC No connect 24 DOUT 25 NC 26 VBIAS 27 HVGND 28 BP 29 HVOUT16 30 HVOUT15 31 HVOUT14 32 HVOUT13 Center Pad Description High voltage push-pull output Data out No connect Level translator bias voltage High voltage ground High voltage backplane output High voltage push-pull output The center pad is at VPP potential. Leave floating or connect to VPP. Do not ground. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com 7 HV528 32-Lead QFN Package Outline (K6) 5.00x5.00mm body, 1.00mm height (max), 0.50mm pitch D2 D 32 32 Note 1 (Index Area D/2 x E/2) 1 1 Note 1 (Index Area D/2 x E/2) e E E2 b View B Top View Bottom View Note 3 θ A A3 L Seating Plane L1 A1 Note 2 View B Side View Notes: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 Identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. 2. Depending on the method of manufacturing, a maximum of 0.15mm pullback (L1) may be present. 3. The inner tip of the lead may be either rounded or square. Symbol Dimension (mm) A A1 MIN 0.80 0.00 NOM 0.90 0.02 MAX 1.00 0.05 A3 0.20 REF b D D2 E E2 0.18 4.85* 1.05 4.85* 1.05 0.25 5.00 - 5.00 - 0.30 5.15* 3.55† 5.15* 3.55† e 0.50 BSC L L1 θ 0.30† 0.00 0O 0.40† - - 0.50† 0.15 14O JEDEC Registration MO-220, Variation VHHD-6, Issue K, June 2006. * This dimension is not specified in the original JEDEC drawing. The value listed is for reference only. † This dimension is a non-JEDEC dimension. Drawings not to scale. Supertex Doc. #: DSPD-32QFNK65X5P050, Version B090808. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www. supertex.com/packaging.html.) Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. website: http//www.supertex.com. ©2008 All rights reserved. Unauthorized use or reproduction is prohibited. Doc.# DSFP-HV528 A091908 8 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com