SUTEX HV5530 32-channel serial to parallel converter with open drain output Datasheet

HV5522/HV5530
HV5622/HV5630
32-Channel Serial To Parallel Converter
With Open Drain Outputs
Ordering Information
Package Options
Device
Recommended
Operating VPP max
44 J-Lead Quad
Ceramic Chip Carrier
44 J-Lead Quad
Plastic Chip Carrier
44 Lead Quad
Plastic Gullwing
Die
HV5522
220V
HV5522DJ
HV5522PJ
HV5522PG
HV5522X
HV5530
300V
HV5530DJ
HV5530PJ
HV5530PG
HV5530X
HV5622
220V
HV5622DJ
HV5622PJ
HV5622PG
HV5622X
HV5630
300V
HV5630DJ
HV5630PJ
HV5630PG
HV5630X
Features
General Description
❏ Processed with HVCMOS® technology
The HV55 and HV56 are low-voltage serial to high-voltage
parallel converters with open drain outputs. These devices have
been designed for use as drivers for AC-electroluminescent
displays. They can also be used in any application requiring
multiple output high voltage current sinking capabilities such as
driving inkjet and electrostatic print heads, plasma panels, vacuum
fluorescent, or large matrix LCD displays.
❏ Sink current minimum 100mA
❏ Shift register speed 8MHz
❏ Polarity and Blanking inputs
❏ CMOS compatible inputs
❏ Forward and reverse shifting options
❏ Diode to VPP allows efficient power recovery
❏ 44-lead ceramic surface mount package
❏ Hi-Rel processing available
Absolute Maximum Ratings
Supply voltage, VDD1
Output voltage,
Logic input
Ground
VPP1
-0.5V to +15V
HV5530/HV5630
-0.5V to +315V
HV5522/HV5622
-0.5V to +230V
levels1
-0.5V to VDD + 0.5V
current2
Continuous total power
These devices consist of a 32-bit shift register, 32 latches, and
control logic to perform the polarity select and blanking of the
outputs. Data is shifted through the shift register on the high to low
transition of the clock. The HV55 shifts in the counterclockwise
direction when viewed from the top of the package, and the HV56
shifts in the clockwise direction. A data output buffer is provided
for cascading devices. This output reflects the current status of
the last bit of the shift register. Operation of the shift register is not
affected by the LE (latch enable), BL (blanking), or the POL
(polarity) inputs. Transfer of data from the shift register to the latch
occurs when the LE (latch enable) input is high. The data in the
latch is stored when LE is low.
1.5A
dissipation3
Operating temperature range
Storage temperature range
Lead temperature 1.6mm (1/16 inch)
from case for 10 seconds
Ceramic
Plastic
1500mW
1200mW
Ceramic -55°C to +125°C
Plastic -40°C to +85°C
-65°C to +150°C
260°C
Notes:
1. All voltages are referenced to VSS.
2. Duty cycle is limited by the total power dissipated in the package.
3. For operation above 25°C ambient derate linearly to maximum operating
temperature at 20°C for plastic and at 15mW/°C for ceramic.
12/13/01
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to
1
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications
are subject to change without notice. For the latest product specifications, refer to the
Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
HV5522/HV5530/HV5622/HV5630
Electrical Characteristics (over recommended operating conditions unless noted)
DC Characteristics
Symbol
Parameter
IDD
VDD supply current
IDDQ
Quiescent VDD supply current
IO(OFF)
Off state output current
IIH
Min
Max
Units
Conditions
15
mA
fCLK = 8MHz
FDATA = 4MHz
100
µA
VIN = 0V
10
µA
All outputs high
All SWS parallel
High-level logic input current
1
µA
VIH = VDD
IIL
Low-level logic input current
-1
µA
VIL = 0V
VOH
High-level output data out
V
IDout = -100µA
VOL
Low-level output voltage
15.0
V
IHVout = +100mA
1.0
V
IDout = +100µA
VOC
HVOUT clamp voltage
-1.5
V
IOL = -100mA
VDD - 1.0V
HVOUT
Data out
AC Characteristics (VDD = 12V, TC = 25°C)
Symbol
Parameter
Min
Max
Units
8
MHz
Conditions
fCLK
Clock frequency
tW
Clock width high or low
62
ns
tSU
Data set-up time before clock falls
25
ns
tH
Data hold time after clock falls
10
ns
tON
Turn on time, HVOUT from enable
500
ns
RL = 2KΩ to VPP MAX
tDHL
Delay time clock to data high to low
100
ns
CL = 15pF
tDLH
Delay time clock to data low to high
100
ns
CL = 15pF
tDLE
Delay time clock to LE low to high
50
ns
tWLE
Width of LE pulse
50
ns
tSLE
LE set-up time before clock falls
50
ns
Recommended Operating Conditions
Symbol
Parameter
VDD
Logic supply voltage
HVOUT
High voltage output
VIH
High-level input voltage
VIL
Low-level input voltage
fCLK
Clock frequency
TA
Operating free-air temperature
Min
Max
Units
10.8
13.2
V
HV5530 and HV5630
-0.3
+300
V
HV5522 and HV5622
-0.3
+220
V
VDD - 2V
VDD
V
2.0
V
0
8
MHz
Plastic
-40
+85
°C
Ceramic
-55
+125
°C
Note:
Power-up sequence should be the following:
1. Connect ground.
2. Apply VDD.
3. Set all inputs to a known state.
Power-down sequence should be the reverse of the above.
2
HV5522/HV5530/HV5622/HV5630
Input and Output Equivalent Circuits
VDD
VDD
HVOUT
Data Out
Input
HVIN
VSS
VSS
VSS
Logic Data Output
Logic Inputs
High Voltage Outputs
Switching Waveforms
VIH
Data Input
50%
Data Valid
50%
VIL
tSU
tH
VIH
Clock
50%
50%
50%
tWH
50%
VIL
tWL
VOH
50%
VOL
tDLH
Data Out
VOH
50%
VOL
tDHL
Latch Enable
VIH
50%
50%
VIL
tDLE
tWLE
tSLE
VOH
HVOUT
w/ S/R HIGH
10%
tON
3
VOL
HV5522/HV5530/HV5622/HV5630
Functional Block Diagram
Polarity
Blanking
Latch Enable
HVOUT1
Data Input
Latch
HVOUT2
Clock
Latch
32-Bit
Shift
Register
(Outputs 3 to 30
not shown)
HVOUT31
Latch
HVOUT32
Data Out
Latch
Function Table
Inputs
Function
Shift Reg
1 2…32
Outputs
HV Outputs
1
2…32
Data Out
*
Data
CLK
LE
BL
POL
All on
X
X
X
L
L
*
*…*
On
On…On
*
All off
X
X
X
L
H
*
*…*
Off
Off…Off
*
Invert mode
X
X
L
H
L
*
*…*
*
*…*
*
H or L
↓
L
H
H
H or L *…*
*
*…*
*
X
H or L
↑
H
H
*
*…*
*
*…*
*
X
H or L
↑
H
L
*
*…*
*
*…*
*
L
↓
H
H
H
L
*…*
Off
*…*
*
H
↓
H
H
H
H
*…*
On
*…*
*
Load S/R
Load
Latches
Transparent
Latch mode
Notes:
H = high level, L = low level, X = irrelevant, ↓ = high-to-low transition, ↑ = low-to-high transistion.
* = dependent on previous stage’s state before the last CLK ↓ or last LE high.
4
HV5522/HV5530/HV5622/HV5630
Pin Configurations
Package Outline
HV55
44 Pin J-Lead Package
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Function
HVOUT 16
HVOUT 17
HVOUT 18
HVOUT 19
HVOUT 20
HVOUT 21
HVOUT 22
HVOUT 23
HVOUT 24
HVOUT 25
HVOUT 26
HVOUT 27
HVOUT 28
HVOUT 29
HVOUT 30
HVOUT 31
HVOUT 32
Data Out
N/C
N/C
N/C
Polarity
Pin
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Function
Clock
VSS
VDD
Latch Enable
Data In
Blanking
N/C
HVOUT 1
HVOUT 2
HVOUT 3
HVOUT 4
HVOUT 5
HVOUT 6
HVOUT 7
HVOUT 8
HVOUT 9
HVOUT 10
HVOUT 11
HVOUT 12
HVOUT 13
HVOUT 14
HVOUT 15
Pin
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Function
Clock
VSS
VDD
Latch Enable
Data In
Blanking
N/C
HVOUT 32
HVOUT 31
HVOUT 30
HVOUT 29
HVOUT 28
HVOUT 27
HVOUT 26
HVOUT 25
HVOUT 24
HVOUT 23
HVOUT 22
HVOUT 21
HVOUT 20
HVOUT 19
HVOUT 18
39 38 37 36 35 34 33 32 31 30 29
Function
HVOUT 17
HVOUT 16
HVOUT 15
HVOUT 14
HVOUT 13
HVOUT 12
HVOUT 11
HVOUT 10
HVOUT 9
HVOUT 8
HVOUT 7
HVOUT 6
HVOUT 5
HVOUT 4
HVOUT 3
HVOUT 2
HVOUT 1
Data Out
N/C
N/C
N/C
Polarity
28
41
27
42
26
43
25
44
24
1
23
2
22
3
21
4
20
5
19
6
18
7
8
9 10 11 12 13 14 15 16 17
top view
44-pin J-Lead Package
HV56
44 Pin J-Lead Package
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
40
5
HV5522/HV5530/HV5622/HV5630
Pin Configurations
Package Outline
HV55
44-Pin Quad Plastic Gullwing Package
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Function
HVOUT 11
HVOUT 12
HVOUT 13
HVOUT 14
HVOUT 15
HVOUT 16
HVOUT 17
HVOUT 18
HVOUT 19
HVOUT 20
HVOUT 21
HVOUT 22
HVOUT 23
HVOUT 24
HVOUT 25
HVOUT 26
HVOUT 27
HVOUT 28
HVOUT 29
HVOUT 30
HVOUT 31
HVOUT 32
Pin
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Function
Data Out
N/C
N/C
N/C
Polarity
Clock
VSS
VDD
Latch Enable
Data In
Blanking
N/C
HVOUT 1
HVOUT 2
HVOUT 3
HVOUT 4
HVOUT 5
HVOUT 6
HVOUT 7
HVOUT 8
HVOUT 9
HVOUT 10
44 43 42 41 40 39 38 37 36 35 34
1
33
2
32
3
31
4
30
5
29
6
28
7
27
8
26
9
25
10
24
11
23
12 13 14 15 16 17 18 19 20 21 22
top view
44-pin Quad Plastic Gullwing Package
HV56
44-Pin Quad Plastic Gullwing Package
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Function
HVOUT 22
HVOUT 21
HVOUT 20
HVOUT 19
HVOUT 18
HVOUT 17
HVOUT 16
HVOUT 15
HVOUT 14
HVOUT 13
HVOUT 12
HVOUT 11
HVOUT 10
HVOUT 9
HVOUT 8
HVOUT 7
HVOUT 6
HVOUT 5
HVOUT 4
HVOUT 3
HVOUT 2
HVOUT 1
Pin
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Function
Data Out
N/C
N/C
N/C
Polarity
Clock
VSS
VDD
Latch Enable
Data In
Blanking
N/C
HVOUT 32
HVOUT 31
HVOUT 30
HVOUT 29
HVOUT 28
HVOUT 27
HVOUT 26
HVOUT 25
HVOUT 24
HVOUT 23
12/13/01
©2001 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.
6
1235 Bordeaux Drive, Sunnyvale, CA 94089
TEL: (408) 744-0100 • FAX: (408) 222-4895
www.supertex.com
Package Outline
44-Lead PLCC Package Outline (PJ)
.653x.653in body, .180in height (max.), .050in pitch
D
D1
1 44
.048/.042
x 45O
6
.150 MAX
.056/.042
x 45O
40
Note 1
(Index Area)
.075 MAX
E1
E
Note 2
(3 places)
0.20max
3 Places
Top View
Side View
View B
b1
A
Base
Plane
A2
.020 MIN
Seating
Plane
e
A1
b
Side View
View B
Note:
1. A Pin 1 identifier must be located in the index area indicated.The Pin 1 identifier may be either a mold, or an embedded metal or marked feature.
2. Exact shape of this feature is optional.
Symbol
Dimension
(inches)
A
A1
A2
b
b1
D
D1
E
E1
MIN
.165
.090
.062
.013
.026
.685
.650
.685
.650
NOM
.172
.105
-
-
-
.690
.653
.690
.653
MAX
.180
.120
.083
.021
.036
.695
.656
.695
.656
JEDEC Registration MS-018, Variation AC, Issue A, June, 1993.
Drawings are not to scale.
Doc. #: DSPD-44PLCCPJ
B051607
e
.050
BSC
Package Outline
44-Lead PQFP Package Outline (PG)
D
D1
E
E1
Note 1
(Index Area
D1/4 x E1/4)
L2
Gauge
Plane
48
L
1
θ
L1
b
Seating
Plane
e
Top View
View B
View B
A
A2
Seating
Plane
A1
Side View
Note 1:
A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier may be either a mold, or an embedded metal or marked feature.
Symbol
MIN
Dimension
(mm)
NOM
MAX
A
A1
A2
b
D
D1
E
E1
-
0.25
1.95
0.30
13.65
9.80
13.65
9.80
2.45
-
2.00
2.10
0.45
13.90
14.15
JEDEC Registration M0-112, Variation AA-2, Issue B, Sep.1995.
Doc. #: DSPD-44PQFPPG
A031607
10.00
10.20
13.90
14.15
10.00
10.20
e
L
L1
L2
0.73
0.80
BSC
0.88
1.03
1.95
REF
0.25
BSC
θ
θ1
3.5O
5O
-
-
O
7
16O
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