Hynix HY57V281620HCT-S 4 banks x 2m x 16bits synchronous dram Datasheet

HY57V281620HC(L)T
4 Banks x 2M x 16bits Synchronous DRAM
DESCRIPTION
The Hynix HY57V281620HC(L)T is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the main memory applications
which require large memory density and high bandwidth. HY57V281620HC(L)T is organized as 4banks of 2,097,152x16
HY57V281620HC(L)T is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and
output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated
by a single control command (Burst length of 1,2,4,8, or full page), and the burst count sequence(sequential or interleave). A burst of
read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst
read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
FEATURES
•
Single 3.3±0.3V power supply
•
Auto refresh and self refresh
•
All device pins are compatible with LVTTL interface
•
4096 refresh cycles / 64ms
•
JEDEC standard 400mil 54pin TSOP-II with 0.8mm
of pin pitch
•
Programmable Burst Length and Burst Type
•
All inputs and outputs referenced to positive edge of
system clock
- 1, 2, 4, 8 or Full page for Sequential Burst
•
Data mask function by UDQM or LDQM
•
Internal four banks operation
- 1, 2, 4 or 8 for Interleave Burst
•
Programmable CAS Latency ; 2, 3 Clocks
ORDERING INFORMATION
Part No.
Clock Frequency
HY57V281620HCT-6
166MHz
HY57V281620HCT-7
143MHz
HY57V281620HCT-K
133MHz
HY57V281620HCT-H
133MHz
HY57V281620HCT-8
125MHz
HY57V281620HCT-P
100MHz
HY57V281620HCT-S
100MHz
HY57V281620HCLT-6
166MHz
HY57V281620HCLT-7
143MHz
HY57V281620HCLT-K
133MHz
HY57V281620HCLT-H
133MHz
HY57V281620HCLT-8
125MHz
HY57V281620HCLT-P
100MHz
HY57V281620HCLT-S
100MHz
Power
Organization
Interface
Package
4Banks x 2Mbits
x16
LVTTL
400mil 54pin TSOP II
Normal
Low power
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of
circuits described. No patent licenses are implied.
Rev. 0.2/Aug. 01
HY57V281620HC(L)T
PIN CONFIGURATION
V DD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
V DD
LDQM
/WE
/CAS
/RAS
/CS
BA0
BA1
A10/AP
A0
A1
A2
A3
V DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54pin TSOP II
400mil x 875mil
0.8mm pin pitch
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V SS
DQ15
V SSQ
DQ14
DQ13
V DDQ
DQ12
DQ11
V SSQ
DQ10
DQ9
V DDQ
DQ8
V SS
NC
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
V SS
PIN DESCRIPTION
PIN
PIN NAME
DESCRIPTION
CLK
Clock
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
CKE
Clock Enable
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
CS
Chip Select
Enables or disables all inputs except CLK, CKE, UDQM and LDQM
BA0, BA1
Bank Address
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
A0 ~ A11
Address
Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA8
Auto-precharge flag : A10
RAS, CAS, WE
Row Address Strobe, Column Address Strobe, Write
Enable
RAS, CAS and WE define the operation
Refer function truth table for details
UDQM, LDQM
Data Input/Output Mask
Controls output buffers in read mode and masks input data in write mode
DQ0 ~ DQ15
Data Input/Output
Multiplexed data input / output pin
V DD /VSS
Power Supply/Ground
Power supply for internal circuits and input buffers
V DDQ /VSSQ
Data Output Power/Ground
Power supply for output buffers
NC
No Connection
No connection
Rev. 0.2/Aug. 01
3
HY57V281620HC(L)T
FUNCTIONAL BLOCK DIAGRAM
2Mbit x 4banks x 16 I/O Synchronous DRAM
Self refresh logic
& timer
Internal Row
counter
2Mx16 Bank 3
CLK
Row active
Row
Pre
Decoders
2Mx16 Bank 2
CS
Column
Active
Column
Pre
Decoders
UDQM
LDQM
A0
A1
Rev. 0.2/Aug. 01
DQ14
Column Add
Counter
Address
Registers
Address buffers
A11
BA0
BA1
DQ1
DQ15
Y decoders
Bank Select
DQ0
I/O Buffer & Logic
WE
Memory
Cell
Array
Sense AMP & I/O Gate
refresh
2Mx16 Bank 0
X decoders
CAS
State Machine
RAS
2Mx16 Bank 1
X decoders
X decoders
X decoders
CKE
Burst
Counter
Mode Registers
CAS Latency
Data Out Control
Pipe Line Control
4
HY57V281620HC(L)T
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Unit
Ambient Temperature
TA
0 ~ 70
°C
Storage Temperature
TSTG
-55 ~ 125
°C
Voltage on Any Pin relative to V S S
V IN, VOUT
-1.0 ~ 4.6
V
Voltage on V DD relative to VSS
V DD, V DDQ
-1.0 ~ 4.6
V
Short Circuit Output Current
IO S
50
mA
Power Dissipation
PD
1
W
Soldering Temperature ⋅ Time
TSOLDER
260 ⋅ 10
°C ⋅ Sec
Note : Operation at above absolute maximum rating can adversely affect device reliability.
DC OPERATING CONDITION (T A=0 to 70°C )
Parameter
Symbol
Min
Typ
Max
Unit
Note
Power Supply Voltage
V DD , VDDQ
3.0
3.3
3.6
V
1
Input High voltage
V IH
2.0
3.0
V DDQ + 0.3
V
1,2
Input Low voltage
V IL
-0.3
0
0.8
V
1,3
Note
Note :
1.All voltages are referenced to VSS = 0V
2.V IH(max) is acceptable 5.6V AC pulse width with <=3ns of duration.
3.V IL(min) is acceptable -2.0V AC pulse width with <=3ns of duration.
AC OPERATING TEST CONDITION (TA =0 to 70°C, VDD =3.3±0.3V, VSS=0V)
Parameter
Symbol
Value
Unit
AC Input High / Low Level Voltage
V IH / VIL
2.4/0.4
V
Input Timing Measurement Reference Level Voltage
Vtrip
1.4
V
Input Rise / Fall Time
tR / tF
1
ns
Output Timing Measurement Reference Level Voltage
Voutref
1.4
V
CL
50
pF
Output Load Capacitance for Access Time Measurement
1
Note :
1.Output load to measure access times is equivalent to two TTL gates and one capacitor (50pF). For details, refer to AC/DC output
load circuit
Rev. 0.2/Aug. 01
5
HY57V281620HC(L)T
CAPACITANCE (TA=25°C, f=1MHz)
-6/K/H
Parameter
Pin
Input capacitance
Data input / output capacitance
-8/P/S
Symbol
Unit
Min
Max
Min
Max
CLK
C I1
2.5
3.5
2.5
4.0
pF
A0 ~ A11, BA0, BA1, CKE, CS, RAS, CAS ,
WE, UDQM, LDQM
CI 2
2.5
3.8
2.5
5.0
pF
DQ0 ~ DQ15
C I/O
4.0
6.5
4.0
6.5
pF
OUTPUT LOAD CIRCUIT
Vtt=1.4V
RT=250 Ω
Output
Output
50pF
50pF
DC Output Load Circuit
AC Output Load Circuit
DC CHARACTERISTICS I (TA=0 to 70°C, VDD =3.3±0.3V)
Parameter
Symbol
Min.
Max
Unit
Note
Input Leakage Current
ILI
-1
1
uA
1
Output Leakage Current
ILO
-1
1
uA
2
Output High Voltage
V OH
2.4
-
V
IOH = -2mA
Output Low Voltage
V OL
-
0.4
V
IOL = +2mA
Note :
1.V IN = 0 to 3.6V, All other pins are not tested under V IN =0V
2.DOUT is disabled, VOUT =0 to 3.6
Rev. 0.2/Aug. 01
6
HY57V281620HC(L)T
DC CHARACTERISTICS II (TA=0 to 70°C, VDD =3.3±0.3V, VSS =0V)
Speed
Parameter
Symbol
Test Condition
-6
-7
-K
-H
-8
-P
-S
130
130
120
120
120
110
110
IDD1
Burst length=1, One bank active
tRC ≥ tRC (min), IOL =0mA
IDD2P
CKE ≤ V IL (max), tCK = 15ns
IDD2PS
CKE ≤ V IL (max), tCK =
IDD2N
CKE ≥ V IH (min), CS ≥ V IH (min), tCK = 15ns
Input signals are changed one time during
30ns. All other pins ≥ V DD -0.2V or ≤ 0.2V
15
IDD2NS
CKE ≥ V IH (min), tCK = ∞
Input signals are stable.
15
IDD3P
CKE ≤ V IL (max), tCK = 15ns
5
IDD3PS
CKE ≤ V IL (max), tCK =
IDD3N
CKE ≥ V IH (min), CS ≥ V IH (min), tCK = 15ns
Input signals are changed one time during
30ns. All other pins ≥ V DD -0.2V or ≤ 0.2V
30
IDD3NS
CKE ≥ V IH (min), tCK = ∞
Input signals are stable.
20
Burst Mode Operating
Current
IDD4
tCK ≥ tCK(min), IOL=0mA
All banks active
Auto Refresh Current
IDD5
tRRC ≥ tRRC (min), All banks active
Self Refresh Current
IDD6
CKE ≤ 0.2V
Operating Current
Precharge Standby Current
in Power Down Mode
Precharge Standby Current
in Non Power Down Mode
Active Standby Current
in Power Down Mode
Active Standby Current
in Non Power Down Mode
Unit
Note
mA
1
2
mA
∞
1
mA
mA
∞
5
mA
CL=3
150
140
130
130
130
110
110
CL=2
160
140
140
140
140
120
120
240
240
220
220
200
200
200
mA
1
mA
2
2
mA
3
800
uA
4
Note :
1.IDD1 and I DD4 depend on output loading and cycle rates. Specified values are measured with the output open
2.Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II
3.HY57V281620HCT-6/K/H/8/P/S
4.HY57V281620HCLT-6/K/H/8/P/S
Rev. 0.2/Aug. 01
7
HY57V281620HC(L)T
AC CHARACTERISTICS I
(AC operating conditions unless otherwise noted)
-6
Parameter
CAS Latency = 3
-K
-H
tCK3
Max
6
Min
Max
Min
Max
Min
7
1000
7.5
1000
7.5
1000
-P
-S
Max
Min
8
1000
10
7.5
Max
10
Min
Max
10
1000
10
Min
10
1000
10
Note
Max
ns
1000
tCK2
10
Clock High Pulse Width
tCHW
2.5
-
2.5
-
2.5
-
2.5
-
3
-
3
-
3
-
ns
1
Clock Low Pulse Width
tCLW
2.5
-
2.5
-
2.5
-
2.5
-
3
-
3
-
3
-
ns
1
CAS Latency = 3
tAC3
-
5.4
-
5.4
-
5.4
-
5.4
-
6
-
6
-
6
ns
CAS Latency = 2
tAC2
-
6
-
6
-
5.4
-
6
-
6
-
6
-
6
ns
Access Time
From Clock
CAS Latency = 2
-8
Unit
Min
System Clock
Cycle Time
-7
Symbol
12
ns
2
Data-Out Hold Time
tOH
2.7
-
2.7
-
2.7
-
2.7
-
3
-
3
-
3
-
ns
Data-Input Setup Time
tDS
1.5
-
1.5
-
1.5
-
1.5
-
2
-
2
-
2
-
ns
1
Data-Input Hold Time
tDH
0.8
-
0.8
-
0.8
-
0.8
-
1
-
1
-
1
-
ns
1
Address Setup Time
tAS
1.5
-
1.5
-
1.5
-
1.5
-
2
-
2
-
2
-
ns
1
Address Hold Time
tAH
0.8
-
0.8
-
0.8
-
0.8
-
1
-
1
-
1
-
ns
1
CKE Setup Time
tCKS
1.5
-
1.5
-
1.5
-
1.5
-
2
-
2
-
2
-
ns
1
CKE Hold Time
tCKH
0.8
-
0.8
-
0.8
-
0.8
-
1
-
1
-
1
-
ns
1
Command Setup Time
tCS
1.5
-
1.5
-
1.5
-
1.5
-
2
-
2
-
2
-
ns
1
Command Hold Time
tCH
0.8
-
0.8
-
0.8
-
0.8
-
1
-
1
-
1
-
ns
1
CLK to Data Output in Low-Z Time
tOLZ
1
-
1
-
1
-
1
-
1
-
1
-
1
-
ns
CLK to Data
Output in High-Z
Time
CAS Latency = 3
tOHZ3
2.7
5.4
2.7
5.4
2.7
5.4
2.7
5.4
3
6
3
6
3
6
ns
CAS Latency = 2
tOHZ2
2.7
5.4
2.7
5.4
2.7
5.4
3
6
3
6
3
6
3
6
ns
Note :
1.Assume tR / tF (input rise and fall time ) is 1ns
If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter
2.Access times to be measured with input signals of 1v/ns edge rate, from 0.8v to 2.0v
If tR > 1ns, then (tR/2-0.5)ns should be added to the parameter
Rev. 0.2/Aug. 01
8
HY57V281620HC(L)T
AC CHARACTERISTICS II
-6
Parameter
-7
-K
-H
-8
-P
-S
Symbol
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Operation
tRC
60
-
60
-
60
-
65
-
68
-
70
-
70
-
ns
Auto Refresh
tRRC
60
-
65
-
65
-
65
-
68
-
70
-
70
-
ns
RAS to CAS Delay
tRCD
18
-
20
-
15
-
20
-
20
-
20
-
20
-
ns
RAS Active Time
tRAS
42
100K
45
100K
45
100K
45
100K
48
100K
50
100K
50
100K
ns
RAS Precharge Time
tRP
18
-
20
-
15
-
20
-
20
-
20
-
20
-
ns
RAS to RAS Bank Active Delay
tRRD
12
-
14
-
15
-
15
-
16
-
20
-
20
-
ns
CAS to CAS Delay
tCCD
1
-
1
-
1
-
1
-
1
-
1
-
1
-
CLK
Write Command to Data-In Delay
tWTL
0
-
0
-
0
-
0
-
0
-
0
-
0
-
CLK
Data-In to Precharge Command
tDPL
2
-
2
-
2
-
2
-
1
-
1
-
1
-
CLK
Data-In to Active Command
tDAL
5
-
5
-
4
-
5
-
4
-
3
-
3
-
CLK
DQM to Data-Out Hi-Z
tDQZ
2
-
2
-
2
-
2
-
2
-
2
-
2
-
CLK
DQM to Data-In Mask
tDQM
0
-
0
-
0
-
0
-
0
-
0
-
0
-
CLK
MRS to New Command
tMRD
2
-
2
-
2
-
2
-
2
-
2
-
2
-
CLK
CAS Latency = 3
tPROZ3
3
-
3
-
3
-
3
-
3
-
3
-
3
-
CLK
CAS Latency = 2
tPROZ2
2
-
2
-
2
-
2
-
2
-
2
-
2
-
CLK
Power Down Exit Time
tPDE
1
-
1
-
1
-
1
-
1
-
1
-
1
-
CLK
Self Refresh Exit Time
tSRE
1
-
1
-
1
-
1
-
1
-
1
-
1
-
CLK
Refresh Time
tREF
-
64
-
64
-
64
-
64
-
64
-
64
-
64
ms
Note
RAS Cycle Time
Precharge to Data
Output Hi-Z
1
Note :
1. A new command can be given tRRC after self refresh exit
Rev. 0.2/Aug. 01
9
HY57V281620HC(L)T
IBIS SPECIFICATION
IOH Characteristics (Pull-up)
Voltage
100MHz
(Min)
100MHz
(Max)
66MHz
(Min)
(V)
I(mA)
I(mA)
I(mA)
-2.4
3.3
-27.3
0
0.5
1
1.5
2
2.5
3
3.5
0
-100
3.0
0
-74.1
-0.7
2.6
-21.1
-129.2
-7.5
2.4
-34.1
-153.3
-13.3
2.0
-58.7
-197
-27.5
1.8
-67.3
-226.2
-35.5
1.65
-73
-248
-41.1
1.5
-77.9
-269.7
-47.9
1.4
-80.8
-284.3
-52.4
1.0
-88.6
-344.5
-72.5
0
-93
-502.4
-93
-200
I (mA)
3.45
66MHz and 100MHz Pull-up
-300
-400
-500
-600
Voltage (V)
IOH Min (100MHz)
IOH Min (66MHz)
IOH Max (66 /100MHz)
IOL Characteristics (Pull-down)
66MHz and 100MHz Pull-down
Voltage
100MHz
(Min)
100MHz
(Max)
66MHz
(Min)
(V)
I(mA)
I(mA)
I(mA)
0
0
0
0
0.4
27.5
70.2
17.7
0.65
41.8
107.5
26.9
0.85
51.6
133.8
33.3
1.0
58.0
151.2
37.6
1.4
70.7
187.7
46.6
1.5
72.9
194.4
48.0
1.65
75.4
202.5
49.5
1.8
77.0
208.6
50.7
Voltage (V)
1.95
77.6
212.0
51.5
IOL Min (100MHz)
3.0
80.3
219.6
54.2
IOL Min (66MHz)
3.45
81.4
222.6
54.9
Rev. 0.2/Aug. 01
250
I (mA)
200
150
100
50
0
0
0.5
1
1.5
2
2.5
3
3.5
IOL Max (100MHz)
10
HY57V281620HC(L)T
VDD Clamp @ CLK, CKE, CS, DQM & DQ
I(mA)
0.0
0.0
0.2
0.0
0.4
0.0
0.6
0.0
0.7
0.0
0.8
0.0
0.9
0.0
1.0
0.23
1.2
1.34
1.4
3.02
1.6
5.06
1.8
7.35
2.0
9.83
2.2
12.48
2.4
15.30
2.6
18.31
20
15
mA
VDD (V)
Minimum V DD clamp current
(Referenced to VDD )
10
5
0
0
-2.6
-57.23
-2.4
-45.77
-2.2
-38.26
-2.0
-31.22
-1.8
-24.58
-1.6
-18.37
-1.4
-12.56
-1.2
-7.57
-1.0
-3.37
-0.9
-1.75
-0.8
-0.58
-0.7
-0.05
-0.6
0.0
-0.4
0.0
-0.2
0.0
0.0
0.0
Rev. 0.2/Aug. 01
3
I (mA)
Minimum VSS clamp current
-3
-2.5
-2
-1.5
-1
-0.5
0
0
-10
-20
mA
I (mA)
2
Voltage
VSS Clamp @ CLK, CKE, CS, DQM & DQ
V SS (V)
1
-30
-40
-50
-60
Voltage
I (mA)
11
HY57V281620HC(L)T
DEVICE OPERATING OPTION TABLE
HY57V281620HC(L)T-6
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
166MHz(6ns)
3CLKs
3CLKs
7CLKs
10CLKs
3CLKs
5.4ns
2.7ns
143MHz(7ns)
3CLKs
3CLKs
6CLKs
9CLKs
3CLKs
5.4ns
2.7ns
133MHz(7.5ns)
2CLKs
3CLKs
6CLKs
9CLKs
3CLKs
5.4ns
2.7ns
HY57V281620HC(L)T-7
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
143MHz(7ns)
3CLKs
3CLKs
7CLKs
10CLKs
3CLKs
5.4ns
2.7ns
133MHz(7.5ns)
3CLKs
3CLKs
7CLKs
10CLKs
3CLKs
5.4ns
2.7ns
125MHz(8ns)
3CLKs
3CLKs
7CLKs
10CLKs
3CLKs
6ns
3ns
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
133MHz(7.5ns)
2CLKs
2CLKs
6CLKs
8CLKs
2CLKs
5.4ns
2.7ns
125MHz(8ns)
3CLKs
3CLKs
6CLKs
9CLKs
3CLKs
6ns
3ns
100MHz(10ns)
2CLKs
2CLKs
5CLKs
7CLKs
2CLKs
6ns
3ns
HY57V281620HC(L)T-K
HY57V281620HC(L)T-H
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
133MHz(7.5ns)
3CLKs
3CLKs
6CLKs
9CLKs
3CLKs
5.4ns
2.7ns
125MHz(8ns)
3CLKs
3CLKs
6CLKs
9CLKs
3CLKs
6ns
3ns
100MHz(10ns)
2CLKs
2CLKs
5CLKs
7CLKs
2CLKs
6ns
3ns
HY57V281620HC(L)T-8
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
125MHz(8ns)
3CLKs
3CLKs
6CLKs
9CLKs
3CLKs
6ns
3ns
100MHz(10ns)
2CLKs
2CLKs
5CLKs
7CLKs
2CLKs
6ns
3ns
83MHz(12ns)
2CLKs
2CLKs
4CLKs
6CLKs
2CLKs
6ns
3ns
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
100MHz(10ns)
2CLKs
2CLKs
5CLKs
7CLKs
2CLKs
6ns
3ns
83MHz(12ns)
2CLKs
2CLKs
5CLKs
7CLKs
2CLKs
6ns
3ns
66MHz(15ns)
2CLKs
2CLKs
4CLKs
6CLKs
2CLKs
6ns
3ns
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
100MHz(10ns)
3CLKs
2CLKs
5CLKs
7CLKs
2CLKs
6ns
3ns
83MHz(12ns)
2CLKs
2CLKs
5CLKs
7CLKs
2CLKs
6ns
3ns
66MHz(15ns)
2CLKs
2CLKs
4CLKs
6CLKs
2CLKs
6ns
3ns
HY57V281620HC(L)T-P
HY57V281620HC(L)T-S
Rev. 0.2/Aug. 01
12
HY57V281620HC(L)T
COMMAND TRUTH TABLE
Command
A10/
AP
ADDR
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM
Mode Register Set
H
X
L
L
L
L
X
OP code
H
X
X
X
No Operation
H
X
X
X
L
H
H
H
Bank Active
H
X
L
L
H
H
X
H
X
L
H
L
H
X
RA
Read
Note
V
L
CA
Read with Autoprecharge
V
H
Write
L
H
X
L
H
L
L
X
CA
Write with Autoprecharge
H
X
L
L
H
L
X
Precharge selected Bank
Burst Stop
H
DQM
H
Auto Refresh
H
H
L
L
L
Burst-Read-SingleWRITE
H
X
L
L
X
Entry
H
L
L
H
Exit
L
H
Self Refresh
H
L
H
H
L
X
L
V
X
V
X
H
X
X
L
L
X
A9 Pin High
(Other Pins OP code)
L
L
H
X
X
X
X
MRS
Mode
X
X
L
H
H
H
H
X
X
X
L
H
H
H
H
X
X
X
L
H
H
H
H
X
X
X
L
V
V
V
L
Precharge
power down
H
X
X
X
1
Entry
V
H
Precharge All Banks
X
X
Exit
Clock
Suspend
BA
Entry
Exit
L
H
L
H
X
L
H
X
X
X
X
Note :
1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high
2. X = Don′t care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address,
Opcode = Operand Code, NOP = No Operation
3. The burst read sigle write mode is entered by programming the write burst mode bit (A9) in the mode register to a logic 1.
Rev. 0.2/Aug. 01
13
HY57V281620HC(L)T
PACKAGE INFORMATION
400mil 54pin Thin Small Outline Package
UNIT : mm(inch)
11.938(0.4700)
11.735(0.4620)
22.327(0.8790)
22.149(0.8720)
10.262(0.4040)
10.058(0.3960)
0.150(0.0059)
0.050(0.0020)
0.80(0.0315)BSC
Rev. 0.2/Aug. 01
0.400(0.016)
0.300(0.012)
1.194(0.0470)
0.991(0.0390)
5deg
0deg
0.597(0.0235)
0.406(0.0160)
0.210(0.0083)
0.120(0.0047)
14
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