Hynix HY57V64820HGLTP-55 4 banks x 2m x 8bit synchronous dram Datasheet

HY57V64820HGTP
4 Banks x 2M x 8Bit Synchronous DRAM
DESCRIPTION
The Hynix HY57V64820HG is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which
require large memory density and high bandwidth. HY57V64820HG is organized as 4banks of 2,097,152x8.
HY57V64820HG is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output
voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by
a single control command (Burst length of 1,2,4,8 or Full page), and the burst count sequence(sequential or interleave). A burst of read
or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or
write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
FEATURES
•
Single 3.3±0.3V power supply
•
Auto refresh and self refresh
•
All device pins are compatible with LVTTL interface
•
4096 refresh cycles / 64ms
•
JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin
pitch
•
Programmable Burst Length and Burst Type
•
All inputs and outputs referenced to positive edge of system
clock
- 1, 2, 4, 8 or Full page for Sequential Burst
•
Data mask function by DQM
•
Internal four banks operation
- 1, 2, 4 or 8 for Interleave Burst
•
Programmable CAS Latency ; 2, 3 Clocks
ORDERING INFORMATION
Part No.
Clock Frequency
HY57V64820HGTP-5/55/6/7
200/183/166/143MHz
HY57V64820HGTP-K
133MHz
HY57V64820HGTP-H
133MHz
HY57V64820HGTP-8
125MHz
HY57V64820HGTP-P
100MHz
HY57V64820HGTP-S
100MHz
HY57V64820HGLTP-5/55/6/7
200/183/166/143MHz
HY57V64820HGLTP-K
133MHz
HY57V64820HGLTP-H
133MHz
HY57V64820HGLTP-8
125MHz
HY57V64820HGLTP-P
100MHz
HY57V64820HGLTP-S
100MHz
Power
Organization
Interface
Package
4Banks x 2Mbits x8
LVTTL
400mil 54pin TSOP II
(Pb free)
Normal
Low power
Note) Hynix supports lead free part for each speed grade with same specification.
This document is a general product description and is subject to change without notice.Hynix Semiconductor does not assume any responsibility for use
of circuits described. No patent licenses are implied.
Rev. 0.1/ Nov. 03
1
HY57V64820HGTP
PIN CONFIGURATION
VDD
DQ0
VDDQ
NC
DQ1
VSSQ
NC
DQ2
VDDQ
NC
DQ3
VSSQ
NC
VDD
NC
/WE
/CAS
/RAS
/CS
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54pin TSOP II
400mil x 875mil
0.8mm pin pitch
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
DQ7
VSSQ
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
VSS
NC
DQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
VSS
PIN DESCRIPTION
PIN
PIN NAME
DESCRIPTION
CLK
Clock
The system clock input. All other inputs are registered to the SDRAM on the rising
edge of CLK
CKE
Clock Enable
Controls internal clock signal and when deactivated, the SDRAM will be one of the
states among power down, suspend or self refresh
CS
Chip Select
Enables or disables all inputs except CLK, CKE and DQM
BA0, BA1
Bank Address
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
A0 ~ A11
Address
Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA8
Auto-precharge flag : A10
RAS, CAS, WE
Row Address Strobe,
Column Address Strobe, Write
Enable
RAS, CAS and WE define the operation
Refer function truth table for details
DQM
Data Input/Output Mask
Controls output buffers in read mode and masks input data in write mode
DQ0 ~ DQ7
Data Input/Output
Multiplexed data input / output pin
VDD/VSS
Power Supply/Ground
Power supply for internal circuits and input buffers
VDDQ/VSSQ
Data Output Power/Ground
Power supply for output buffers
NC
No Connection
No connection
Rev. 0.1/ Nov. 03
2
HY57V64820HGTP
FUNCTIONAL BLOCK DIAGRAM
2Mbit x 4banks x 8 I/O Synchronous DRAM
Self refresh logic
& timer
Internal Row
counter
2Mx8 Bank3
CLK
Row active
Column
Pre
Decoders
DQM
DQ0
I/O Buffer & Logic
Column
Active
Memory
Cell
Array
Sense AMP & I/O Gate
refresh
2Mx8 Bank 0
X decoders
WE
2Mx8 Bank 1
X decoders
CAS
2Mx8 Bank 2
X decoders
RAS
State Machine
CS
Row
Pre
Decoders
X decoders
CKE
DQ1
DQ6
DQ7
Y decoders
Bank Select
A0
A1
Column Add
Counter
Address
Registers
Address buffers
A11
BA0
BA1
Rev. 0.1/ Nov. 03
Burst
Counter
Mode Registers
CAS Latency
Data Out Control
Pipe Line Control
3
HY57V64820HGTP
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Unit
Ambient Temperature
TA
0 ~ 70
°C
Storage Temperature
TSTG
-55 ~ 125
°C
Voltage on Any Pin relative to VSS
VIN, VOUT
-1.0 ~ 4.6
V
Voltage on VDD relative to VSS
VDD, VDDQ
-1.0 ~ 4.6
V
Short Circuit Output Current
IOS
50
mA
Power Dissipation
PD
1
W
Soldering Temperature ⋅ Time
TSOLDER
260 ⋅ 10
°C ⋅ Sec
Note : Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITION (TA=0 to 70°C)
Parameter
Symbol
Min
Typ.
Max
Unit
Note
Power Supply Voltage
VDD, VDDQ
3.0
3.3
3.6
V
1
Input High Voltage
VIH
2.0
3.0
VDDQ + 2.0
V
1,2
Input Low Voltage
VIL
VSSQ - 2.0
0
0.8
V
1,3
Note
Note :
1.All voltages are referenced to VSS = 0V
2.VIH (max) is acceptable 5.6V AC pulse width with ≤3ns of duration
3.VIL (min) is acceptable -2.0V AC pulse width with ≤3ns of duration
AC OPERATING CONDITION (TA=0 to 70°C, VDD=3.3 ± 0.3V, VSS=0V)
Parameter
Symbol
Value
Unit
VIH / VIL
2.4/0.4
V
Vtrip
1.4
V
Input Rise / Fall Time
tR / tF
1
ns
Output Timing Measurement Reference Level
Voutref
1.4
V
CL
50
pF
AC Input High / Low Level Voltage
Input Timing Measurement Reference Level Voltage
Output Load Capacitance for Access Time Measurement
1
Note :
1. Output load to measure access time is equivalent to two TTL gates and one capacitor (50pF)
For details, refer to AC/DC output circuit
Rev. 0.1/ Nov. 03
4
HY57V64820HGTP
CAPACITANCE (TA=25°C, f=1MHz)
Parameter
Pin
Input capacitance
Data input / output capacitance
Symbol
Min
Max
Unit
CLK
CI1
2
4
pF
A0 ~ A11, BA0, BA1, CKE, CS, RAS, CAS,
WE, DQM
CI2
2.5
5
pF
DQ0 ~ DQ7
CI/O
2
6.5
pF
OUTPUT LOAD CIRCUIT
Vtt=1.4V
RT=250 Ω
Output
Output
50pF
50pF
DC Output Load Circuit
AC Output Load Circuit
DC CHARACTERISTICS I (TA=0 to 70°C, VDD=3.3±0.3V)
Parameter
Symbol
Min.
Max
Unit
Note
Input Leakage Current
ILI
-1
1
uA
1
Output Leakage Current
ILO
-1
1
uA
2
Output High Voltage
VOH
2.4
-
V
IOH = -4mA
Output Low Voltage
VOL
-
0.4
V
IOL = +4mA
Note :
1.VIN = 0 to 3.6V, All other pins are not tested under VIN =0V
2.DOUT is disabled, VOUT=0 to 3.6V
Rev. 0.1/ Nov. 03
5
HY57V64820HGTP
DC CHARACTERISTICS II (TA=0 to 70°C, VDD=3.3±0.3V, VSS=0V)
Speed
Parameter
Symbol
Test Condition
-6
-7
-K
-H
-8
-P/S
90
85
85
85
85
80
Unit
Note
mA
1
IDD1
Burst length=1, One bank active
tRC ≥ tRC(min), IOL=0mA
IDD2P
CKE ≤ VIL(max), tCK = min
2
mA
IDD2PS
CKE ≤ VIL(max), tCK = ∞
2
mA
IDD2N
CKE ≥ VIH(min), CS ≥ VIH(min), tCK = min
Input signals are changed one time during
2clks. All other pins ≥ VDD-0.2V or ≤ 0.2V
15
mA
IDD2NS
CKE ≥ VIH(min), tCK = ∞
Input signals are stable.
12
mA
IDD3P
CKE ≤ VIL(max), tCK = min
6
mA
IDD3PS
CKE ≤ VIL(max), tCK = ∞
5
mA
IDD3N
CKE ≥ VIH(min), CS ≥ VIH(min), tCK = min
Input signals are changed one time during
2clks. All other pins ≥ VDD-0.2V or ≤ 0.2V
30
mA
IDD3NS
CKE ≥ VIH(min), tCK = ∞
Input signals are stable.
20
mA
Burst Mode Operating
Current
IDD4
tCK ≥ tCK(min), IOL=0mA
All banks active
Auto Refresh Current
IDD5
tRRC ≥ tRRC(min), All banks active
Self Refresh Current
IDD6
CKE ≤ 0.2V
Operating Current
Precharge Standby Current
in Power Down Mode
Precharge Standby Current
in Non Power Down Mode
Active Standby Current
in Power Down Mode
Active Standby Current
in Non Power Down Mode
CL=3
150
150
CL=2
NA
NA
150
150
130
120
120
mA
1
mA
160
mA
2
1
mA
3
400
uA
4
Note :
1.IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open
2.Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II
3.HY57V64820HGTP-7/K/H/8/P/S
4.HY57V64820HGLTP-7/K/H/8/P/S
Rev. 0.1/ Nov. 03
6
HY57V64820HGTP
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
-6
Parameter
CAS
Latency = 3
tCK3
Max
6
Min
Max
7
1000
CAS
Latency = 2
-K
-H
-8
-P
-S
Unit
Min
System clock
cycle time
-7
Symbol
Min
Max
7.5
1000
Max
7.5
1000
Max
8
1000
10
Min
Max
10
1000
10
Min
10
1000
10
Note
Max
ns
1000
10
Clock high pulse width
tCHW
2.5
-
2.5
-
2.5
-
2.5
-
3
-
3
-
3
-
ns
1
Clock low pulse width
tCLW
2.5
-
2.5
-
2.5
-
2.5
-
3
-
3
-
3
-
ns
1
tAC3
-
5.4
-
5.4
-
5.4
5.4
-
6
6
-
6
ns
CAS
Latency = 3
7.5
Min
tCK2
Access time
from clock
10
Min
12
ns
2
CAS
Latency = 2
tAC2
-
6
-
6
-
5.4
6
-
6
-
6
-
8
ns
Data-out hold time
tOH
2.7
-
2.7
-
2.7
-
2.7
-
3
-
3
-
3
-
ns
Data-Input setup time
tDS
1.5
-
1.5
-
1.5
-
1.5
-
2
-
2
-
2
-
ns
1
Data-Input hold time
tDH
0.8
-
0.8
-
0.8
-
0.8
-
1
-
1
-
1
-
ns
1
Address setup time
tAS
1.5
-
1.5
-
1.5
-
1.5
-
2
-
2
-
2
-
ns
1
Address hold time
tAH
0.8
-
0.8
-
0.8
-
0.8
-
1
-
1
-
1
-
ns
1
CKE setup time
tCKS
1.5
-
1.5
-
1.5
-
1.5
-
2
-
2
-
2
-
ns
1
CKE hold time
tCKH
0.8
-
0.8
-
0.8
-
0.8
-
1
-
1
-
1
-
ns
1
Command setup time
tCS
1.5
-
1.5
-
1.5
-
1.5
-
2
-
2
-
2
-
ns
1
Command hold time
tCH
0.8
-
0.8
-
0.8
-
0.8
-
1
-
1
-
1
-
ns
1
CLK to data output in
low Z-time
tOLZ
1
-
1.5
-
1.5
-
1.5
-
1
-
1
-
2
-
ns
CAS
Latency = 3
CLK to data
output in high
Z-time
CAS
Latency = 2
tOHZ3
ns
5.4
5.4
tOHZ2
5.4
5.4
6
6
6
ns
Note :
1.Assume tR / tF (input rise and fall time ) is 1ns
2.Access times to be measured with input signals of 1v/ns edge rate
Rev. 0.1/ Nov. 03
7
HY57V64820HGTP
AC CHARACTERISTICS II
-6
Parameter
-7
-K
-H
-8
-P
-S
Symbol
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Operation
tRC
60
-
62
-
65
-
65
-
68
-
70
-
70
-
ns
Auto
Refresh
tRRC
60
-
62
-
65
-
65
-
68
-
70
-
70
-
ns
RAS to CAS Delay
tRCD
18
-
20
-
15
-
20
-
20
-
20
-
20
-
ns
RAS Active Time
tRAS
42
100K
42
120K
45
120K
45
120K
48
120K
50
120K
50
120K
ns
RAS Precharge Time
tRP
18
-
20
-
15
-
20
-
20
-
20
-
20
-
ns
RAS to RAS Bank Active
tRRD
Delay
12
-
14
-
15
-
15
-
16
-
20
-
20
-
ns
tCCD
1
-
1
-
1
-
1
-
1
-
1
-
1
-
CLK
Write Command to DatatWTL
In Delay
0
-
0
-
0
-
0
-
0
-
0
-
0
-
CLK
Data-In to Precharge
Command
tDPL
2
-
1
-
1
-
1
-
1
-
1
-
1
-
CLK
Data-In to Active
Command
tDAL
5
-
4
-
4
-
4
-
4
-
3
-
3
-
CLK
DQM to Data-Out Hi-Z
tDQZ
2
-
2
-
2
-
2
-
2
-
2
-
2
-
CLK
DQM to Data-In Mask
tDQM
0
-
0
-
0
-
0
-
0
-
0
-
0
-
CLK
MRS to New Command tMRD
2
-
1
-
1
-
1
-
1
-
1
-
1
-
CLK
3
-
3
-
3
-
3
-
3
-
3
-
3
-
CLK
2
-
2
-
2
-
2
-
2
-
2
-
2
-
CLK
RAS Cycle
Time
CAS to CAS Delay
CAS
tPROZ3
Precharge Latency = 3
to Data
Output Hi-Z CAS
tPROZ2
Latency = 2
Power Down Exit Time
tPDE
1
-
1
-
1
-
1
-
1
-
1
-
1
-
CLK
Self Refresh Exit Time
tSRE
1
-
1
-
1
-
1
-
1
-
1
-
1
-
CLK
Refresh Time
tREF
-
64
-
64
-
64
-
64
-
64
-
64
-
64
ms
Note
1
Note :
1. A new command can be given tRRC after self refresh exit
Rev. 0.1/ Nov. 03
8
HY57V64820HGTP
DEVICE OPERATING OPTION TABLE
HYHY57V64820(L)TP-6
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
3CLKs
3CLKs
2CLKs
3CLKs
3CLKs
3CLKs
7CLKs
6CLKs
6CLKs
10CLKs
9CLKs
9CLKs
3CLKs
3CLKs
3CLKs
5.4ns
5.4ns
5.4ns
2.7ns
2.7ns
2.7ns
166MHz(6ns)
143MHz(7ns)
133MHz(7.5ns)
57V64820HG(L)TP-7
143MHz(7ns)
133MHz(7.5ns)
100MHz(10ns)
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
3CLKs
3CLKs
2CLKs
3CLKs
3CLKs
2CLKs
6CLKs
6CLKs
5CLKs
9CLKs
9CLKs
7CLKs
3CLKs
3CLKs
2CLKs
5.4ns
5.4ns
6ns
2.7ns
2.7ns
3ns
HY57V64820HG(L)TP-K
133MHz(7.5ns)
125MHz(8ns)
100MHz(10ns)
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
2CLKs
3CLKs
2CLKs
2CLKs
3CLKs
2CLKs
6CLKs
6CLKs
5CLKs
8CLKs
9CLKs
7CLKs
2CLKs
3CLKs
2CLKs
5.4ns
6ns
6ns
2.7ns
3ns
3ns
HY57V64820HG(L)TP-H
133MHz(7.5ns)
125MHz(8ns)
100MHz(10ns)
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
3CLKs
3CLKs
2CLKs
3CLKs
3CLKs
2CLKs
6CLKs
6CLKs
5CLKs
9CLKs
9CLKs
7CLKs
3CLKs
3CLKs
2CLKs
5.4ns
6ns
6ns
2.7ns
3ns
3ns
HY57V64820HG(L)TP-8
125MHz(8ns)
100MHz(10ns)
83MHz(12ns)
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
3CLKs
2CLKs
2CLKs
3CLKs
2CLKs
2CLKs
7CLKs
5CLKs
5CLKs
10CLKs
7CLKs
7CLKs
3CLKs
2CLKs
2CLKs
6ns
6ns
6ns
3ns
3ns
3ns
HY57V64820HG(L)TP-P
100MHz(10ns)
83MHz(12ns)
66MHz(15ns)
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
2CLKs
2CLKs
2CLKs
2CLKs
2CLKs
2CLKs
5CLKs
5CLKs
4CLKs
7CLKs
7CLKs
6CLKs
2CLKs
2CLKs
2CLKs
6ns
6ns
6ns
3ns
3ns
3ns
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
3CLKs
2CLKs
2CLKs
2CLKs
2CLKs
2CLKs
5CLKs
5CLKs
4CLKs
7CLKs
7CLKs
6CLKs
2CLKs
2CLKs
2CLKs
6ns
6ns
6ns
3ns
3ns
3ns
HY57V64820HG(L)TP-S
100MHz(10ns)
83MHz(12ns)
66MHz(15ns)
Rev. 0.1/ Nov. 03
9
HY57V64820HGTP
COMMAND TRUTH TABLE
Command
A10/
AP
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM
Mode Register Set
H
X
L
L
L
L
X
OP code
H
X
X
X
No Operation
H
X
X
X
L
H
H
H
Bank Active
H
X
L
L
H
H
X
H
X
L
H
L
H
X
ADDR
RA
Read
Note
V
L
CA
Read with Autoprecharge
V
H
Write
L
H
X
L
H
L
L
X
CA
Write with Autoprecharge
H
X
L
L
H
L
X
Burst Stop
H
X
DQM
H
Auto Refresh
H
H
L
L
L
Burst-READ-Single-WRITE
H
X
L
L
Entry
H
L
L
H
H
H
Exit
L
H
L
L
V
X
V
X
H
X
X
L
L
X
A9 Pin High
(Other Pins OP code)
L
L
H
X
X
X
X
X
X
L
H
H
H
H
X
X
X
L
H
H
H
H
X
X
X
L
H
H
H
H
X
X
X
L
V
V
V
L
Precharge power
down
X
X
X
Self Refresh1
H
L
H
X
Precharge selected Bank
Entry
V
H
Precharge All Banks
X
X
Exit
Clock
Suspend
BA
Entry
Exit
L
H
L
H
X
L
H
X
X
X
X
Note :
1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high
2. X = Don′t care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address,
Opcode = Operand Code, NOP = No Operation
Rev. 0.1/ Nov. 03
10
HY57V64820HGTP
PACKAGE INFORMATION
400mil 54pin Thin Small Outline Package
UNIT : mm(inch)
11.938(0.4700)
11.735(0.4620)
22.327(0.8790)
22.149(0.8720)
10.262(0.4040)
10.058(0.3960)
0.150(0.0059)
0.050(0.0020)
0.80(0.0315)BSC
Rev. 0.1/ Nov. 03
0.400(0.016)
0.300(0.012)
1.194(0.0470)
0.991(0.0390)
5deg
0deg
0.597(0.0235)
0.406(0.0160)
0.210(0.0083)
0.120(0.0047)
11
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