Qimonda HYB25DC256163CE-5 256-mbit double-data-rate sgram Datasheet

January 2007
HYB25D C25616 3 CE- 4
HYB25D C25616 3 CE- 5
HYB25D C25616 3 CE- 6
2 5 6 - M b i t D o u b l e - D a t a - R a t e SG R A M
Green Product
Internet Data Sheet
Rev. 1.1
Internet Data Sheet
HYB25DC256163CE
256-Mbit Double-Data-Rate SGRAM
HYB25DC256163CE-4, HYB25DC256163CE-5, HYB25DC256163CE-6
Revision History: 2007-01, Rev. 1.1
Page
Subjects (major changes since last revision)
All
Adapted internet edition
All
Added new speedsort -4
Previous Revision: 2007-01, Rev. 1.0
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qag_techdoc_rev400 / 3.2 QAG / 2006-08-01
03292006-SR4U-HULB
2
Internet Data Sheet
HYB25DC256163CE
256-Mbit Double-Data-Rate SGRAM
1
Overview
This chapter lists all main features of the product family HYB25DC256163CE and the ordering information.
1.1
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Features
Double data rate architecture: two data transfers per clock cycle
Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver
DQS is edge-aligned with data for reads and is center-aligned with data for writes
Differential clock inputs (CK and CK)
Four internal banks for concurrent operation
Data mask (DM) for write data
DLL aligns DQ and DQS transitions with CK transitions
Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
Burst Lengths: 2, 4, or 8
CAS Latency: 3
Auto Precharge option for each burst access
Auto Refresh and Self Refresh Modes
7.8 µs Maximum Average Periodic Refresh Interval
2.5 V (SSTL_2 compatible) I/O
VDDQ = 2.5 V ± 0.2 V (DDR200, DDR266, DDR333); VDDQ = 2.6 V ± 0.1 V (DDR400, DDR500)
VDD = 2.5 V ± 0.2 V (DDR200, DDR266, DDR333); VDD = 2.6 V ± 0.1 V (DDR400, DDR500)
PG-TSOPII-66 package
Lead- and halogene-free = green product
TABLE 1
Performance
Part Number Speed Code
Speed Grade
Max. Clock Frequency
Rev. 1.1, 2007-01
03292006-SR4U-HULB
@CL3
fCK3
3
–4
–5
–6
Unit
DDR500
DDR400B
DDR333
—
250
200
166
MHz
Internet Data Sheet
HYB25DC256163CE
256-Mbit Double-Data-Rate SGRAM
1.1.1
Description
The 256-Mbit Double-Data-Rate SGRAM is a high-speed CMOS, dynamic random-access memory containing
268,435,456 bits. It is internally configured as a quad-bank DRAM.
The 256-Mbit Double-Data-Rate SGRAM uses a double-data-rate architecture to achieve high-speed operation. The double
data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock
cycle at the I/O pins. A single read or write access for the 256-Mbit Double-Data-Rate SGRAM effectively consists of a single
2n-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle
data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a
strobe transmitted by the DDR SGRAM during Reads and by the memory controller during Writes. DQS is edge-aligned with
data for Reads and center-aligned with data for Writes.
The 256-Mbit Double-Data-Rate SGRAM operates from a differential clock (CK and CK; the crossing of CK going HIGH and
CK going LOW is referred to as the positive edge of CK). Commands (address and control signals) are registered at every
positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as
well as to both edges of CK.Read and write accesses to the DDR SGRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration
of an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the
Active command are used to select the bank and row to be accessed. The address bits registered coincident with the Read or
Write command are used to select the bank and the starting column location for the burst access.
The DDR SGRAM provides for programmable Read or Write burst lengths of 2, 4 or 8 locations. An Auto Precharge function
may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard SDRAMs,
the pipelined, multibank architecture of DDR SGRAMs allows for concurrent operation, thereby providing high effective
bandwidth by hiding row precharge and activation time.
An auto refresh mode is provided along with a power-saving power-down mode. All inputs are compatible with the Industry
Standard for SSTL_2. All outputs are SSTL_2, Class II compatible.
Note: The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of
operation.
TABLE 2
Ordering Information for Lead free Products
Product Type
Organisation
Clock (MHz)
Package
Note
HYB25DC256163CE-4
×16
250
PG-TSOPII-66-2
1)
HYB25DC256163CE-5
200
HYB25DC256163CE-6
166
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 1.1, 2007-01
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Internet Data Sheet
HYB25DC256163CE
256-Mbit Double-Data-Rate SGRAM
2
Chip Configuration
The chip configuration of a DDR SGRAM is listed by function in Table 3. The abbreviations used in the Pin#/Buffer# column
are explained in Table 4 and Table 5 respectively. The chip numbering for TSOP is depicted in Figure 1.
TABLE 3
Chip Configuration
Ball#
Name
Pin
Type
Buffer
Type
Function
CK
I
SSTL
Clock Signal
Clock Signals
45
46
CK
I
SSTL
Complementary Clock Signal
44
CKE
I
SSTL
Clock Enable
23
RAS
I
SSTL
Row Address Strobe
22
CAS
I
SSTL
Column Address Strobe
21
WE
I
SSTL
Write Enable
24
CS
I
SSTL
Chip Select
Bank Address Bus 2:0
Control Signals
Address Signals
26
BA0
I
SSTL
27
BA1
I
SSTL
29
A0
I
SSTL
30
A1
I
SSTL
31
A2
I
SSTL
32
A3
I
SSTL
35
A4
I
SSTL
36
A5
I
SSTL
37
A6
I
SSTL
38
A7
I
SSTL
39
A8
I
SSTL
40
A9
I
SSTL
28
A10
I
SSTL
Address Bus 11:0
AP
I
SSTL
41
A11
I
SSTL
42
A12
I
SSTL
Address Signal 12
Note: Module based on 256 Mbit or larger dies
NC
NC
—
Note: Module based on 128 Mbit or smaller dies
17
A13
I
SSTL
Address Signal 13
Note: 1 Gbit based module
NC
NC
—
Note: Module based on 512 Mbit or smaller dies
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Internet Data Sheet
HYB25DC256163CE
256-Mbit Double-Data-Rate SGRAM
Ball#
Name
Pin
Type
Buffer
Type
Function
Data Signal 15:0
Data Signals ×16 Organization
2
DQ0
I/O
SSTL
4
DQ1
I/O
SSTL
5
DQ2
I/O
SSTL
7
DQ3
I/O
SSTL
8
DQ4
I/O
SSTL
10
DQ5
I/O
SSTL
11
DQ6
I/O
SSTL
13
DQ7
I/O
SSTL
54
DQ8
I/O
SSTL
56
DQ9
I/O
SSTL
57
DQ10
I/O
SSTL
59
DQ11
I/O
SSTL
60
DQ12
I/O
SSTL
62
DQ13
I/O
SSTL
63
DQ14
I/O
SSTL
65
DQ15
I/O
SSTL
Data Strobe ×16 Organization
51
UDQS
I/O
SSTL
Data Strobe Upper Byte
16
LDQS
I/O
SSTL
Data Strobe Lower Byte
Data Mask ×16 Organization
47
UDM
I
SSTL
Data Mask Upper Byte
20
LDM
I
SSTL
Data Mask Lower Byte
AI
—
I/O Reference Voltage
PWR
—
I/O Driver Power Supply
PWR
—
Power Supply
PWR
—
Power Supply
PWR
—
Power Supply
—
Not Connected
Power Supplies
VREF
3, 9, 15, 55, 61 VDDQ
1, 18, 33
VDD
6, 12, 52, 58, 64 VSSQ
VSS
34
49
Not Connected ×16 Organization
14, 17, 19, 25,
42, 43, 50, 53
NC
Rev. 1.1, 2007-01
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NC
6
Internet Data Sheet
HYB25DC256163CE
256-Mbit Double-Data-Rate SGRAM
TABLE 4
Abbreviations for Pin Type
Abbreviation
Description
I
Standard input-only pin. Digital levels
O
Output. Digital levels
I/O
I/O is a bidirectional input/output signal
AI
Input. Analog levels
PWR
Power
GND
Ground
NC
Not Connected
TABLE 5
Abbreviations for Buffer Type
Abbreviation
Description
SSTL
Serial Stub Terminalted Logic (SSTL2)
LV-CMOS
Low Voltage CMOS
CMOS
CMOS Levels
OD
Open Drain. The corresponding pin has 2 operational states, active low and tristate, and
allows multiple devices to share as a wire-OR
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Internet Data Sheet
HYB25DC256163CE
256-Mbit Double-Data-Rate SGRAM
FIGURE 1
Chip Configuration PG-TSOPII-66
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Rev. 1.1, 2007-01
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Internet Data Sheet
HYB25DC256163CE
256-Mbit Double-Data-Rate SGRAM
3
Functional Description
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Field
Bits
Type1)
Description
BL
[2:0]
W
Burst Length
Number of sequential bits per DQ related to one read/write command.
Note: All other bit combinations are RESERVED.
001 2
010 4
010 8
BT
3
Burst Type
See Table 6 for internal address sequence of low order address bits.
0 Sequential
1 Sequential
CL
[6:4]
CAS Latency
Number of full clocks from read command to first data valid window.
Note: All other bit combinations are RESERVED.
011 3
MODE [12:7]
Operating Mode
Note: All other bit combinations are RESERVED.
000000 Normal Operation without DLL Reset
000010 Normal Operation with DLL Reset
1) W = write only register bit
Rev. 1.1, 2007-01
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Internet Data Sheet
HYB25DC256163CE
256-Mbit Double-Data-Rate SGRAM
TABLE 6
Burst Definition
Burst Length
Starting Column Address
A2
A1
A0
Type = Sequential
Type = Interleaved
0
0-1
0-1
1
1-0
1-0
0
0
0-1-2-3
0-1-2-3
0
1
1-2-3-0
1-0-3-2
1
0
2-3-0-1
2-3-0-1
2
4
8
Order of Accesses Within a Burst
1
1
3-0-1-2
3-2-1-0
0
0
0
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7
0
0
1
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0
1
0
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
0
1
1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1
0
0
4-5-6-7-0-1-2-3
4-5-6-7-0-1-2-3
1
0
1
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1
1
0
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
1
1
1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
Notes
1.
2.
3.
4.
For a burst length of two, A1-Ai selects the two-data-element block; A0 selects the first access within the block.
For a burst length of four, A2-Ai selects the four-data-element block; A0-A1 selects the first access within the block.
For a burst length of eight, A3-Ai selects the eight-data-element block; A0-A2 selects the first access within the block.
Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.
Rev. 1.1, 2007-01
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Internet Data Sheet
HYB25DC256163CE
256-Mbit Double-Data-Rate SGRAM
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Field
Bits
Type1)
Description
DLL
0
W
DLL Status
Enabled
0B
1B
Disabled
DS
1
Drive Strength
0B
Normal
Weak
1B
MODE
[12:2]
Operating Mode
Note: All other bit combinations are RESERVED.
00000000000B Normal Operation
1) W = write only register bit
TABLE 7
Truth Table 1a: Commands
Name (Function)
CS
RAS
CAS
WE
Address
MNE
Note
Deselect (NOP)
H
X
X
X
X
NOP
1)2)
No Operation (NOP)
L
H
H
H
X
NOP
1)2)
Active (Select Bank And Activate Row)
L
L
H
H
Bank/Row
ACT
1)3)
Read (Select Bank And Column, And Start Read Burst)
L
H
L
H
Bank/Col
Read
1)4)
Write (Select Bank And Column, And Start Write Burst)
L
H
L
L
Bank/Col
Write
1)4)
Burst Terminate
L
H
H
L
X
BST
1)5)
Precharge (Deactivate Row In Bank Or Banks)
L
L
H
L
Code
PRE
1)6)
Auto Refresh Or Self Refresh (Enter Self Refresh Mode)
L
L
L
H
X
AR/SR
1)7)8)
Mode Register Set
L
L
L
L
Op-Code
MRS
1)9)
1)
2)
3)
4)
5)
6)
7)
8)
9)
CKE is HIGH for all commands shown except Self Refresh. VREF must be maintained during Self Refresh operation
Deselect and NOP are functionally interchangeable.
BA0-BA1 provide bank address and A0-A12 provide row address.
BA0, BA1 provide bank address; A0-Ai provide column address (where i = 8 for x16);A10 HIGH enables the Auto Precharge feature
(nonpersistent), A10 LOW disables the Auto Precharge feature.
Applies only to read bursts with Auto Precharge disabled; this command is undefined (and should not be used) for read bursts with Auto
Precharge enabled or for write bursts.
A10 LOW: BA0, BA1 determine which bank is precharged. A10 HIGH: all banks are precharged and BA0, BA1 are “Don’t Care”.
This command is Auto Refresh if CKE is HIGH; Self Refresh if CKE is LOW.
Internal refresh counter controls row and bank addressing; all inputs and I/Os are “Don’t Care” except for CKE.
BA0, BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register; BA0 = 1, BA1 = 0 selects
Extended Mode Register; other combinations of BA0-BA1 are reserved; A0-A12 provide the op-code to be written to the selected Mode
Register).
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Internet Data Sheet
HYB25DC256163CE
256-Mbit Double-Data-Rate SGRAM
TABLE 8
Truth Table 1b: DM Operation
Name (Function)
DM
DQs
Note
Write Enable
L
Valid
1)
Write Inhibit
H
X
1) Used to mask write data; provided coincident with the corresponding data.
TABLE 9
Truth Table 2: Clock Enable (CKE)
Current State
CKE n-1
CKEn
Command n
Action n
Note
Previous Cycle
Current Cycle
Self Refresh
L
L
X
Maintain Self-Refresh
1)
Self Refresh
L
H
Deselect or NOP
Exit Self-Refresh
2)
Power Down
L
L
X
Maintain Power-Down
–
Power Down
L
H
Deselect or NOP
Exit Power-Down
–
All Banks Idle
H
L
Deselect or NOP
Precharge Power-Down Entry
–
All Banks Idle
H
L
AUTO REFRESH
Self Refresh Entry
–
Bank(s) Active
H
L
Deselect or NOP
Active Power-Down Entry
–
H
H
See Table 10
–
–
1) VREF must be maintained during Self Refresh operation
2) Deselect or NOP commands should be issued on any clock edges occurring during the Self Refresh Exit (tXSNR) period. A minimum of 200
clock cycles are needed before applying a read command to allow the DLL to lock to the input clock.
Notes
1.
2.
3.
4.
CKEn is the logic state of CKE at clock edge n: CKE n-1 was the state of CKE at the previous clock edge.
Current state is the state of the DDR SGRAM immediately prior to clock edge n.
COMMAND n is the command registered at clock edge n, and ACTION n is a result of COMMAND n.
All states and sequences not shown are illegal or reserved.
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Internet Data Sheet
HYB25DC256163CE
256-Mbit Double-Data-Rate SGRAM
TABLE 10
Truth Table 3: Current State Bank n - Command to Bank n (same bank)
Current State
CS
RAS
CAS
WE
Command
Action
Note
Any
H
X
X
X
Deselect
NOP. Continue previous operation.
1)2)3)4)5)6)
L
H
H
H
No Operation
NOP. Continue previous operation.
1) to 6)
L
L
H
H
Active
Select and activate row
1) to 6)
L
L
L
H
AUTO REFRESH
–
1) to7)
L
L
L
L
MODE REGISTER
SET
–
1) to 7)
L
H
L
H
Read
Select column and start Read burst
1) to 6),8)
L
H
L
L
Write
Select column and start Write burst
1) to 6),8)
L
L
H
L
Precharge
Deactivate row in bank(s)
1) to 6),9)
Read (Auto
Precharge
Disabled)
L
H
L
H
Read
Select column and start new Read burst
1) to 6),8)
L
L
H
L
Precharge
Truncate Read burst, start Precharge
1) to 6),9)
L
H
H
L
BURST
TERMINATE
BURST TERMINATE
1) to 6),10)
Write (Auto
Precharge
Disabled)
L
H
L
H
Read
Select column and start Read burst
1) to 6), 8),11)
L
H
L
L
Write
Select column and start Write burst
1) to 6),8)
Idle
Row Active
1) to 6),9),11)
Truncate Write burst, start Precharge
1) This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Table 9 and after tXSNR/tXSRD has been met (if the previous state was
L
L
H
L
Precharge
self refresh).
2) This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are those allowed
to be issued to that bank when in that state. Exceptions are covered in the notes below.
3) Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in
progress.
Read: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
4) The following states must not be interrupted by a command issued to the same bank.
Precharging: Starts with registration of a Precharge command and ends when tRP is met. Once tRP is met, the bank is in the idle state.
Row Activating: Starts with registration of an Active command and ends when tRCD is met. Once tRCD is met, the bank is in the “row active”
state.
Read w/Auto Precharge Enabled: Starts with registration of a Read command with Auto Precharge enabled and ends when tRP has been
met. Once tRP is met, the bank is in the idle state.
Write w/Auto Precharge Enabled: Starts with registration of a Write command with Auto Precharge enabled and ends when tRP has been
met. Once tRP is met, the bank is in the idle state. Deselect or NOP commands, or allowable commands to the other bank should be issued
on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and according
to Table 11.
5) The following states must not be interrupted by any executable command; Deselect or NOP commands must be applied on each positive
clock edge during these states.
Refreshing: Starts with registration of an Auto Refresh command and ends when tRFC is met. Once tRFC is met, the DDR SGRAM is in the
“all banks idle” state.
Accessing Mode Register: Starts with registration of a Mode Register Set command and ends when tMRD has been met. Once tMRD is met,
the DDR SGRAM is in the “all banks idle” state.
Precharging All: Starts with registration of a Precharge All command and ends when tRP is met. Once tRP is met, all banks is in the idle state.
6) All states and sequences not shown are illegal or reserved.
7) Not bank-specific; requires that all banks are idle.
8) Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with
Auto Precharge disabled.
9) May or may not be bank-specific; if all/any banks are to be precharged, all/any must be in a valid state for precharging.
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Internet Data Sheet
HYB25DC256163CE
256-Mbit Double-Data-Rate SGRAM
10) Not bank-specific; BURST TERMINATE affects the most recent Read burst, regardless of bank.
11) Requires appropriate DM masking.
TABLE 11
Truth Table 4: Current State Bank n - Command to Bank m (different bank)
Current State
CS
RAS CAS WE
Command
Action
Note
H
X
X
X
Deselect
NOP. Continue previous operation.
1)2)3)4)5)6)
L
H
H
H
No Operation
NOP. Continue previous operation.
1) to 6)
Idle
X
X
X
X
Any Command
Otherwise Allowed to
Bank m
–
1) to 6)
Row Activating,
Active, or
Precharging
L
L
H
H
Active
Select and activate row
1) to 6)
L
H
L
H
Read
Select column and start Read burst
1) to7)
L
H
L
L
Write
Select column and start Write burst
1) to 7)
L
L
H
L
Precharge
–
1) to 6)
Read (Auto
Precharge
Disabled)
L
L
H
H
Active
Select and activate row
1) to 6)
L
H
L
H
Read
Select column and start new Read burst
1) to 7)
L
L
H
L
Precharge
–
1) to 6)
Write (Auto
Precharge
Disabled)
L
L
H
H
Active
Select and activate row
1) to 6)
L
H
L
H
Read
Select column and start Read burst
1) to 8)
L
H
L
L
Write
Select column and start new Write burst
1) to 7)
L
L
H
L
Precharge
–
1) to 6)
L
L
H
H
Active
Select and activate row
1) to 6)
L
H
L
H
Read
Select column and start new Read burst
1) to 7),9)
L
H
L
L
Write
Select column and start Write burst
1) to 7),9),10)
L
L
H
L
Precharge
–
1) to 6)
L
L
H
H
Active
Select and activate row
1) to 6)
L
H
L
H
Read
Select column and start Read burst
1) to 7),9)
L
H
L
L
Write
Select column and start new Write burst
1) to 7),9)
L
L
H
L
Precharge
–
1) to 6)
Any
Read (With Auto
Precharge)
Write (With Auto
Precharge)
1) This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Table 9: Clock Enable (CKE) and after tXSNR/tXSRD has been met (if
the previous state was self refresh).
2) This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown are those
allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in
the notes below.
3) Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in
progress.
Read: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Read with Auto Precharge Enabled: See 10).
Write with Auto Precharge Enabled: See 10).
4) AUTO REFRESH and Mode Register Set commands may only be issued when all banks are idle.
5) A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only.
6) All states and sequences not shown are illegal or reserved.
7) Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with
Auto Precharge disabled.
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HYB25DC256163CE
256-Mbit Double-Data-Rate SGRAM
8) Requires appropriate DM masking.
9) Concurrent Auto Precharge: This device supports “Concurrent Auto Precharge”. When a read with auto precharge or a write with auto
precharge is enabled any command may follow to the other banks as long as that command does not interrupt the read or write data
transfer and all other limitations apply (e.g. contention between READ data and WRITE data must be avoided). The minimum delay from
a read or write command with auto precharge enable, to a command to a different banks is summarized in Table 12.
10) A Write command may be applied after the completion of data output.
TABLE 12
Truth Table 5: Concurrent Auto Precharge
From Command
To Command (different bank)
Minimum Delay with Concurrent Auto Unit
Precharge Support
WRITE w/AP
Read or Read w/AP
1 + (BL/2) + tWTR
Write to Write w/AP
BL/2
Read w/AP
Rev. 1.1, 2007-01
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Precharge or Activate
1
Read or Read w/AP
BL/2
Write or Write w/AP
CL (rounded up) + BL/2
Precharge or Activate
1
15
tCK
tCK
tCK
tCK
tCK
tCK
Internet Data Sheet
HYB25DC256163CE
256-Mbit Double-Data-Rate SGRAM
4
Electrical Characteristics
4.1
Operating Conditions
TABLE 13
Absolute Maximum Ratings
Parameter
Voltage on I/O pins relative to VSS
Voltage on inputs relative to VSS
Voltage on VDD supply relative to VSS
Voltage on VDDQ supply relative to VSS
Operating temperature (ambient)
Storage temperature (plastic)
Power dissipation (per SDRAM component)
Short circuit output current
Symbol
VIN, VOUT
VIN
VDD
VDDQ
TA
TSTG
PD
IOUT
Values
Unit
Note/ Test
Condition
Min.
Typ.
Max.
–0.5
—
VDDQ + 0.5
V
—
–1
—
+3.6
V
—
–1
—
+3.6
V
—
–1
—
+3.6
V
—
0
—
+70
°C
—
–55
—
+150
°C
—
—
1
—
W
—
—
50
—
mA
—
Attention: Stresses above the max. values listed here may cause permanent damage to the device. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings
are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated
circuit.
TABLE 14
Input and Output Capacitances
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note/ Test Condition
Input Capacitance: CK, CK
CI1
2.0
—
3.0
pF
1)
Delta Input Capacitance
CdI1
—
—
0.25
pF
1)
Input Capacitance: All other input-only pins
CI2
2.0
—
3.0
pF
1)
Delta Input Capacitance: All other input-only pins
CdIO
—
—
0.5
pF
1)
Input/Output Capacitance: DQ, DQS, DM
CIO
4.0
—
5.0
pF
1)2)
Delta Input/Output Capacitance: DQ, DQS, DM
CdIO
—
—
0.5
pF
1)
1) These values are guaranteed by design and are tested on a sample base only. VDDQ = VDD = 2.5 V ± 0.2 V, f = 100 MHz, TA = 25 °C,
VOUT(DC) = VDDQ/2, VOUT (Peak to Peak) 0.2 V. Unused pins are tied to ground.
2) DM inputs are grouped with I/O pins reflecting the fact that they are matched in loading to DQ and DQS to facilitate trace matching at the
board level.
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HYB25DC256163CE
256-Mbit Double-Data-Rate SGRAM
TABLE 15
Electrical Characteristics and DC Operating Conditions
Parameter
Device Supply Voltage
Device Supply Voltage
Output Supply Voltage
Output Supply Voltage
Supply Voltage, I/O Supply
Voltage
Input Reference Voltage
I/O Termination Voltage
(System)
Symbol
Unit Note1)/Test Condition
Values
Min.
Typ.
Max.
VDD
VDD
VDDQ
VDDQ
VSS, VSSQ
2.3
2.5
2.7
V
2.5
2.6
2.7
V
2.3
2.5
2.7
V
2.5
2.6
2.7
V
fCK ≤ 166 MHz
fCK > 166 MHz 2)
fCK ≤ 166 MHz 3)
fCK > 166 MHz 2)3)
0
V
—
VREF
VTT
0.49 × VDDQ
0.5 × VDDQ
0.51 × VDDQ
V
4)
VREF – 0.04
—
VREF + 0.04
V
5)
VREF + 0.15
—
V
6)
–0.3
—
V
6)
–0.3
—
VDDQ + 0.3
VREF – 0.15
VDDQ + 0.3
V
6)
VIH(DC)
Input Low (Logic0) Voltage
VIL(DC)
Input Voltage Level, CK and VIN(DC)
Input High (Logic1) Voltage
0
CK Inputs
Input Differential Voltage,
CK and CK Inputs
VID(DC)
0.36
—
VDDQ + 0.6
V
6)7)
VI-Matching Pull-up Current
to Pull-down Current
VIRatio
0.71
—
1.4
—
8)
Input Leakage Current
II
–2
—
2
µA
Any input 0 V ≤ VIN ≤ VDD; All
other pins not under test = 0 V9)
Output Leakage Current
IOZ
–5
—
5
µA
Output High Current, Normal IOH
Strength Driver
—
—
Output Low Current, Normal IOL
16.2
—
Strength Driver
1) 0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V.
DQs are disabled; 0 V ≤ VOUT ≤
–16.2
mA
VDDQ 9)
VOUT = 1.95 V
—
mA
VOUT = 0.35 V
2) DDR400 conditions apply for all clock frequencies above 166 MHz.
3) Under all conditions, VDDQ must be less than or equal to VDD.
4) Peak to peak AC noise on VREF may not exceed ± 2% VREF.DC. VREF is also expected to track noise variations in VDDQ.
5) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and
must track variations in the DC level of VREF.
6) Inputs are not recognized as valid until VREF stabilizes.
7) VID is the magnitude of the difference between the input level on CK and the input level on CK.
8) The ratio of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire temperature and
voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the maximum difference between
pull-up and pull-down drivers due to process variation.
9) Values are shown per pin.
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HYB25DC256163CE
256-Mbit Double-Data-Rate SGRAM
4.2
AC Characteristics
(Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating Conditions, IDD
Specifications and Conditions, and Electrical Characteristics and AC Timing.)
Notes
1. All voltages referenced to VSS.
2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage
levels, but the related specifications and device operation are guaranteed for the full voltage range specified.
3. Figure 2 represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended
to be either a precise representation of the typical system environment nor a depiction of the actual load presented by a
production tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to a system
environment. Manufacturers will correlate to their production test conditions (generally a coaxial transmission line
terminated at the tester electronics).
4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5 V in the test environment, but input timing is still referenced
to VREF (or to the crossing point for CK, CK), and parameter specifications are guaranteed for the specified AC input levels
under normal use conditions. The minimum slew rate for the input signals is 1 V/ns in the range between VIL(AC) and VIH(AC).
5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches as
a result of the signal crossing the AC input level, and remains in that state as long as the signal does not ring back above
(below) the DC input LOW (HIGH) level).
6. For System Characteristics like Setup & Holdtime Derating for Slew Rate, I/O Delta Rise/Fall Derating, DDR SGRAM Slew
Rate Standards, Overshoot & Undershoot specification and Clamp V-I characteristics see the latest Industry specification
for DDR components.
FIGURE 2
AC Output Load Circuit Diagram / Timing Reference Load
VTT
50 Ω
Output
(VOUT)
Timing Reference Point
30 pF
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HYB25DC256163CE
256-Mbit Double-Data-Rate SGRAM
TABLE 16
AC Operating Conditions
Parameter
Symbol
VIH(AC)
VIL(AC)
VID(AC)
VIX(AC)
Input High (Logic 1) Voltage, DQ, DQS and DM Signals
Input Low (Logic 0) Voltage, DQ, DQS and DM Signals
Input Differential Voltage, CK and CK Inputs
Values
Min.
Max.
VREF + 0.31
—
Unit Note/ Test
Condition
V
1)2)3)
VREF – 0.31
V
0.7
VDDQ + 0.6
V
0.5 × VDDQ– 0.2 0.5 × VDDQ+ 0.2 V
1)2)3)
—
1)2)3)4)
1)2)3)5)
Input Closing Point Voltage, CK and CK Inputs
1) VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V (DDR200 - DDR333); VDDQ = 2.6 V ± 0.1 V, VDD = +2.6 V ± 0.1 V (DDR400); 0 °C ≤ TA ≤ 70 °C
2)
3)
4)
5)
Input slew rate = 1 V/ns.
Inputs are not recognized as valid until VREF stabilizes.
VID is the magnitude of the difference between the input level on CK and the input level on CK.
The value of VIX is expected to equal 0.5 × VDDQ of the transmitting device and must track variations in the DC level of the same.
TABLE 17
AC Timing - Absolute Specifications
Parameter
Symbol –4
DDR500
–5
–6
DDR400B
DDR333
Unit Note1)/ Test
Condition
Min.
Max.
Min.
Max.
Min.
Max.
tAC
–0.6
+0.6
–0.65
+0.65
–0.7
+0.7
ns
2)3)4)5)
CK high-level width tCH
0.45
0.55
0.45
0.55
0.45
0.55
tCK
2)3)4)5)
tCK
4
12
5
12
6
12
ns
CL = 3.0
tCL
tDAL
0.45
0.55
0.45
0.55
0.45
28
—
35
—
DQ and DM input
hold time
tDH
0.4
—
0.4
DQ and DM input
pulse width (each
input)
tDIPW
1.75
—
–0.65
DQ output access
time from CK/CK
Clock cycle time
CK low-level width
Auto precharge
write recovery +
precharge time
DQS output access tDQSCK
time from CK/CK
2)3)4)5)
2)3)4)5)
(tWR/tCK)+(tRP/tCK)
tCK
tCK
—
0.45
—
ns
2)3)4)5)
1.75
—
1.75
—
ns
2)3)4)5)6)
+0.65
–0.65
+0.65
–0.6
+0.6
ns
2)3)4)5)
0.55
2)3)4)5)6)
DQS input low
(high) pulse width
(write cycle)
tDQSL,H
0.35
—
0.35
—
0.35
—
tCK
2)3)4)5)
DQS-DQ skew
(DQS and
associated DQ
signals)
tDQSQ
—
0.5
—
0.5
—
0.45
ns
TSOPII
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HYB25DC256163CE
256-Mbit Double-Data-Rate SGRAM
Parameter
Symbol –4
DDR500
–5
–6
DDR400B
DDR333
Unit Note1)/ Test
Condition
Min.
Max.
Min.
Max.
Min.
Max.
Write command to
1st DQS latching
transition
tDQSS
0.85
1.15
0.75
1.25
0.75
1.25
tCK
2)3)4)5)
DQ and DM input
setup time
tDS
0.4
—
0.4
—
0.45
—
ns
2)3)4)5)
DQS falling edge
hold time from CK
(write cycle)
tDSH
0.2
—
0.2
—
0.2
—
tCK
2)3)4)5)
DQS falling edge to tDSS
CK setup time
(write cycle)
0.2
—
0.2
—
0.2
—
tCK
2)3)4)5)
Clock Half Period
tHP
min. (tCL, tCH)
—
min. (tCL, tCH) —
min. (tCL,
tCH)
—
ns
2)3)4)5)
Data-out highimpedance time
from CK/CK
tHZ
—
+0.7
—
+0.7
—
+0.7
ns
2)3)4)5)7)
Address and
control input hold
time
tIH
0.6
—
0.6
—
0.75
—
ns
fast slew rate
Control and Addr.
input pulse width
(each input)
3)4)5)6)8)
0.7
—
0.7
—
0.8
—
ns
slow slew
rate3)4)5)6)8)
tIPW
2.2
—
2.2
—
2.2
—
ns
2)3)4)5)9)
Address and
control input setup
time
tIS
0.6
—
0.6
—
0.75
—
ns
fast slew rate
Data-out lowimpedance time
from CK/CK
Mode register set
command cycle
time
3)4)5)6)8)
0.7
—
0.7
—
0.8
—
ns
slow slew
rate3)4)5)6)8)
tLZ
–0.7
+0.7
–0.7
+0.7
–0.7
+0.7
ns
2)3)4)5)7)
tMRD
2
—
2
—
2
—
tCK
2)3)4)5)
tHP –tQHS
—
tHP –tQHS
—
tHP –tQHS
—
ns
2)3)4)5)
DQ/DQS output
tQH
hold time from DQS
Data hold skew
factor
tQHS
—
0.4
—
0.5
—
0.55
ns
TSOPII2)3)4)5)
Active to
Autoprecharge
delay
tRAP
16
—
20
—
tRCD
—
ns
2)3)4)5)
Active to Precharge tRAS
command
36
70E+3
40
70E+3
42
70E+3 ns
2)3)4)5)
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HYB25DC256163CE
256-Mbit Double-Data-Rate SGRAM
Parameter
Symbol –4
DDR500
Active to
tRC
Active/Auto-refresh
command period
–5
–6
DDR400B
DDR333
Unit Note1)/ Test
Condition
Min.
Max.
Min.
Max.
Min.
Max.
52
—
55
—
60
—
ns
2)3)4)5)
Active to Read
delay
tRCDRD
16
—
20
—
18
—
ns
2)3)4)5)
Active to Write
delay
tRCDWR
12
—
15
—
18
—
ns
2)3)4)5)
Average Periodic
Refresh Interval
tREFI
—
7.8
—
7.8
—
7.8
µs
2)3)4)5)8)
Precharge
command period
tRP
16
—
20
—
18
—
ns
2)3)4)5)
Read preamble
tRPRE
tRPST
tRRD
0.9
1.1
0.9
1.1
0.9
1.1
2)3)4)5)
0.4
0.6
0.4
0.6
0.4
0.6
tCK
tCK
8
—
10
—
12
—
ns
2)3)4)5)
tWPRE
tWPRES
0.25
—
0.25
—
0.25
—
tCK
2)3)4)5)
Read postamble
Active bank A to
Active bank B
command
Write preamble
2)3)4)5)
0
—
0
—
0
—
ns
2)3)4)5)10)
tWPST
Write recovery time tWR
Internal write to
tWTR
0.4
0.6
0.4
0.6
0.4
0.6
tCK
2)3)4)5)11)
15
—
15
—
15
—
ns
2)3)4)5)
1
—
1
—
1
—
tCK
2)3)4)5)
Exit self-refresh to tXSNR
non-read command
75
—
75
—
75
—
ns
2)3)4)5)
Write preamble
setup time
Write postamble
read command
delay
Exit self-refresh to tXSRD
200
—
200
—
200
—
tCK 2)3)4)5)
read command
1) 0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V (DDR333); VDDQ = 2.6 V ± 0.1 V, VDD = +2.6 V ± 0.1 V (DDR400)
2) Input slew rate ≥ 1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals
other than CK/CK, is VREF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until VREF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT.
6) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time.
7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific
voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured
between VIH(ac) and VIL(ac).
9) These parameters guarantee device timing, but they are not necessarily tested on each device.
10) The specific requirement is that DQS be valid (HIGH,LOW, or some point on a valid transition) on or before this CK edge. A valid transition
is defined as monotonic and meeting the input slew rate specificationsof the device. When no writes were previously in progress on the
bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW at this time, depending
on tDQSS.
11) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
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HYB25DC256163CE
256-Mbit Double-Data-Rate SGRAM
TABLE 18
IDD Conditions
Parameter
Symbol
Operating Current: one bank; active/ precharge; tRC = tRCMIN; tCK = tCKMIN;
DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once every two
clock cycles.
IDD0
Operating Current: one bank; active/read/precharge; Burst = 4;
Refer to the following page for detailed test conditions.
IDD1
Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE ≤VILMAX; tCK = tCKMIN
IDD2P
IDD2F
Precharge Floating Standby Current: CS ≥ VIHMIN, all banks idle;
CKE ≥ VIHMIN; tCK = tCKMIN, address and other control inputs changing once per clock cycle, VIN = VREF for DQ, DQS
and DM.
Precharge Quiet Standby Current: CS ≥ VIHMIN, all banks idle; CKE ≥ VIHMIN; tCK = tCKMIN, address and other
control inputs stable at ≥ VIHMIN or ≤ VILMAX; VIN=VREF for DQ, DQS and DM.
IDD2Q
Active Power-Down Standby Current: one bank active; power-down mode;
CKE ≤ VILMAX; tCK= tCKMIN; VIN = VREF for DQ, DQS and DM.
IDD3P
Active Standby Current: one bank active; CS ≥ VIHMIN; CKE ≥ VIHMIN; tRC = tRASMAX; tCK = tCKMIN; DQ, DM and DQS IDD3N
inputs changing twice per clock cycle; address and control inputs changing once per clock cycle
Operating Current: one bank active; Burst = 2; reads; continuous burst; address and control inputs changing
once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR200 and DDR266A,
CL = 3 for DDR333; tCK = tCKMIN; IOUT = 0 mA
IDD4R
Operating Current: one bank active; Burst = 2; writes; continuous burst; address and control inputs changing
once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR200 and DDR266A,
CL = 3 for DDR333; tCK = tCKMIN
IDD4W
Auto-Refresh Current: tRC = tRFCMIN, burst refresh
IDD5
IDD6
IDD7
Self-Refresh Current: CKE ≤ 0.2 V; external clock on; tCK = tCKMIN
Operating Current: four bank; four bank interleaving with BL = 4; Refer to the following page for detailed test
conditions.
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HYB25DC256163CE
256-Mbit Double-Data-Rate SGRAM
TABLE 19
IDD Specification
Symbol
IDD0
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
IDD7
–4
–5
–6
1)
Unit
Note /Test Condition
115
75
65
mA
2)3)
135
95
80
mA
3)
6
4
4
mA
3)
45
30
25
mA
3)
35
20
17
mA
3)
23
13
11
mA
3)
65
43
36
mA
3)
150
100
85
mA
3)
160
100
90
mA
3)
240
140
120
mA
3)
2.8
1.4
1.4
mA
4)
315
210
180
mA
3)
1) Test conditions: VDD = 2.7 V, TA = 10 °C
2) IDD specifications are tested after the device is properly initialized and measured at 133 MHz for DDR266, 166 MHz for DDR333, and 200
MHz for DDR400, 250MHz for DDR500
3) Input slew rate = 1 V/ns
4) Enables on-chip refresh and address counters
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Internet Data Sheet
HYB25DC256163CE
256-Mbit Double-Data-Rate SGRAM
4.3
Current Measurement Conditions
Legend: A = Activate, R = Read, P = Precharge, N = NOP
IDD1: Operating Current: One Bank Operation, ACT- RD- PRE
1. General test condition
a) Only one bank is accessed with tRC,MIN
b) Burst Mode, Address and Control inputs on NOP adge are changing once per clock cycle
c) 50% of data changing at every burst
d) IOUT = 0 mA
2. Timing patterns
a) DDR333 (166 MHz, CL = 2.5): tCK = 6 ns, BL = 4, tRCD = 3 × tCK, tRC = 10 × tCK, tRAS = 7 × tCK
Setup: A0 N N R0 N N N P0 N N
Read : A0 N N R0 N N N P0 N N - repeat the same timing with random address changing
b) DDR400A (200 MHz, CL = 2.5): tCK = 5 ns, BL = 4, tRCD = 3 × tCK, tRC = 11 × tCK, tRAS = 8 × tCK
Setup: A0 N N R0 N N N N P0 N N
Read : A0 N N R0 N N N N P0 N N - repeat the same timing with random address changing
c) DDR500 (250 MHz, CL = 3): tCK =4 ns, BL =4, tRCD = 3 × tCK, tRC = 13 × tCK, tRAS = 10 × tCK
Setup: A0 N N R0 N N N N N N P0 N N
Read : A0 N N R0 N N N N N N P0 N N - repeat the same timing with random address changing
IDD7: Operating Current: Four Bank Operation
1. General test condition
a) Four banks are being interleaved with tRCMIN
b) Burst Mode, Address and Control inputs on NOP edge are not changing
c) 50% of data changing at every burst
d) IOUT = 0 mA
2. Timing patterns
a) DDR333 (166 MHz, CL = 2.5): tCK = 6 ns, BL = 4, tRRD = 2 × tCK, tRCD = 3 × tCK, tRAS = 7 × tCK, tRC = 10 × tCK
Setup: A0 N A1 RA0 A2 RA1 A3 RA2 N RA3
Read : A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 - repeat the same timing with random address changing
b) DDR400A (200 MHz, CL = 2.5): tCK = 5 ns, BL = 4, tRRD = 2 × tCK, tRCD = 3 × tCK, tRAS = 8 × tCK, tRC = 11 × tCK
Setup: A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 N N N
Read : A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 N N N - repeat the same timing with random address changing
c) DDR500 (250Mhz, CL=3): tCK = 4 ns, BL=4, tRRD = 2 × tCK, tRCD = 3 × tCK , tRAS = 10 × tCK, tRC = 13 × tCK
Setup: A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 N N N
Read : A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 N N N - repeat the same timing with random address changing
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Internet Data Sheet
HYB25DC256163CE
256-Mbit Double-Data-Rate SGRAM
5
Package Outlines
There is package TSOPII-66 type used for this product family.
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EDUS UR WU XV LR QRI PD[ Notes
1. Drawing according to ISO 8015
2. Dimensions in mm
3. General tolerances +/- 0.15
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“ “ ƒ “
ƒ “ Package Outline PG-TSOPII-66
Internet Data Sheet
HYB25DC256163CE
256-Mbit Double-Data-Rate SGRAM
List of Figures
Figure 1
Figure 2
Figure 3
Chip Configuration PG-TSOPII-66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
AC Output Load Circuit Diagram / Timing Reference Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Package Outline PG-TSOPII-66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
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Internet Data Sheet
HYB25DC256163CE
256-Mbit Double-Data-Rate SGRAM
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering Information for Lead free Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Chip Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Abbreviations for Pin Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Abbreviations for Buffer Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Burst Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Truth Table 1a: Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Truth Table 1b: DM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Truth Table 2: Clock Enable (CKE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Truth Table 3: Current State Bank n - Command to Bank n (same bank) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Truth Table 4: Current State Bank n - Command to Bank m (different bank). . . . . . . . . . . . . . . . . . . . . . . . . . 14
Truth Table 5: Concurrent Auto Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Input and Output Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Electrical Characteristics and DC Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
AC Timing - Absolute Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
IDD Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
IDD Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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Internet Data Sheet
HYB25DC256163CE
256-Mbit Double-Data-Rate SGRAM
Table of Contents
1
1.1
1.1.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Chip Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4
4.1
4.2
4.3
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
16
16
18
24
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
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03292006-SR4U-HULB
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Internet Data Sheet
Edition 2007-01
Published by Qimonda AG
Gustav-Heinemann-Ring 212
D-81739 München, Germany
© Qimonda AG 2007.
All Rights Reserved.
Legal Disclaimer
The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics
(“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind,
including without limitation warranties of non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office.
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in question please
contact your nearest Qimonda Office.
Under no circumstances may the Qimonda product as referred to in this Internet Data Sheet be used in
1. Any applications that are intended for military usage (including but not limited to weaponry), or
2. Any applications, devices or systems which are safety critical or serve the purpose of supporting, maintaining, sustaining
or protecting human life (such applications, devices and systems collectively referred to as "Critical Systems"), if
a) A failure of the Qimonda product can reasonable be expected to - directly or indirectly (i) Have a detrimental effect on such Critical Systems in terms of reliability, effectiveness or safety; or
(ii) Cause the failure of such Critical Systems; or
b) A failure or malfunction of such Critical Systems can reasonably be expected to - directly or indirectly (i) Endanger the health or the life of the user of such Critical Systems or any other person; or
(ii) Otherwise cause material damages (including but not limited to death, bodily injury or significant damages to
property, whether tangible or intangible).
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