Siemens HYB3164160ATL-60 4m x 16-bit dynamic ram Datasheet

4M x 16-Bit Dynamic RAM
( 8k, 4k & 2k Refresh)
HYB 3164160AT(L) -40/-50/-60
HYB 3165160AT(L) -40/-50/-60
HYB 3166160AT(L) -40/-50/-60
Advanced Information
•
4 194 304 words by 16-bit organization
•
0 to 70 °C operating temperature
•
Fast Page Mode operation
•
Performance:
40
50
60
ns
tCAC
CAS access time
10
13
15
ns
tAA
Access time from address
20
25
30
ns
tRC
Read/write cycle time
75
90
110
ns
tPC
Fast page mode cycle time
30
35
40
ns
•
Low power dissipation:
•
•
-60
RAS access time
Single + 3.3 V (± 0.3V) power supply
•
•
-50
tRAC
•
•
-40
-40
-50
-60
HYB3166160AT(L)
900
558
396
mW
HYB3165160AT(L)
756
468
324
mW
HYB3164160AT(L)
612
378
270
mW
7.2 mW standby (TTL)
3.24 mW standby (MOS)
720 µW standby for L-version
Read, write, read-modify-write, CAS-before-RAS refresh (CBR),
RAS-only refresh, hidden refresh and self refresh (L-version only)
2 CAS / 1 WE byte control
8192 refresh cycles /128 ms , 13 R/ 9C addresses (HYB 3164160AT)
4096 refresh cycles / 64 ms , 12 R/ 10C addresses (HYB 3165160AT)
2048 refresh cycles / 32 ms , 11 R/ 11C addresses (HYB 3166160AT)
256 msec refresh period for L-versions
Plastic Package:
P-TSOPII-50 400 mil
Semiconductor Group
1
6.97
HYB3164(5/6)160AT(L)-40/-50/-60
4M x 16-DRAM
This device is a 64 MBit dynamic RAM organized 4 194 304 by 16 bits. The device is fabricated on
an advanced second generation 64Mbit 0,35µm-CMOS silicon gate process technology. The circuit
and process design allow this device to achieve high performance and low power dissipation. This
DRAM operates with a single 3.3 +/-0.3V power supply and interfaces with either LVTTL or
LVCMOS levels. Multiplexed address inputs permit the HYB 3164(5)160AT to be packaged in a 400
mil wide TSOP-50 package. These packages provide high system bit densities and are compatible
with commonly used automatic testing and insertion equipment. The HYB3164(5/6)160ATL parts
(L-version) have a very low power „sleep mode“ supported by Self Refresh.
Ordering Information
Type
Ordering
Code
Package
Descriptions
8k-refresh versions:
HYB 3164160AT-40
P-TSOPII-50
400 mil
DRAM (access time 40 ns)
HYB 3164160AT-50
P-TSOPII-50
400 mil
DRAM (access time 50 ns)
HYB 3164160AT-60
P-TSOPII-50
400 mil
DRAM (access time 60 ns)
HYB 3164160ATL-50
P-TSOPII-50
400 mil
DRAM (access time 50 ns)
HYB 3164160ATL-60
P-TSOPII-50
400 mil
DRAM (access time 60 ns)
HYB 3165160AT-40
P-TSOPII-50
400 mil
DRAM (access time 40 ns)
HYB 3165160AT-50
P-TSOPII-50
400 mil
DRAM (access time 50 ns)
HYB 3165160AT-60
P-TSOPII-50
400 mil
DRAM (access time 60 ns)
HYB 3165160ATL-50
P-TSOPII-50
400 mil
DRAM (access time 50 ns)
HYB 3165160ATL-60
P-TSOPII-50
400 mil
DRAM (access time 60 ns)
HYB 3166160AT-40
P-TSOPII-50
400 mil
DRAM (access time 40 ns)
HYB 3166160AT-50
P-TSOPII-50
400 mil
DRAM (access time 50 ns)
HYB 3166160AT-60
P-TSOPII-50
400 mil
DRAM (access time 60 ns)
HYB 3166160ATL-50
P-TSOPII-50
400 mil
DRAM (access time 50 ns)
HYB 3166160ATL-60
P-TSOPII-50
400 mil
DRAM (access time 60 ns)
4k-refresh versions:
2k-refresh versions:
Semiconductor Group
2
HYB3164(5/6)160AT(L)-40/-50/-60
4M x 16-DRAM
Pin Configuration
P-TSOPII-50 (400 mil)
O
VCC
I/O1
I/O2
I/O3
I/O4
VCC
I/O5
I/O6
I/O7
I/O8
N.C.
VCC
WE
RAS
N.C.
N.C.
N.C.
N.C.
A0
A1
A2
A3
A4
A5
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
.
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
VSS
I/O16
I/O15
I/O14
I/O13
VSS
I/O12
I/O11
I/O10
I/O9
N.C.
VSS
.
LCAS
UCAS
OE
N.C.
N.C.
A12/N.C. *
A11/N.C.**
A10
A9
A8
A7
A6
VSS
* Pin 33 is A12 for HYB 3164160AT(L) and N.C. for HYB 3165(6)160AT(L)
** Pin 32 is A11 for HYB 3164(5)160AT(L) and N.C. for HYB 3166160AT(L)
Pin Names
A0-A12
Address Inputs for 8k-refresh version HYB 3164160AT(L)
A0-A11
Address Inputs for 4k-refresh version HYB 3165160AT(L)
A0-A10
Address Inputs for 2k-refresh version HYB 3166160AT(L)
RAS
Row Address Strobe
OE
Output Enable
I/O1-I/O16
Data Input/Output
UCAS,LCAS
Column Address Strobe
WE
Read/Write Input
Vcc
Power Supply ( + 3.3V)
Vss
Ground
Semiconductor Group
3
HYB3164(5/6)160AT(L)-40/-50/-60
4M x 16-DRAM
TRUTH TABLE
FUNCTION
RAS
LCAS
UCAS
WE
OE
ROW
ADD
COL
ADD
I/O1I/O16
Standby
H
H-X
H-X
X
X
X
X
High Impedance
Read:Word
L
L
H
H
L
ROW
COL
Data Out
Read:Lower Byte
L
L
H
H
L
ROW
COL
Lower Byte:Data Out
Upper-Byte:High-Z
Read:Upper Byte
L
H
L
H
L
ROW
COL
Lower Byte:High-Z
Upper Byte:Data Out
Write:Word
(Early-Write)
L
L
L
L
X
ROW
COL
Data In
Write:Lower Byte
(Early-Write)
L
L
H
L
X
ROW
COL
Lower Byte:Data Out
Upper-Byte:High-Z
Write:Upper Byte
(Early Write)
L
H
L
L
X
ROW
COL
Lower Byte:High-Z
Upper Byte:Data Out
Read-ModifyWrite
L
L
L
H-L
L-H
ROW
COL
Data Out, Data In
Fast Page Mode
Read (Word)
1st
Cycle
L
H-L
H-L
H
L
ROW
COL
Data Out
Fast Page Mode
Read (Word)
2nd
Cycle
L
H-L
H-L
H
L
n/a
COL
Data Out
Fast Page Mode
1st
Early Write(Word) Cycle
L
H-L
H-L
L
X
ROW
COL
Data In
Fast Page Mode
2nd
Early Write(Word) Cycle
L
H-L
H-L
L
X
n/a
COL
Data In
Fast Page Mode
RMW
1st
Cycle
L
H-L
H-L
H-L
L-H
ROW
COL
Data Out, Data In
Fast Page Mode
RMW
2st
Cycle
L
H-L
H-L
H-L
L-H
n/a
COL
Data Out, Data In
RAS only refresh
L
H
H
X
X
ROW
n/a
High Impedance
CAS-before-RAS
refresh
H-L
L
L
H
X
X
n/a
High Impedance
Test Mode Entry
H-L
L
L
L
X
X
n/a
High Impedance
Hidden Refresh
(Read)
L-HL
L
L
H
L
ROW
COL
Data Out
Hidden Refresh
(Write)
L-HL
L
L
L
X
ROW
COL
Data In
Semiconductor Group
4
HYB3164(5/6)160AT(L)-40/-50/-60
4M x 16-DRAM
I/O1 I/O2
I/O16
WE
UCAS
LCAS
&
.
.
Data in
Buffer
No. 2 Clock
Generator
9
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
16
Column
Address
Buffer(9)
9
Data out
Buffer
16
Column
Decoder
Refresh
Controller
Sense Amplifier
I/O Gating
Refresh
Counter (13)
512
x16
13
Row
13
RAS
Address
Buffers(13)
Row
Decoder 8192
13
No. 1 Clock
Generator
Block Diagram for HYB 3164160AT(L)
Semiconductor Group
OE
5
Memory Array
8192x512x16
16
HYB3164(5/6)160AT(L)-40/-50/-60
4M x 16-DRAM
I/O1 I/O2
I/O16
WE
UCAS
LCAS
&
.
.
Data in
Buffer
No. 2 Clock
Generator
10
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
16
Column
Address
Buffer(10)
10
Data out
Buffer
16
Column
Decoder
Refresh
Controller
Sense Amplifier
I/O Gating
Refresh
Counter (12)
1024
x16
12
Row
12
RAS
Address
Buffers(12)
Row
Decoder 4096
12
No. 1 Clock
Generator
Block Diagram for HYB 3165160AT(L)
Semiconductor Group
OE
6
Memory Array
4096x1024x16
16
HYB3164(5/6)160AT(L)-40/-50/-60
4M x 16-DRAM
I/O1 I/O2
I/O16
WE
UCAS
LCAS
&
.
.
Data in
Buffer
No. 2 Clock
Generator
11
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
16
Column
Address
Buffer(11)
11
Data out
Buffer
16
Column
Decoder
Refresh
Controller
Sense Amplifier
I/O Gating
Refresh
Counter (11)
2048
x16
11
Row
11
RAS
Address
Buffers(11)
Row
Decoder 2048
11
No. 1 Clock
Generator
Block Diagram for HYB 3166160AT(L)
Semiconductor Group
OE
7
Memory Array
2048x2048x16
16
HYB3164(5/6)160AT(L)-40/-50/-60
4M x 16-DRAM
Absolute Maximum Ratings
Operating temperature range..............................................................................................0 to 70 °C
Storage temperature range.........................................................................................– 55 to 150 °C
Input/output voltage..................................................................................-0.5 to min (Vcc+0.5,4.6) V
Power supply voltage....................................................................................................-0.5V to 4.6 V
Power dissipation......................................................................................................................1.3 W
Data out current (short circuit)..................................................................................................50 mA
Note
Stresses above those listed under „Absolute Maximum Ratings“ may cause permanent damage of
the device. Exposure to absolute maximum rating conditions for extended periods may effect device
reliability.
DC Characteristics
TA = 0 to 70 °C, VSS = 0 V, VCC = 3.3 V ± 0.3 V
Parameter
Symbol
Limit Values
min.
max.
Unit Note
Input high voltage
VIH
2.0
Vcc+0.3
V
1)
Input low voltage
VIL
– 0.3
0.8
V
1)
Output high voltage (LVTTL)
Output „H“ level voltage (Iout = -2mA)
VOH
2.4
–
V
Output low voltage (LVTTL)
Output „L“level voltage (Iout = +2mA)
VOL
–
0.4
V
Output high voltage (LVCMOS)
Output „H“ level voltage (Iout = -100uA)
VOH
Vcc-0.2 -
V
Ouput low voltage (LVCMOS)
Output „L“ level voltage (Iout = +100uA)
VOL
-
0.2
V
Input leakage current,any input
II(L)
–2
2
µA
IO(L)
–2
2
µA
(0 V < Vin < Vcc , all other pins = 0 V
Output leakage current
(DO is disabled, 0 V < Vout < Vcc )
Semiconductor Group
8
HYB3164(5/6)160AT(L)-40/-50/-60
4M x 16-DRAM
DC-Characteristics (cont’d)
TA = 0 to 70 °C, VSS = 0 V, VCC = 3.3 V ± 0.3 V
Parameter
Symbol
refresh version
2k
4k
Unit Note
8k
ICC1
Operating Current
-40 ns version
-50 ns version
-60 ns version
250
210
170
155
130
105
110
90
75
mA
mA
mA
2) 3) 4)
2
2
2
mA
–
250
210
170
155
130
105
110
90
75
mA
mA
mA
2) 4)
70
60
50
70
60
50
70
60
50
mA
mA
mA
2) 3) 4)
ICC5
900
900
900
µA
–
ICC5
200
200
200
µA
–
ICC6
CAS Before RAS Refresh Current
-40 ns version
-50 ns version
-60 ns version
250
210
170
155
130
105
155
130
105
mA
mA
mA
2) 4)
400
400
400
µA
(RAS, CAS, address cycling: tRC = tRC min.)
ICC2
Standby Current
(RAS=CAS= Vih)
RAS Only Refresh Current:
-
ICC3
-40 ns version
-50ns version
-60 ns version
(RAS cycling: CAS = VIH: tRC = tRC min.)
ICC4
Fast Page Mode Current:
-40 ns version
-50 ns version
-60 ns version
(RAS = VIL, CAS, address cycling: tPC=tPC min.)
Standby Current
(RAS=CAS= Vcc-0.2V)
Standby Current (L-Version)
(RAS=CAS= Vcc-0.2V)
(RAS, CAS cycling: tRC = tRC min.)
Self Refresh Current (L-version only)
ICC7
(CBR cycle with tRAS>TRASSmin, CAS held low,
WE = Vcc-0.2V, Address and Din=Vcc-0.2V or 0.2V)
Semiconductor Group
9
HYB3164(5/6)160AT(L)-40/-50/-60
4M x 16-DRAM
AC64-2F
AC Characteristics (note: 6,7,8)
TA = 0 to 70 °C,VCC = 3.3 ± 0.3V
Parameter
-40
Symbol
-50
-60
Unit Note
min.
max. min.
max. min.
max.
tRC
75
–
–
–
tRAS
40
100k 50
100k 60
100k ns
tCAS
10
100k 13
100k 15
100k ns
tRP
25
–
30
–
40
–
ns
CAS precharge time
tCP
10
–
10
–
10
–
ns
Row address setup time
tASR
0
–
0
–
0
–
ns
Row address hold time
tRAH
5
–
7
–
10
–
ns
Column address setup time
tASC
0
–
0
–
0
–
ns
Column address hold time
tCAH
5
–
7
–
10
–
ns
RAS to CAS delay time
tRCD
15
30
17
37
20
45
ns
RAS to column address delay
tRAD
10
20
12
25
15
30
ns
RAS hold time
tRSH
10
–
13
–
15
–
ns
CAS hold time
tCSH
40
–
50
–
60
–
ns
CAS to RAS precharge time
tCRP
5
–
5
–
5
–
ns
tT
1
30
1
30
1
30
ns
Refresh period for 8k-refresh
tREF
–
128
–
128
–
128
ms
Refresh period for 4k-refresh
tREF
–
64
–
64
–
64
ms
Refresh period for 2k-refresh
tREF
–
32
–
32
–
64
ms
Refresh period for L-versions
tREF
–
256
–
256
–
256
ms
Access time from RAS
tRAC
–
40
–
50
–
60
ns
8, 9
Access time from CAS
tCAC
–
10
–
13
–
15
ns
8, 9
Access time from column address
tAA
–
20
–
25
–
30
ns
8, 10
OE access time
tOEA
–
10
–
13
–
15
ns
8
Column address to RAS lead time tRAL
20
–
25
–
30
–
ns
Read command setup time
tRCS
0
–
0
–
0
–
ns
Read command hold time
tRCH
0
–
0
–
0
–
ns
11
Read command hold time
referenced to RAS
tRRH
0
–
0
–
0
–
ns
11
Common Parameters
Random read or write cycle time
RAS pulse width
CAS pulse width
RAS precharge time
Transition time (rise and fall)
90
110
ns
7
Read Cycle
Semiconductor Group
10
HYB3164(5/6)160AT(L)-40/-50/-60
4M x 16-DRAM
AC64-2F
AC Characteristics (cont’d)(note: 6,7,8)
TA = 0 to 70 °C,VCC = 3.3 ± 0.3V
Parameter
-40
Symbol
-50
-60
Unit Note
min.
max. min.
max. min.
max.
tCLZ
0
–
0
–
0
–
ns
8
Output buffer turn-off delay
tOFF
–
10
–
13
–
15
ns
12
Output buffer turn-off delay from
OE
tOEZ
–
10
–
13
–
15
ns
12
Data to OE low delay
tDZO
0
–
0
–
0
–
ns
13
CAS high to data delay
tCDD
10
–
13
–
15
–
ns
14
OE high to data delay
tODD
10
–
13
–
15
–
ns
14
Write command hold time
tWCH
5
–
7
–
10
–
ns
Write command pulse width
tWP
5
–
7
–
10
–
ns
Write command setup time
tWCS
0
–
0
–
0
–
ns
Write command to RAS lead time tR WL
10
–
13
–
15
–
ns
Write command to CAS lead time tC WL
10
–
13
–
15
–
ns
Data setup time
tDS
0
–
0
–
0
–
ns
16
Data hold time
tDH
5
–
7
–
10
–
ns
16
CAS delay time from Din
tDZC
0
–
0
–
0
–
ns
13
Read-write cycle time
tR WC
105
–
126
–
150
–
ns
RAS to WE delay time
tR WD
55
–
68
–
80
–
ns
15
CAS to WE delay time
tC WD
25
–
31
–
35
–
ns
15
Column address to WE delay time tAWD
35
–
43
–
50
–
ns
15
OE command hold time
tOEH
5
–
7
–
10
–
ns
Fast page mode cycle time
tPC
30
–
35
–
40
–
ns
Access time from CAS precharge
tCPA
–
25
–
30
–
35
ns
tRAS
40
200k 50
200k 60
200k ns
tRHPC
25
–
–
–
CAS to output in low-Z
Write Cycle
15
Read-Modify-Write Cycle
Fast Page Mode Cycle
RAS pulse width
CAS precharge to RAS Delay
Semiconductor Group
11
30
35
ns
8
HYB3164(5/6)160AT(L)-40/-50/-60
4M x 16-DRAM
AC64-2F
AC Characteristics (cont’d)(note: 6,7,8)
TA = 0 to 70 °C,VCC = 3.3 ± 0.3V
Parameter
-40
Symbol
-50
-60
min.
max. min.
max. min.
max.
Unit Note
Fast Page Mode Read-Modify-Write Cycle
Fast page mode read-write cycle
time
tPR WC
60
–
71
–
80
–
ns
CAS precharge to WE
tCPWD
40
–
48
–
55
–
ns
CAS setup time
tCSR
5
–
5
–
5
–
ns
CAS hold time
tCHR
5
–
5
–
10
–
ns
RAS to CAS precharge time
tRPC
0
–
0
–
0
–
ns
Write to RAS precharge time
tWRP
5
–
5
–
10
–
ns
Write hold time referenced to RAS tWRH
5
–
5
–
10
–
ns
CAS-before-RAS Refresh Cycle
Self Refresh Cycle (L-version only)
RAS pulse width
tRASS
100k –
100k –
100k –
ns
17
RAS precharge time
tRPS
75
–
90
–
110
–
ns
17
CAS hold time
tCHS
-50
–
-50
–
-50
–
ns
17
Capacitance
TA = 0 to 70 °C,VCC = 3.3 V ± 0.3 V, f = 1 MHz
Parameter
Symbol
Limit Values
min.
max.
Unit
Input capacitance (A0 to A11,A12)
CI1
–
5
pF
Input capacitance (RAS, CAS, WE, OE)
CI2
–
7
pF
I/O capacitance (I/O1-I/O8)
CIO
–
7
pF
Semiconductor Group
12
HYB3164(5/6)160AT(L)-40/-50/-60
4M x 16-DRAM
Notes:
1) All voltages are referenced to VSS.
Vih may overshoot to Vcc + 2.0 V for pulse widths of < 4ns with 3.3V. Vil may undershoot to -2.0V for pulse
width < 4.0 ns with 3.3V. Pulse width measured at 50% points with amplitude measured peak to DC reference.
2) ICC1, ICC3, ICC4 and ICC6 and ICC7 depend on cycle rate.
3) ICC1 and ICC4 depend on output loading. Specified values are measured with the output open.
4) Address can be changed once or less while RAS = Vil.In the case of ICC4 it can be changed once or less
during a fast page mode cycle ( tpc).
5) An initial pause of 100 µs is required after power-up followed by 8 RAS-only-refresh cycles, before proper
device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS
initialization cycles instead of 8 RAS cycles are required.
6) AC measurements assume tT = 5 ns.
7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Also, transition times are
measured between VIH and VIL.
8) Measured with the specified current load and 100 pF at Voh = 2.0 V and Vol = 0.8 V.
9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a
reference point only: If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by
tCAC.
10) Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a
reference point only: If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by
tAA.
11) Either tRCH or tRRH must be satisfied for a read cycle.
12) tOFF (max.) and tOEZ (max.) define the time at which the outputs achieve the open-circuit condition and are
not referenced to output voltage levels.
13) Either tDZC or tDZO must be satisfied.
14) Either tCDD or tODD must be satisfied.
15) tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and the I/O pin
will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD
(min.), tAWD > tAWD (min.) and tCPWD > tCPWD (min.) , the cycle is a read-write cycle and I/O pins will
contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition
of the I/O pins (at access time) is indeterminate.
16) These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in ReadModify-Write cycles.
17) When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM
operation:
If row addresses are being refresh in an evenly distributed manner over the refresh iterval using CBR refresh
cycles, then only one CBR cycle must be performed immediatly after exit from Self Refresh.
If row addresses are being refresh in any other manner (ROR - Distributed/Burst or CBR-Burst) over the
refresh interval, then a full set of row refreshed must be performed immediately before entry to and immediatey
after exit from Self Refresh
Semiconductor Group
13
HYB3164(5/6)160AT(L)-40/-50/-60
4M x 16-DRAM
tRC
tRAS
tRP
V
IH
RAS
VIL
tCSH
V
IH
UCAS
LCAS
VIL
tRAD
tASR
V
Address
AAA
AAAAAAA
IH AAAA
AAAAAAA
AAAA
AAAAAAA
AAA
AAAAAAA
VIL
Row
tRAL
tCAH
tASC
AAAAAAA
AAAAAAA
AAAAAAA
AAAA
AAAAAAA
AAA
AAAAAAA
tCRP
tRSH
tCAS
tRCD
tASR
AAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
AAAAAAAAAAAAAAAAAAAAAAAAAAA
Column
tRCH
tRAH
tRCS
tRRH
V
WE
OE
I/O
(Inputs)
Row
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
IH AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAA
VIL
AAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
V
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
VIL
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAA
AAA
tAA
tOEA
IH AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
tCDD
tDZC
tODD
tDZO
V
AAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AAAAAAAAAAAAAAAAAAAAAAAA
IH AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAA
VIL
AAAA
AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
tCAC
tCLZ
V
OH
I/O
(Outputs) V
Hi Z
OL
tOFF
AAAAAAAAAAAAAAAAAAAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
tOEZ
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AAAAAA
AA
Valid Data Out
Hi Z
tRAC
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAA
AAAA
WL1
“H” or “L”
Read Cycle
Semiconductor Group
14
HYB3164(5/6)160AT(L)-40/-50/-60
4M x 16-DRAM
tRC
tRAS
tRP
V
IH
RAS
VIL
tCSH
tRCD
tRSH
tCAS
V
IH
UCAS
LCAS
VIL
tRAD
tASR
V
Address
IH
VIL
AAAA
AAAAAAA
AAA
AAAA
AAAAAAA
AAA
AAAA
AAAAAAA
AAA
tRAL
AAAA
AAAAAAA
AAA
AAAA
AAAAAAA
AAA
AAAA
AAAAAAA
AAA
tRAH
V
WE
tASR
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAA
AAA
Column
AAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
.
Row
tCWL
tWCS
AAAAAAAAAAAAAAAAAAAAAA
IH AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAA
VIL
tCAH
tASC
Row
tCRP
t WP
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
A
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
A
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
tWCH
tRWL
OE
V AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
IHAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
VIL AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
tDS
I/O
(Inputs)
tDH
V
IH
Valid Data In
VIL
V
OH
I/O
(Outputs) V
Hi Z
OL
AAAA
AAA
AAAA
AAA
AAAA
AAA
AAAA
AAA
AAAA
AAA
AAAA
AAAAAAA
AAA
WL2
“H” or “L”
Write Cycle (Early Write)
Semiconductor Group
15
HYB3164(5/6)160AT(L)-40/-50/-60
4M x 16-DRAM
tRC
tRAS
tRP
V
IH
RAS
VIL
tCSH
tRCD
V
IH
UCAS
LCAS
VIL
tRAD
tASR
tCAH
tASC
V AAAAAAAAA
IHAAAA
AAAAAAAA
AAAAA
A
AAAAAAAA
AAAA
AAAAAAAA
AAAA
AAAA
AAAAAAAA
AAAA
AAAA
AAAAAAAA
AAAA
Address V AAAA
AAAAAAAA
AAAAA
A Row
AAAAAAAAA
IL AAAAAAAAA
tRAL
Column
tASR
AAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
tCWL
tRAH
V
WE
tCRP
tRSH
tCAS
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
IH AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
VIL AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tRWL
tWP
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
.
Row
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAA
tOEH
V
OE
IH AAAAAAAAAAAAAAAAAAAAAAA
VIL
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
tODD
tDS
tOEZ
tDZO
tDZC
I/O
(Inputs)
V
IH AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
VIL
AAAA
AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
AAAA
AAAA
AAAA
AAAA
AA
tCLZ
tOEA
V
OH
I/O
(Outputs) V
Hi-Z
OL
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAA
AAAA
AAAA
AA
AAAA
AAAA
AA
AAAA
AAAA
AAAAAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAA
AAAA
“H” or “L”
Valid Data
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
AAAA
AAA
Hi-Z
WL3
Write Cycle (OE Controlled Write)
Semiconductor Group
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAA
tDH
16
HYB3164(5/6)160AT(L)-40/-50/-60
4M x 16-DRAM
tRWC
tRAS
tRP
V
IH
RAS
tCSH
VIL
tRSH
tCAS
tRCD
V
tCRP
IH
UCAS
LCAS
VIL
tRAH
tCAH
V
IH AAA
AAAA
A
AAAA
Address
VIL
AAAA
AAA
AAAA
A
Row
tASR
tASC
tASR
AAAA
AAAAAA
AA
AAAA
AAAAAA
AA
AAAA
AAAAAA
AA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAA
tCWL
tAWD
Column
tRAD
tCWD
tRWL
tWP
tRWD
V
WE
AAAAAAAAAAAAAAAAAAA
IH AAA
AAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AAA
AAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AAAA
AAAA
AAAA
VIL AAA
AAAAAAAAAAAAAAAAAAA
AAAA
Row
AAAAAAAAAAAAAAAAAAAAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAAAAAAAAAAAAAAAA
AA
tAA
tRCS
tOEH
tOEA
V
OE
IH AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
VIL AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAA
tDS
tDZO
tDZC
tDH
V
I/O
(Inputs)
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAA
A
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAA
A
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
A
AAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAA
AAAA
AAAA
AAAA
AAAA
AA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
IH AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
VIL AAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AAAA
AAA
AAAA
AAA
AAAA
AAA
AAAA
AAA
AAAA
AAA
AAAA
AAAAAAA
AAA
tCLZ
Valid
Data in
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAAAAAAAAAAAAA
AAA
tODD
tCAC
tOEZ
V
OH
AAAA
AA
AAAA
AA Data
AAAA
AAAAAA
AA
AAAA
AAAAAA
AA Out
I/O
(Outputs) VOL
tRAC
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAA
AAAA
“H” or “L”
WL4
Read-Write (Read-Modify-Write) Cycle
Semiconductor Group
17
HYB3164(5/6)160AT(L)-40/-50/-60
4M x 16-DRAM
tRP
tRASP
V
IH
RAS
VIL
tRHCP
tRSH
tCAS
tPC
tCP
tCAS
tRCD
tCAS
V
tCRP
IH
UCAS
LCAS
VIL
tCSH
tRAH
tASR
V
Address
tASC
IH AAAA
AAAAA
A
AAAAA
VIL
tCAH
AAAA
AAAAA
A
AAAAA Row AAAA
AAAAA
A
AAAA
A
AAAA
AAAAA
AAAAA
A
tRAD
tASC
AAAA
AAAAAAAA
AAAAAA
AA
AAAA
AAAAAAAA
AAAAAA
AA
AAAA
AAAA
AAAAAAAAAA
AA
Column
WE
VIL
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
tRCS
IH AAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
AAAA
AAAAAA
AAAA
AAAAAA
AAAA
AAAAAA
tAA
OE
V
AAAAAAAAAAAAAAAAAAAAAAAAAAA
VIL
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
tDZC
tODD
tCAC
tRAC
tCLZ
V
OL
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAA
AAAA
AAAAAA
AAAA
AAAA
AA
AAAA
AAAA
A
AAAA
AAAAAA
tOFF
tOEZ
AAAA
AA
AAAA
AAAA
AA Valid
AAAA
AAAA
AAAAAAA Data Out
AAAA
OH
I/O
(Outputs) V
Row
AAAAAAAAAAAAAAAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
tODD
tCAC
tCLZ
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA Valid
AAAA
AAAAAA
AA Data Out
AAAA
AA
AAAAAAAAAAAAAAAAAAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAAAAAAAAAAAAAA
AAAA
tCDD
tDZO
AAAAA
AA
AAA
AAA
AA
AAA
AA
AAA
AA
AAA
AAAAA
AA
tOFF
tOEZ
tDZC
AAAA
AAAAAAAA
AAAAAAA
AAA
AAAA
AAAAAAAA
AAAAAAA
AAA
AAAA
AAAA
AAA
tRRHAAAAAAAAAAA
tODD
tCAC
tCLZ
AAAAAAAA
AAAAAA
AA
AAAA
AAAA
AAAA
AA
AAAA
AAAA
AA
AAAA
AAAA
AA
AAAA
AAAA
AAAAAAAAAA
AA
tOFF
tOEZ
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA Valid
AAAA
AAAAAA
AA Data Out
AAAA
AA
“H” or “L”
FPM1
Fast Page Mode Read Cycle
Semiconductor Group
tCPA
tAA
tOEA
tDZO
IH AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AAAA
AAAAAA
AAAA
AAAAAA
AAAA
AAAAAA
tCPA
tAA
AAAAAAAAAAAAAAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAAAAAAAAAA
AAAA
tDZC
V
VIL
AAAA
AAAAAAAA
AAAAAAA
AAA
AAAA
AAAAAAAA
AAAAAAA
AAA
AAAA
AAAA
AAAAAAAAAAA
AAA
tRCS
tOEA
tOEA
IH AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
tDZO
I/O
(Inputs)
AAAA
AAAAAAAA
AAAAAA
AAAA
AAAAAAAA
AAAAAA Column
AAAA
AAAAAAAA
AAAAAA
tRCH
tRCS
AAAAAAAAAAAAAAA
tASR
tASC
Column
tRCH
V
tCAH
tCAH
18
HYB3164(5/6)160AT(L)-40/-50/-60
4M x 16-DRAM
tRP
tRAS
V
IH
RAS
VIL
tRSH
tPC
tRCD
tCAS
tCP
tCAS
tCAS
tCRP
V
IH
UCAS
LCAS
VIL
tRAL
tRAH
tCAH
tASR
Address
V
AAAAA
VIL
AAAA
AAAAA
A
AAAA
AAAAA
A
IH AAAA
AAAAA
A
Row
AAAA
AAAAA
A
AAAA
AAAAA
A
AAAA
AAAAA
A
tASC
tASR
tCAH
AAAAAAAAAA
AAAAAAAAAA
tCWL
tWCS
tWCH
AAAAAAAAAAAAAAA
AAAA
IH AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
AAAAAAAAA
AAAAAAAAA
tWP
AAAA
AAAAAAAA
AAAAAAA
AAA
AAAA
AAAAAAAA
AAAAAAA
AAA
AAAA
AAAA
AAAAAAAAAAA
AAA
tWCS
tCWL
tRWL
tWCH
tWCH
tWP AAAAAAAAAAAAA tWP AAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AAAAAAAAAAAAAAAAAAAAAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
VIL
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
V
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
IH AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
VIL AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
tDH
V
AAAAAAAAAAA
AAAA
AAAA
AAAA
AAA
IH AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
V AAAA
AAAAAAAAAAAAAAA
AAA
IL
Valid
Data In
tDH
tDH
tDS
tDS
I/O
(Inputs)
tASC
AAAAAAAAAA
AAAAAAAAAA
tCWL
V
OE
tASC
AAAAAAAAAA
AAAAAAAAAA
AAAAAAAAA
Column AAAA
AAAAAAAA
AAAAAA
AA Column AAAA
AAAAAAAA
AAAAAA
AA Column AAAA
AAAAAAAA
AAAAAA Column
AAAA
AAAA
AA
AAAA
AAAA
AA
AAAA
AAAAAAAAAA
AAAAAAAAAA
AAAAAAAA
AAAAAA
tRAD
tWCS
WE
tCAH
AAAAAAAAA
AAAA
AAAA
AA
AAAA
AAAA
AAAA
AAAA
AA
AAAA
AAAA
AAAA
AAAAAAAA
AAAAAA
Valid
Data In
tDS
AAAAAAAAAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAA
AAAA
AAAA
AAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAAAAAAAAA
AAA
Valid
Data In
AAAAAAAAAAAAAAAAAAAAAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAAAAAAAAAAAAAAAAA
AAA
V
OH
I/O
(Outputs) V
HI-Z
OL
AAAA
AAA
AAAA
AAA
AAAA
AAA
AAAA
AAA
AAAA
AAA
AAAA
AAAAAAA
AAA
“H” or “L”
FPM2
Fast Page Mode Early Write Cycle
Semiconductor Group
19
20
Data
Out
tDS
tDH
Data
Out
tOEZ
Data
Out
tDS
tOEZ tDH
AAAA
AA
AAAA
AAAAAA
AA
“H” or “L”
tRAC
V
OH
I/O
(Outputs) V
AAAA
AAA
AAAA
AAA
AAAA
AAA
AAAA
AAA
AAAA
AAAAAAA
AAA
AAAA
AAAAAAA
AAA
OL
tODD
tOEH
tAA
AAAA
AAAAAA
AA
AAAA
AAAAAA
AA
tCAC
I/O
(Inputs) V IL
IH
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AAAAAA
AA
AAAA
AA
AAAA
AAAAAA
AA
V
tDS
tDH
tOEZ
tCAC
tCLZ
AAAA
AAAAAA
AA
AAAA
AAAAAA
AA
AAAAAA
AA
AAAA
tDZC
tCLZ
tDZO
V IL
IH
OE
V
tAA
tOEA
tAWD
V IL
IH
WE
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AAAAAA
AA
AAAA
AA
AAAA
AA
AAAA
AAAAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AAAAAA
AA
AAAA
AA
AAAA
AAAAAA
AA
tOEH
Data In
AAAAA
AAAA
AAAAAA
Data In
tOEA
tAWD
tWP
AAAAAA
AAAA
AA
AAAA
AAAAAA
AA
AAAA
AAAAAA
AA
AAAA
AAAAAA
AA
AAAA
AAAAAA
AA
AAAAAA
AA
AAAA
AAAA
AAAAAA
AA
tCPA
tDZC
tODD
tDZC
tCLZ
tCPA
AAAAAA
AAAA
AA
AAAA
AAAAAA
AA
AAAA
AAAAAA
AA
AAAA
AAAAAA
AA
AAAAAA
AAAA
AAAAAA
AA
AAAAAA
tAA
Data In
tODD
tWP
tOEA
tWP
tCWL
tAWD
tCPWD
tCWD
tCPWD
tCWD
tCWL
tRWD
tCWD
Row
V IL
IH
V
Address
tASR
V IL
IH
UCAS
LCAS
V
AAAA
AA
AAAA
AAAAAA
AA
AAAA
AA
AAAA
AAAAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AAAAAA
AA
AAAA
AA
AAAA
AAAAAA
AA
Fast Page Mode Read-Modify-Write Cycle
Semiconductor Group
AAAA
AAAAAA
AA
AAAAAA
AAAA
AAAAAA
AA
AAAAAA
AAAAAA
AAAA
AA
AAAA
AAAAAA
AA
AAAA
AAAAAA
AA
AAAA
AAAAAA
AA
AAAA
AAAAAA
AAAAA
AAAAA
AAAA
AAAAAA
V
tASC
Column
tCAH
tRAH
tRAD
tRCD
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AAAAAA
AA
tRCS
tASC
Column
Address
tCAH
tCP
AAAAAA
AAAAAA
AAAA
AA
AAAA
AAAAAA
AA
AAAA
AAAAAA
AA
AAAA
AAAAAA
AA
AAAA
AA
AAAA
AAAAAA
AA
AAAA
AAAAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AAAAAA
AA
tCAS
tCSH
V IL
IH
RAS
Column
tASC
tPRWC
tCAS
tRAS
V
AAAAAA
AAAA
AA
AAAA
AAAAAA
AA
AAAA
AAAAAA
AA
AAAA
AAAAAA
AA
AAAA
AA
AAAA
AAAAAA
AA
AAAA
AAAAAA
AA
AAAA
AAAAAA
AA
AAAA
AAAAAA
AA
AAAA
AAAAAA
AA
AAAA
AAAAAA
AA
tRWL
tCWL
Row
tASR
tRAL
tCAH
tCAS
tRSH
tCRP
tRP
AAAAAA
AA
AAAA
AAAAAA
AAAAAA
AAAA
AAAAAA
AA
AAAAAA
AAAA
AAAAAA
AA
AAAAAA
AAAA
AAAAAA
AA
AAAAAA
AAAAAA
AAAA
AAAAAA
AA
AAAAAA
AAAAAA
AAAA
AAAAAA
AA
AAAAAA
AAAA
AAAAAA
AA
AAAAAA
AAAAAA
AAAAAA
AA
AAAA
AAAAAA
AAAAAA
AAAA
AAAAAA
AA
AAAAAA
AAAAAA
AAAA
AAAAAA
AA
AAAAAA
AAAA
AAAAAA
AA
AAAAAA
AAAAAA
AAAA
AAAAAA
AA
AAAAAA
AAAAAA
AAAAAA
AA
AAAA
AAAAAA
AAAA
AAAAAA
AA
AAAAAA
AAAAAA
AAAA
AAAAAA
AA
AAAAAA
AAAAAA
AAAA
AAAAAA
AA
AAAAAA
AAAA
AAAAAA
AA
AAAAAA
AAAA
AAAAAA
AA
AAAAAA
AAAA
AAAAAA
AA
AAAAAA
AAAAAA
AAAA
AAAAAA
AA
AAAAAA
AAAAAA
AAAA
AAAAAA
AA
AAAAAA
AAAA
AAAAAA
AA
AAAAAA
AAAAAA
AAAA
AAAAAA
AA
AAAAAA
AAAAAA
AAAA
AAAAAA
AA
AAAAAA
tOEH
HYB3164(5/6)160AT(L)-40/-50/-60
4M x 16-DRAM
HYB3164(5/6)160AT(L)-40/-50/-60
4M x 16-DRAM
tRC
tRAS
tRP
V
IH
RAS
VIL
tCRP
tRPC
V
AAAA
AAAAAAAA
AAAAAA
AAAAAAAAA
AAAAAAAAA
AAAA
AAAAAAAA
AAAAAA
AAAAAAAAA
IH
UCAS
LCAS
VIL
tRAH
tASR
tASR
V
Address
AAAAAAAA
IH AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAA
VIL
AAAA
AAAAAAAA
AAAAAAAA
AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAA
Row
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
V
OH
I/O
(Outputs) V
HI-Z
OL
AAAA
AAAAAAAA
AAAA
AAAA
AAAAAAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAA
AAAA
“H” or “L”
WL9
RAS-Only Refresh Cycle
Semiconductor Group
21
Row
HYB3164(5/6)160AT(L)-40/-50/-60
4M x 16-DRAM
tRC
tRP
tRAS
tRP
V
RAS
IH
VIL
tRPC
tCSR
tCRP
tCP
UCAS
LCAS
tRPC
tCHR
V
AAAA
AAAAAA
AA
AAAAAA
AAAAAA
AAAA
AAAAAA
AA
AAAAAA
IH
VIL
tWRP
tWRH
WE
V
AAAAAAAAAAAAAAAA
VIL
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
IH AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
tOEZ
V
OE
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAA
AA
IH
VIL
tCDD
V
AAAA
AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
IH
I/O
(Inputs) V
IL
tODD
V
OH
I/O
(Outputs)VOL
HI-Z
tOFF
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAA
AAAA
“H” or “L”
WL10
CAS-Before-RAS Refresh Cycle
Semiconductor Group
22
HYB3164(5/6)160AT(L)-40/-50/-60
4M x 16-DRAM
tRC
tRC
RAS
tRP
tRAS
V
tRP
tRAS
IH
VIL
tRSH
tRCD
tCRP
tCHR
V
UCAS
LCAS
IH
tRAD
VIL
tWRP
tASC
tASR
Address
V AAAAAAA
IHAAAA
AAAAAAA
AAA
AAAAAAA
AAA
VIL AAAA
AAAA
AAAAAAA
AAA
tRAH
AAAAA
AAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAA Column AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
Row AAAA
AAAAA
AAAAAAAA
AAAA
AAAA
AAAAA
A
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
Row
tRRH
tRCS
WE
tASR
tWRH
tCAH
V AAAAAAAAAAAAAAAA
IHAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AAAA
VIL AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AAAAAA
AAAA
AAAAAA
AA
AAAA
AAAAAA
AA
AAAA
AAAAAA
AA
tAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
tOEA
OE
V AAAAAAAAAAAAAAAAAAAAAAAAAAAAA
IHAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAA
A
VIL AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAA
A
tDZC
tCDD
tDZO
V
I/O
(Inputs)
IH
VIL
AAAA
AAAA
AAAA
AAAA
A
AAAA
AAAA
AAAA
AAAA
A
AAAA
AAAA
AAAA
AAAA
A
AAAA
AAAA
AAAA
AAAA
A
AAAA
AAAA
AAAA
AAAA
A
AAAA
AAAA
AAAA
AAAA
AAAAAAAAAAAAAAAAA
A
tODD
tCAC
tOFF
tCLZ
tOEZ
tRAC
V
AAAA
AA
AAAA
AAAA
AA
AAAA
AAAA
AAAAAA
OH
I/O
(Outputs) V
OL
AAAA
AAA
AAAA
AAA
AAAA
AAA
AAAA
AAA
AAAA
AAA
AAAA
AAAAAAA
AAA
Valid Data Out
“H” or “L”
HI-Z
WL11
Hidden Refresh Cycle (Read)
Semiconductor Group
AAAA
AAAA
AAAA
AAAA
AA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
A
AAAA
AAAA
AAAA
AAAA
AAAAAAAAAAAAAAAAAA
23
HYB3164(5/6)160AT(L)-40/-50/-60
4M x 16-DRAM
tRC
tRC
tRP
tRAS
V
RAS
IH
tRAS
tRP
VIL
tRCD
tRSH
tCHR
tCRP
V
UCAS
LCAS
IH
tRAD
VIL
tRAH
tASC
tCAH
tASR
Address
V AAAAAAA
IHAAAA
AAAAAAA
AAA
AAAAAAA
AAA
VIL AAAA
AAAA
AAAAAAA
AAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AAAAA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AAAA
AAAAA
Row AAAA
Column AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
AAAA
AAAA
AAAAA
A
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
tWCS
V
WE
tASR
AAAAAAAAAAAAAAAAAAA
IH AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
AAAA
AAAA
AAAA
VIL AAAA
AAAAAAAAAAAAAAAAAAA
AAA
tDS
tWRP
tWCH
tWP
AAAAAAAA
AAAA
AAAAAAAA
AAAA
AAAA
AAAAAAAA
AAAA
AAAA
AAAAAAAA
AAAA
AAAAAAAAAA
AAAA
AAAAAAAAAA
IH AAAA
AAAAAAAAAAAAAA
V
IL
AAAA
AAAA
AAAA
AAAAAAAA
AAAAAA
AA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
tWRH
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAA
tDH
V
I/O
(Input)
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
Valid Data
V
OH
I/O
(Output) V
OL
AAAA
AAAA
AAAA
AAAAAAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAA
AAAA
HI-Z
“H” or “L”
WL12
Hidden Refresh Write Cycle
Semiconductor Group
Row
24
HYB3164(5/6)160AT(L)-40/-50/-60
4M x 16-DRAM
tRP
tRASS
tRPS
V
RAS
IH
VIL
tRPC
tCP
V
UCAS
LCAS
tCRP
tCHS
tCSR
AAAAAAAAA
AAAAAAAAA
AAAAAAAAA
AAAA
AAAAAAAA
AAAAAA
AAAAAAAAA
IH
VIL
tWRP
tWRH
V
WE
AAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
AAAAAAAAAAAAAAA
IH AAAA
AAAAAAAAAAAAAAAAAAA
VIL
V
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
IH
OE
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAA
A
AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAA
A
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
VIL
tCDD
V
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
tODD
IH
I/O
(Inputs) V
IL
tOEZ
V
OH
I/O
(Outputs) VOL
HI-Z
tOFF
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAA
AAAA
“H” or “L”
WL13
CAS-before-RAS Self Refresh („Sleep Mode“)
Semiconductor Group
25
HYB3164(5/6)160AT(L)-40/-50/-60
4M x 16-DRAM
Package Outlines
Plastic Package P-TSOPII-50
(400 mil width, 0.8 mm lead pitch, thin small outline, SMD)
Semiconductor Group
26
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