Siemens HYB3164800T-60 8m x 8-bit dynamic ram Datasheet

8M x 8-Bit Dynamic RAM
(4k & 8k Refresh)
HYB 3164800J/T -50/-60
HYB 3165800J/T -50/-60
Preliminary Information
•
•
•
•
•
•
•
•
•
•
•
8 388 608 words by 8-bit organization
0 to 70 ˚C operating temperature
Fast access and cycle time
RAS access time:
50 ns (-50 version)
60 ns (-60 version)
Cycle time:
90 ns (-50 version)
110 ns (-60 version)
CAS access time:
13 ns ( -50 version)
15 ns ( -60 version)
Fast page mode cycle time
35 ns (-50 version)
40 ns (-60 version)
Single + 3.3 V (± 0.3V) power supply
Low power dissipation
max. 396 active mW ( HYB 3164800J/T-50)
max. 360 active mW ( HYB 3164800J/T-60)
max. 504 active mW ( HYB 3165800J/T-50)
max. 432 active mW ( HYB 3165800J/T-60)
7.2 mW standby (TTL)
720 W standby (MOS)
Read, write, read-modify-write, CAS-before-RAS refresh (CBR),
RAS-only refresh, hidden refresh and self refresh modes
Fast page mode capability
8192 refresh cycles/128 ms , 13 R/ 10C addresses (HYB 3164800J/T)
4096 refresh cycles/ 64 ms , 12 R/ 11C addresses (HYB 3165800J/T)
Plastic Package:
P-SOJ-34-1
500 mil
HYB 3164(5)800J
P-TSOPII-34-1 500 mil
HYB 3164(5)800T
Semiconductor Group
121
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
This device is a 64 MBit dynamic RAM organized 8 388 608 by 8 bits. The device is fabricated in
SIEMENS/IBM’s most advanced first generation 64Mbit CMOS silicon gate process technology.
The circuit and process design allow this device to achieve high performance and low power
dissipation. This DRAM operates with a single 3.3 +/-0.3V power supply and interfaces with either
LVTTL or LVCMOS levels. Multiplexed address inputs permit the HYB 3164(5)800J/T to be
packaged in a 500 mil wide SOJ-34 or TSOP-34 plastic package. These packages provide high
system bit densities and are compatible with commonly used automatic testing and insertion
equipment.
Ordering Information
Type
Ordering
Code
Package
HYB 3164800J-50
on request
P-SOJ-34-1
500 mil DRAM (access time 50 ns)
HYB 3164800J-60
on request
P-SOJ-34-1
500 mil DRAM (access time 60 ns)
HYB 3164800T-50
on request
P-TSOPII-34-1
500 mil DRAM (access time 50 ns)
HYB 3164800T-60
on request
P-TSOPII-34-1
500 mil DRAM (access time 60 ns)
HYB 3165800J-50
on request
P-SOJ-34-1
500 mil DRAM (access time 50 ns)
HYB 3165800J-60
on request
P-SOJ-34-1
500 mil DRAM (access time 60 ns)
HYB 3165800T-50
on request
P-TSOPII-34-1
500 mil DRAM (access time 50 ns)
HYB 3165800T-60
on request
P-TSOPII-34-1
500 mil DRAM (access time 60 ns)
Pin Names
A0-A12
Address Inputs for HYB 3164800J/T
A0-A11
Address Inputs for HYB 3165800J/T
RAS
Row Address Strobe
OE
Output Enable
I/O1-I/O8
Data Input/Output
CAS
Column Address Strobe
WRITE
Read/Write Input
Vcc
Power Supply ( + 3.3V)
Vss
Ground
Semiconductor Group
122
Descriptions
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
P-SOJ-34-1 (500 mil)
P-TSOPII-34-1 (500 mil)
Pin Configuration
Semiconductor Group
123
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
TRUTH TABLE
FUNCTION
RAS
CAS
WRITE
OE
ROW
ADDR
COL
ADDR
I/O1I/O8
Standby
H
H-X
X
X
X
X
High Impedance
Read
L
L
H
L
ROW
COL
Data Out
Early-Write
L
L
L
X
ROW
COL
Data In
Delayed-Write
L
L
H-L
H
ROW
COL
Data In
Read-Modify-Write
L
L
H-L
L-H
ROW
COL
Data Out, Data In
1st Cycle
L
H-L
H
L
ROW
COL
Data Out
2nd Cycle
L
H-L
H
L
n/a
COL
Data Out
1st Cycle
L
H-L
L
X
ROW
COL
Data In
2nd Cycle
L
H-L
L
X
n/a
COL
Data In
1st Cycle
L
H-L
H-L
L-H
ROW
COL
Data Out, Data In
2st Cycle
L
H-L
H-L
L-H
n/a
COL
Data Out, Data In
L
H
X
X
ROW
n/a
High Impedance
CAS-before-RAS refresh
H-L
L
H
X
X
n/a
High Impedance
Test Mode Entry
H-L
L
L
X
X
n/a
High Impedance
READ
L-H-L
L
H
L
ROW
COL
Data Out
WRITE
L-H-L
L
L
X
ROW
COL
Data In
Fast Page Mode Read
Fast Page Mode Early
Write
Fast Page Mode RMW
RAS only refresh
Hidden Refresh
Semiconductor Group
124
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
Block Diagram for HYB 3165800J/T
Semiconductor Group
125
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
Block Diagram for HYB 3164800J/T
Semiconductor Group
126
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
Absolute Maximum Ratings
Operating temperature range..............................................................................................0 to 70 ˚C
Storage temperature range.........................................................................................– 55 to 150 ˚C
Input/output voltage..................................................................................-0.5 to min (Vcc+0.5,4.6) V
Power supply voltage....................................................................................................-0.5V to 4.6 V
Power dissipation......................................................................................................................1.0 W
Data out current (short circuit)..................................................................................................50 mA
Note
Stresses above those listed under „Absolute Maximum Ratings“ may cause permanent damage of
the device. Exposure to absolute maximum rating conditions for extended periods may effect device
reliability.
DC Characteristics
TA = 0 to 70 ˚C, VSS = 0 V, VCC = 3.3 V ± 0.3 V, (values in brackets for HYB 3165800J/T)
Parameter
Symbol
Limit Values
min.
max.
Unit Note
Input high voltage
VIH
2.0
Vcc+0.3
V
1)
Input low voltage
VIL
– 0.3
0.8
V
1)
Output high voltage (LVTTL)
Output „H“ level voltage (Iout = -2mA)
VOH
2.4
–
V
Output low voltage (LVTTL)
Output „L“level voltage (Iout = +2mA)
VOL
–
0.4
V
Output high voltage (LVCMOS)
Output „H“ level voltage (Iout = -100uA)
VOH
Vcc-0.2 -
V
Ouput low voltage (LVCMOS)
Output „L“ level voltage (Iout = +100uA)
VOL
-
0.2
V
Input leakage current,any input
II(L)
–2
2
µA
IO(L)
–2
2
µA
–
–
110 (140) mA
100 (120) mA
2) 3) 4)
–
2
–
(0 V < Vin < Vcc , all other pins = 0 V
Output leakage current
(DO is disabled, 0 V < Vout < Vcc )
ICC1
Average Vcc supply current:
-50 ns version
-60 ns version
(RAS, CAS, address cycling: tRC = tRC min.)
Standby Vcc supply current
ICC2
(RAS=CAS= Vih)
Semiconductor Group
127
mA
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
DC Characteristics (cont’d)
TA = 0 to 70 ˚C, VSS = 0 V, VCC = 3.3 V ± 0.3 V, (values in brackets for HYB 3165800J/T)
Parameter
Symbol
Limit Values
Unit Note
min.
max.
–
–
110 (140) mA
100 (120) mA
2) 4)
–
–
85 (85)
75 (75)
mA
mA
2) 3) 4)
ICC5
–
200
A
–
Average Vcc supply current, during CAS-before- ICC6
RAS refresh mode:
-50 ns version
-60 ns version
–
–
110 (140) mA
100 (120) mA
–
400
Average Vcc supply current, during RAS-only
ICC3
refresh cycles:
-50 ns version
-60 ns version
(RAS cycling: CAS = VIH: tRC = tRC min.)
Average Vcc supply current,
during fast page mode:
ICC4
-50 ns version
-60 ns version
(RAS = VIL, CAS, address cycling: tPC=tPC min.)
Standby Vcc supply current
(RAS=CAS= Vcc-0.2V)
2) 4)
(RAS, CAS cycling: tRC = tRC min.)
ICC7
Self Refresh Current
A
Average Power Supply Current during Self Refresh.
(CBR cycle with tRAS>TRASSmin, CAS held low,
WE = Vcc-0.2V, Address and Din=Vcc-0.2V or 0.2V)
Capacitance
TA = 0 to 70 ˚C,VCC = 3.3 V ± 0.3 V, f = 1 MHz
Parameter
Symbol
Limit Values
min.
max.
Unit
Input capacitance (A0 to A11,A12)
CI1
–
5
pF
Input capacitance (RAS, CAS, WRITE, OE)
CI2
–
7
pF
I/O capacitance (I/O1-I/O8)
CIO
–
7
pF
Semiconductor Group
128
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
AC Characteristics (note: 6,7,8)
TA = 0 to 70 ˚C,VCC = 3.3 ± 0.3V
Parameter
Symbol
HYB
3164(5)800
J/T-50
HYB
3164(5)800
J/T-60
Unit
Note
min.
max.
min.
max.
tRC
90
–
110
–
ns
RAS precharge time
tRP
30
–
40
–
ns
RAS pulse width
tRAS
50
100k
60
100k
ns
CAS pulse width
tCAS
13
100k
15
100k
ns
Row address setup time
tASR
0
–
0
–
ns
Row address hold time
tRAH
8
–
10
–
ns
Column address setup time
tASC
0
–
0
–
ns
Column address hold time
tCAH
10
–
10
–
ns
RAS to CAS delay time
tRCD
18
37
20
45
RAS to column address delay time
tRAD
13
25
15
30
ns
RAS hold time
tRSH
13
–
15
–
ns
CAS hold time
tCSH
50
–
60
–
ns
CAS to RAS precharge time
tCRP
5
–
5
–
ns
Transition time (rise and fall)
tT
3
30
3
30
ns
Refresh period for HYB3164800
tREF
–
128
–
128
ms
Refresh period for HYB3165800
tREF
–
64
–
64
ms
Access time from RAS
tRAC
–
50
–
60
ns
8, 9
Access time from CAS
tCAC
–
13
–
15
ns
8, 9
Access time from column address
tAA
–
25
–
30
ns
8, 10
OE access time
tOEA
–
13
–
15
ns
8
Column address to RAS lead time
tRAL
25
–
30
–
ns
Read command setup time
tRCS
0
–
0
–
ns
Read command hold time
tRCH
0
–
0
–
ns
11
Read command hold time referenced
to RAS
tRRH
0
–
0
–
ns
11
common parameters
Random read or write cycle time
7
Read Cycle
Semiconductor Group
129
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
AC Characteristics (cont’d)(note: 6,7,8)
TA = 0 to 70 ˚C,VCC = 3.3 ± 0.3V
Parameter
Symbol
HYB
3164(5)800
J/T-50
HYB
3164(5)800
J/T-60
Unit
Note
min.
max.
min.
max.
tCLZ
0
–
0
–
ns
8
Output buffer turn-off delay
tOFF
–
13
–
15
ns
12
Output buffer turn-off delay from OE
tOEZ
–
13
–
15
ns
12
Data to OE low delay
tDZO
0
–
0
–
ns
13
CAS high to data delay
tCDD
13
–
15
–
ns
14
OE high to data delay
tODD
13
–
15
–
ns
14
Write command hold time
tWCH
8
–
10
–
ns
Write command pulse width
tWP
8
–
10
–
ns
Write command setup time
tWCS
0
–
0
–
ns
Write command to RAS lead time
tRWL
13
–
15
–
ns
Write command to CAS lead time
tCWL
13
–
15
–
ns
Data setup time
tDS
0
–
0
–
ns
16
Data hold time
tDH
10
–
10
–
ns
16
CAS delay time from Din
tDZC
0
–
0
–
ns
13
Read-write cycle time
tRWC
126
–
150
–
ns
RAS to WE delay time
tRWD
68
–
80
–
ns
15
CAS to WE delay time
tCWD
31
–
35
–
ns
15
Column address to WE delay time
tAWD
43
–
50
–
ns
15
OE command hold time
tOEH
13
–
15
–
ns
Fast page mode cycle time
tPC
35
–
40
–
ns
CAS precharge time
tCP
10
–
10
–
ns
Access time from CAS precharge
tCPA
–
30
–
35
ns
tRAS
50
200k
60
200k
ns
CAS to output in low-Z
Write Cycle
15
Read-Modify-Write Cycle
Fast Page Mode Cycle
RAS pulse width
Semiconductor Group
130
8
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
AC Characteristics (cont’d)(note: 6,7,8)
TA = 0 to 70 ˚C,VCC = 3.3 ± 0.3V
Parameter
Symbol
HYB
3164(5)800
J/T-50
HYB
3164(5)800
J/T-60
Unit
min.
max.
min.
max.
tRHCP
30
–
35
–
ns
Fast page mode read-write cycle time
tPRWC
71
–
80
–
ns
CAS precharge to WE
tCPWD
48
–
55
–
ns
CAS setup time
tCSR
5
–
5
–
ns
CAS hold time
tCHR
10
–
10
–
ns
RAS to CAS precharge time
tRPC
5
–
5
–
ns
Write to RAS precharge time
tWRP
10
–
10
–
ns
Write hold time referenced to RAS
tWRH
10
–
10
–
ns
tCPT
25
–
30
–
ns
Write command setup time
tWTS
10
–
10
–
ns
Write command hold time
tWTH
10
–
10
–
ns
RAS pulse width
tRASS
100k
–
100k
–
ns
RAS precharge time
tRPS
90
–
110
–
CAS hold time
tCHS
-50
–
-50
–
CAS precharge to RAS Delay
Note
Fast Page Mode Read-Modify-Write
Cycle
CAS-before-RAS refresh cycle
CAS-before-RAS counter test cycle
CAS precharge time
Test mode cycle
Self Refresh Cycle
Semiconductor Group
131
17
17
ns
17
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
Notes:
1)
2)
3)
4)
All voltages are referenced to VSS.
ICC1, ICC3, ICC4 and ICC6 and ICC7 depend on cycle rate.
ICC1 and ICC4 depend on output loading. Specified values are measured with the output open.
Address can be changed once or less while RAS = Vil.In the case of ICC4 it can be changed once or less
during a fast page mode cycle ( tpc).
5) An initial pause of 100 s is required after power-up followed by 8 RAS-only-refresh cycles, before proper
device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS
initialization cycles instead of 8 RAS cycles are required.
6) AC measurements assume tT = 5 ns.
7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Also, transition times are
measured between VIH and VIL.
8) Measured with the specified current load and 100 pF at Voh = 2.0 V and Vol = 0.8 V.
9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a
reference point only: If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by
tCAC.
10) Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a
reference point only: If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by
tAA.
11) Either tRCH or tRRH must be satisfied for a read cycle.
12) tOFF (max.) and tOEZ (max.) define the time at which the outputs achieve the open-circuit condition and are
not referenced to output voltage levels.
13) Either tDZC or tDZO must be satisfied.
14) Either tCDD or tODD must be satisfied.
15) tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and the I/O pin
will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD
(min.), tAWD > tAWD (min.) and tCPWD > tCPWD (min.) , the cycle is a read-write cycle and I/O pins will
contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition
of the I/O pins (at access time) is indeterminate.
16) These parameters are referenced to CAS leading edge in early write cycles and to WRITE leading edge in
Read-Modify-Write cycles.
17) When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM
operation:
If row addresses are being refresh in an evenly distributed manner over the refresh iterval using CBR refresh
cycles, then only one CBR cycle must be performed immediatly after exit from Self Refresh.
If row addresses are being refresh in any other manner (ROR - Distributed/Burst or CBR-Burst) over the
refresh interval, then a full set of row refreshed must be performed immediately before entry to and immediatey
after exit from Self Refresh
Semiconductor Group
132
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
tRC
tRAS
RAS
V
IH
VIL
tCSH
V
IH
VIL
tRAD
tASR
Address
V
IH
VIL
tRAL
tCAH
tASC
tASR
Column
Address
Row
Address
Row
Address
tRCH
tRAH tRCS
WRITE
OE
tRRH
V
IH
VIL
tAA
tOEA
V
IH
VIL
tCDD
tDZC
tODD
tDZO
V
I/O1-I/O4
8 IH
(Inputs) V
IL
tCAC
tOFF
tCLZ
V
I/O1-I/O8 OH
(Outpus) V
OL
Hi Z
tOEZ
Valid Data Out
tRAC
“H” or “L”
Read Cycle
Semiconductor Group
tCRP
tRSH
tCAS
tRCD
CAS
tRP
133
Hi Z
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
tRC
tRAS
RAS
V
IH
VIL
tCSH
tRCD
tRSH
tCAS
V
IH
CAS
VIL
tRAD
tASR
Address
V
IH
VIL
tASR
Column
Address
Row
Address
tCWL
tWCS
t WP
V
IH
VIL
tWCH
V
IH
VIL
tDS
tDH
V
I/O1-I/O8 IH
(Inputs V
IL
Valid Data In
V
I/O1-I/O8 OH
(Outputs) V
Hi Z
OL
“H” or “L”
Write Cycle (Early Write)
Semiconductor Group
.
Row
Address
tRWL
OE
tCRP
tRAL
tCAH
tASC
tRAH
WRITE
tRP
134
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
tRC
tRAS
RAS
V
IH
VIL
tCSH
tRCD
VIL
tRAD
tASR
V
IH
Address V
IL
tCAH
tASC
tRAL
tASR
tCWL
tRWL
tWP
V
IH
VIL
tOEH
OE
V
IH
VIL
tODD
tDZO
tDZC
V
I/O1-I/O8 IH
(Inputs) V
IL
tDS
tDH
tOEZ
Valid Data
tCLZ
tOEA
V
I/O1-I/O8 OH
(Outputs) V
Hi-Z
Hi-Z
OL
“H” or “L”
Write Cycle (OE Controlled Write)
Semiconductor Group
135
.
Row
Address
Column
Address
Row
Address
tRAH
WRITE
tCRP
tRSH
tCAS
V
IH
CAS
tRP
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
tRWC
tRAS
RAS
V
IH
tCSH
VIL
tRSH
tCAS
tRCD
V
IH
CAS
tRP
tCRP
VIL
tCAH
tRAH
V
Address IH
VIL
tASR
tASC
tASR
Column
Address
Row
Address
Row
Address
tCWL
tRWL
tAWD
tRAD
tCWD
tRWD
tWP
V
IH
WRITE
VIL
tAA
tOEA
tRCS
tOEH
V
IH
OE
VIL
tDZO
tDS
tDZC
tDH
V
IH
Valid
Data in
I/O1-I/O8
(Inputs) VIL
tCLZ
tCAC
tOEZ
V
I/O1-I/O8 OH
(Outputs) VOL
Data
Out
tRAC
“H” or “L”
Read-Write (Read-Modify-Write) Cycle
Semiconductor Group
tODD
136
Semiconductor Group
Fast Page Mode Read-Modify-Write Cycle
137
IH
IH
IH
IH
IH
V
IH
V IL
V
V IL
V
V IL
V
V IL
V
V IL
OL
I/O1-I/O8 VOH
(Outputs) V
I/O1-I/O8
(Inputs) V IL
OE
WRITE
Address
CAS
RAS
V
tASR
tRAC
tCAS
tAA
tOEA
tCAC
Data In
tDS
tOEA
tCAC
tCLZ
Data
Out
tWP
tDS
tDH
Data In
tODD
tOEZ
tAWD
tCPA
tAA
tDZC
tCWL
tCAS
tPRWC
tCPWD
tCWD
tCAH
Column
Address
tASC
tCP
tOEH
tWP
tOEZ tDH
tODD
Data
Out
tAWD
tRWD
tCWD
Column
Address
tASC
tCAH
tDZC
tCLZ
tDZO
tRCS
“H” or “L”
Row
Address
tRAH
tRAD
tRCD
tCSH
tRASP
tOEH
tDZC
tCWL
tAA
tCLZ
tCPA
tRAL
tDS
tDH
tOEH
tRWL
tCWL
tWP
Data In
tODD
Data
Out
tAWD
tCPWD
tCWD
tOEA
Column
Address
tASC
tCAH
tCAS
tRSH
tCRP
Row
Address
tASR
tRP
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
tRASP
tRP
V
IH
RAS
VIL
tCP
tCAS
V
IH
CAS
VIL
tASR
Address
VIL
tCAS
tCAS
tCRP
tCSH
tRAH
V
IH
tRHCP
tRSH
tPC
tRCD
tCAH
tASC
Row
Addr
tASC
Column
Address
tCAH
tCAH
tASR
tASC
Column
Address
Column
Address
tRAD
Row
Address
tRCH
tRCH
tRCS
tRCS
tRCS
tCPA
tAA
tCPA
tAA
tOEA
V
IH
WRITE
VIL
tAA
OE
tOEA
tOEA
V
IH
VIL
V
tCAC
tOFF
tCLZ
tOFF
tOEZ
V
I/O1-I/O8 OH
(Outputs) V
Valid
Data Out
OL
“H” or “L”
Fast Page Mode Read Cycle
Semiconductor Group
138
tODD
tODD
tODD
tCAC
tCAC
tOFF
tCLZ
tCDD
tDZO
tDZO
tDZO
I/O1-I/O8 IH
(Inputs) V
IL
tDZC
tDZC
tDZC
tRRH
tOEZ
Valid
Data Out
tCLZ
tOFF
tOEZ
Valid
Data Out
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
tRASP
tRP
V
IH
RAS
VIL
tPC
tCAS
tRCD
VIL
tRAL
tRAH
tCAH
tASC
tASC tCAH
Column
Address
Column
Address
tASR
Address
V
IH
VIL
Row
Addr
OE
tWCS
tWCH
tWP
V
IH
tASC
tCAH
Column
Address
tCWL
tRWL
tWCS
tCWL
tWCS
tCWL
tRAD
WRITE
tCRP
tCP
V
IH
CAS
tRSH
tCAS
tCAS
tWCH
tWP
tWCH
tWP
tDH
tDH
VIL
V
IH
VIL
tDH
tDS
tDS
V
I/O1-I/O8 IH
(Inputs) V
IL
Valid
Data In
tDS
Valid
Data In
Valid
Data In
V
I/O1-I/O8 OH
(Outputs) V
HI-Z
OL
“H” or “L”
Fast Page Mode Early Write Cycle
Semiconductor Group
139
tASR
Column
Address
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
tRC
tRAS
RAS
tRP
V
IH
VIL
tCRP
tRPC
V
IH
CAS
VIL
tRAH
tASR
tASR
Address
V
IH
Row
Address
VIL
Row
Address
V
I/O1-I/O8 OH
(Outputs) V
HI-Z
OL
“H” or “L”
RAS-Only Refresh Cycle
Semiconductor Group
140
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
tRC
tRP
RAS
tRP
tRAS
V
IH
VIL
tCRP
tRPC
tCSR
CAS
V
IH
VIL
tRPC
tCHR
tCP
tWRP
tWRH
WRITE
V
IH
VIL
tOEZ
OE
V
IH
VIL
tCDD
V
I/O1-I/O8 IH
(Inputs) V
IL
tODD
V
I/O1-I/O8 OH
(Outputs)VOL
HI-Z
tOFF
“H” or “L”
CAS-Before-RAS Refresh Cycle
Semiconductor Group
141
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
tRC
tRC
RAS
tRP
tRAS
V
IH
tRP
tRAS
VIL
tRSH
tRCD
tCRP
tCHR
CAS
V
IH
VIL
tRAD
Address
VIL
Column
Address
Row
Addr
Row
Address
tRRH
tRCS
WRITE
tASR
tWRH
tCAH
tASR
V
IH
tWRP
tASC
tRAH
V
IH
VIL
tAA
tOEA
OE
V
IH
VIL
tDZC
tCDD
tDZO
tODD
V
I/O1-I/O8 IH
(Inputs) V
IL
tOFF
tCAC
tCLZ
tOEZ
tRAC
V
I/O1-I/O8 OH
(Outputs) V
Valid Data Out
OL
“H” or “L”
Hidden Refresh Cycle (Read)
Semiconductor Group
142
HI-Z
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
tRC
tRC
tRP
RAS
tRAS
V
IH
VIL
tRCD
CAS
WRITE
OE
tRSH
tCHR
tCRP
V
IH
VIL
tRAD
tRAH
tASC
tCAH
tASR
Address
tRP
tRAS
V
IH
VIL
Row
Addr
tASR
Row
Address
Column
Address
tWCS
tWCH
tWP
V
IH
VIL
V
IH
VIL
tDS
tDH
V
IH
I/O1-I/O8
(Inputs) V
IL
Valid Data
V
I/O1-I/O8 OH
(Outputs) V
HI-Z
OL
“H” or “L”
Hidden Refresh Cycle (Early Write)
Semiconductor Group
143
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
V
RAS
V
IL
tCHR
tCSR
V
CAS
V
IH
V
tWRP
V
tASR
Row
Address
Column
Address
IL
tAA
tRCS
tWRH
V
tRAL
tCAH
tASC
IH
Read Cycle
WRITE
tRSH
tCAS
tCPT
IL
V
Address
tRP
tRAS
IH
tRRH
tRCH
tCAC
IH
IL
tOEA
V
IH
OE
V
I/O1-I/O8
(Inputs)
IL
V
V
tDZC
tDZO
tCDD
tODD
IH
IL
tOFF
tCLZ
I/O1-I/O8
(Outputs)
V
OH
V
OL
Write Cycle
V
tRWL
tCWL
tWCH
IH
IL
V
OE
Valid Data Out
tWCS
tWRP
tWRH
V
WRITE
V
IH
IL
tDH
tDS
I/O1-I/O8
(Inputs)
I/O1-I/O8
(Outputs)
V
V
IH
V
IH
IL
V
I/O1-I/O8
(Outputs)
tRCS
tWRH
tAA
tOEH
IH
tDS
tDZC
tDZO
tDH
IH
Data In
IL
tCLZ
V
OH
V
tOEA
IL
V
tWP
tCAC
IL
V
V
HI-Z
IH
V
I/O1-I/O8
(Inputs)
tWRP
tCWL
tRWL
tAWD
tCWD
V
V
OE
Valit Data In
IL
Read-Modify-Write Cycle
WRITE
tOEZ
OL
D.Out
HI-Z
CAS-Before-RAS Refresh Counter Test Cycle
Semiconductor Group
tODD
tOEZ
tCAC
144
HI-Z
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
tRC
tRP
RAS
VIL
tRP
tRPC
tCP
CAS
tRAS
V
IH
tRPC
tCHR
tCSR
V
IH
VIL
tRAH
tASR
V
Adress IH
VIL
WRITE
OE
Row
Address
tWTS
V
IH
tWTH
VIL
V
IH
VIL
tODD
V
I/O1-I/O8 IH
(Inputs) V
IL
V
tCDD
tOEZ
I/O1-I/O8 OH
(Outputs) V
HI-Z
OL
tOFF
“H” or “L”
Test Mode Entry
Semiconductor Group
145
tCRP
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
tRASS
tRP
RAS
tRPS
V
IH
VIL
tRPC
tCHS
tCSR
CAS
V
IH
tCP
VIL
tWRP
tWRH
WRITE
V
IH
VIL
tOEZ
OE
V
IH
VIL
tCDD
I/O1-I/O8
(Inputs)
V
IH
VIL
tODD
V
OH
I/O1-I/O8
(Outputs) V
OL
HI-Z
tOFF
“H” or “L”
CAS-before-RAS Self Refresh
Semiconductor Group
146
tCRP
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
Package Outlines
P-SOJ-34-1 (500 mil)
(Plastic Small Outline J-leaded Package)
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
SMD = Surface Mounted Device
Semiconductor Group
147
Dimensions in mm
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
P-TSOPII-34-1 (500 mil)
(Plastic Thin Small Outline Package Type
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
SMD = Surface Mounted Device
Semiconductor Group
148
Dimensions in mm
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