June 2007 HY[B/I]39S512400A[E/T] HY[B/I]39S512800A[E/T] HY[B/I]39S512160A[E/T] 512-Mbit Synchronous DRAM SDRAM RoHS Compliant Products Internet Data Sheet Rev. 1.52 Internet Data Sheet HY[I/B]39S512[40/80/16]0A[E/T] 512-Mbit Synchronous DRAM HY[B/I]39S512400A[E/T], HY[B/I]39S512800A[E/T], HY[B/I]39S512160A[E/T] Revision History: 2007-06, Rev. 1.52 Page Subjects (major changes since last revision) All Adapted internet edition 13 Corrected operation command "Power Down / Clock suspend ...” in truth table Previous Revision: 2007-06, Rev. 1.51 13 Corrected operation command "Power Down Exit" to X (WE#) 15 Corrected text to "After the mode register is set a NOP command is required" , chapter 3.3 19 Corrected text to "One clock delay is required for mode entry and exit", chapter 3.5 21 Corrected the line "Input Capacitances: CK" in table 10, chapter 4 Qimonda template Previous Revision: 2007-05, Rev. 1.5 All Added more product types Previous Revision: 2006-01, Rev. 1.4 We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: [email protected] qag_techdoc_rev400 / 3.2 QAG / 2006-07-21 03292006-6Y91-0T2Z 2 Internet Data Sheet HY[I/B]39S512[40/80/16]0A[E/T] 512-Mbit Synchronous DRAM 1 Overview This chapter lists all main features of the product family HY[I/B]39S512[40/80/16]0A[E/T] and the ordering information. 1.1 • • • • • • • • • • Features Fully Synchronous to Positive Clock Edge 0 to 70 °C Operating Temperature for HYB... -40 to 85 °C Operating Temperature for HYI... Four Banks controlled by BA0 & BA1 Programmable CAS Latency: 2 & 3 Programmable Wrap Sequence: Sequential or Interleave Programmable Burst Length: 1, 2, 4, 8 and full page Multiple Burst Read with Single Write Operation Automatic and Controlled Precharge Command Data Mask for Read / Write control (x4, x8, x16) • • • • • • • • • Data Mask for Byte Control (x16) Auto Refresh (CBR) and Self Refresh Power Down and Clock Suspend Mode 8192 refresh cycles / 64 ms (7.8 µs) Random Column Address every CLK (1-N Rule) Single 3.3 V ± 0.3 V Power Supply LVTTL Interface Plastic Package : P(G)-TSOPII-54 RoHS compliant product TABLE 1 Performance Product Type Speed Code –7.5 Speed Grade Max. Clock Frequency PC133–333 @CL3 @CL2 fCK3 tCK3 tAC3 tCK2 tAC2 1) Max. Frequency CL/tRCD / tRP Rev. 1.52, 2007-06 03292006-6Y91-0T2Z 3 Unit 1) — 133 MHz 7.5 ns 5.4 ns 10 ns 6 ns Internet Data Sheet HY[I/B]39S512[40/80/16]0A[E/T] 512-Mbit Synchronous DRAM 1.2 Description The HY[I/B]39S512[40/80/16]0A[E/T] are four bank Synchronous DRAM’s organized as 4 banks × 32MBit ×4, 4 banks × 16MBit ×8 and 4 banks × 8Mbit ×16 respectively. These synchronous devices achieve high speed data transfer rates for CAS latencies by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. The chip is fabricated with Qimonda advanced 0.14 µm 512-MBit DRAM process technology. The device is designed to comply with all industry standards set for synchronous DRAM products, both electrically and mechanically. All of the control, address, data input and output circuits are synchronized with the positive edge of an externally supplied clock. Operating the four memory banks in an interleave fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate is possible depending on burst length, CAS latency and speed grade of the device. Auto Refresh (CBR) and Self Refresh operation are supported. These devices operate with a single 3.3 V ± 0.3 V power supply. All 512-Mbit components are available in P(G)-TSOPII-54 packages. TABLE 2 Ordering Information for RoHS Compliant Products Product Type Speed Grade Description Package 133MHz 4B × 32M × 4 SDRAM P-TSOPII-54 Note Standard Operating Temperature (0 °C - +70 °C) HYB39S512400AT-7.5 PC133-333-520 HYB39S512800AT-7.5 133MHz 4B × 16M × 8 SDRAM HYB39S512160AT-7.5 133MHz 4B × 8M × 16 SDRAM HYB39S512400AE-7.5 133MHz 4B × 32M × 4 SDRAM HYB39S512800AE-7.5 133MHz 4B × 16M × 8 SDRAM HYB39S512160AE-7.5 133MHz 4B × 8M × 16 SDRAM PG-TSOPII-54 1) Industrial Operating Temperature (–40 °C - +85 °C) HYI39S512400AT-7.5 PC133-333-520 133MHz 4B × 32M × 4 SDRAM HYI39S512800AT-7.5 133MHz 4B × 16M × 8 SDRAM HYI39S512160AT-7.5 133MHz 4B × 8M × 16 SDRAM HYI39S512400AE-7.5 133MHz 4B × 32M × 4 SDRAM HYI39S512800AE-7.5 133MHz 4B × 16M × 8 SDRAM HYI39S512160AE-7.5 133MHz 4B × 8M × 16 SDRAM P-TSOPII-54 PG-TSOPII-54 1) 1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers. Rev. 1.52, 2007-06 03292006-6Y91-0T2Z 4 Internet Data Sheet HY[I/B]39S512[40/80/16]0A[E/T] 512-Mbit Synchronous DRAM 2 Configuration This chapter contains the pin configuration table and the TSOP package drawing. 2.1 Pin Configuration Listed below are the pin configurations sections for the various signals of the SDRAM. TABLE 3 Ball Configuration of the SDRAM Ball No. Name Pin Type Buffer Type Function Clock Signals x4/ x8/ x16 Organization 38 CLK I LVTTL Clock Signal CLK 37 CKE I LVTTL Clock Enable Control Signals x4/ x8/ x16 Organization 18 RAS I LVTTL 17 CAS I LVTTL 16 WE I LVTTL 19 CS I LVTTL Row Address Strobe (RAS), Column Address Strobe (CAS), Write Enable (WE) Chip Select Address Signals x4/ x8/ x16 Organization 20 BA0 I LVTTL 21 BA1 I LVTTL 23 A0 I LVTTL 24 A1 I LVTTL 25 A2 I LVTTL 26 A3 I LVTTL 29 A4 I LVTTL 30 A5 I LVTTL 31 A6 I LVTTL 32 A7 I LVTTL 33 A8 I LVTTL 34 A9 I LVTTL 22 A10 I LVTTL 35 A11 I LVTTL 36 A12 I LVTTL Rev. 1.52, 2007-06 03292006-6Y91-0T2Z Bank Address Signals 1:0 Address Signal 9:0, Address Signal 10/Auto precharge 5 Internet Data Sheet HY[I/B]39S512[40/80/16]0A[E/T] 512-Mbit Synchronous DRAM Ball No. Name Pin Type Buffer Type Function Data Signals x4 Organization 5 DQ0 I/O LVTTL 11 DQ1 I/O LVTTL 44 DQ2 I/O LVTTL 50 DQ3 I/O LVTTL Data Signal Bus [3:0] Data Signals x8 Organization 2 DQ0 I/O LVTTL 5 DQ1 I/O LVTTL 8 DQ2 I/O LVTTL 11 DQ3 I/O LVTTL 44 DQ4 I/O LVTTL 47 DQ5 I/O LVTTL 50 DQ6 I/O LVTTL 53 DQ7 I/O LVTTL Data Signal Bus [7:0] Data Signals x16 Organization 2 DQ0 I/O LVTTL 4 DQ1 I/O LVTTL 5 DQ2 I/O LVTTL 7 DQ3 I/O LVTTL 8 DQ4 I/O LVTTL 10 DQ5 I/O LVTTL 11 DQ6 I/O LVTTL 13 DQ7 I/O LVTTL 42 DQ8 I/O LVTTL 44 DQ9 I/O LVTTL 45 DQ10 I/O LVTTL 47 DQ11 I/O LVTTL 48 DQ12 I/O LVTTL 50 DQ13 I/O LVTTL 51 DQ14 I/O LVTTL 53 DQ15 I/O LVTTL Data Signal Bus [15:0] Data Mask x4 / x8 Organization 39 DQM I/O LVTTL Data Mask Data Mask x16 Organization 39 UDQM I/O LVTTL Data Mask Upper Byte 15 LDQM I/O LVTTL Data Mask Lower Byte Power Supplies x4 /x8/ x16 Organization 3, 43, 49 VDDQ 1, 14 VDD PWR — Power Supply PWR — Power Supply Rev. 1.52, 2007-06 03292006-6Y91-0T2Z 6 Internet Data Sheet HY[I/B]39S512[40/80/16]0A[E/T] 512-Mbit Synchronous DRAM Ball No. Name 6, 12, 46, VSSQ 52 28, 41, 54 VSS Pin Type Buffer Type Function PWR — Power Supply Ground for DQs PWR — Power Supply Ground Not connected x4 Organization 2, 4, 7, 8, NC 10, 13, 15, 40, 42, 45, 47, 48, 51, 53 NC — Not connected Not connected x8 Organization 4, 7, 10, 13, 15, 40, 42, 45, 48, 51 NC NC — Not connected Not connected x16 Organization 40 NC NC Rev. 1.52, 2007-06 03292006-6Y91-0T2Z — Not connected 7 Internet Data Sheet HY[I/B]39S512[40/80/16]0A[E/T] 512-Mbit Synchronous DRAM FIGURE 1 Ball Configuration P(G)-TSOPII-54 [ [ [ 9'' '4 1& 9''4 9''4 '4 1& 1& '4 '4 9664 9664 9'' 9'' '4 9''4 966 966 966 1& '4 '4 9664 9664 9664 1& 1& '4 '4 '4 '4 '4 9664 9''4 9''4 9''4 '4 1& 1& 1& 1& '4 '4 '4 1& 1& '4 '4 9''4 9''4 9''4 9664 9664 9664 '4 1& 1& 1& 1& '4 '4 '4 '4 '4 '4 '4 9664 9664 9664 9''4 9''4 9''4 '4 1& 1& 1& 1& '4 9'' 9'' 9'' 966 966 966 /'40 1& 1& 1& 1& 1& :( :( :( '40 '40 8'40 &$6 &$6 &$6 &/. &/. &/. 5$6 5$6 5$6 &.( &.( &.( &6 &6 &6 1&$ 1&$ 1&$ %$ %$ %$ $ $ $ %$ %$ %$ $ $ $ $$3 $$3 $$3 $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ 9'' 9'' 9'' 966 966 966 0336 Rev. 1.52, 2007-06 03292006-6Y91-0T2Z 8 Internet Data Sheet HY[I/B]39S512[40/80/16]0A[E/T] 512-Mbit Synchronous DRAM 3 Functional Description This chapter lists all defined commands and their usage for this Synchronous DRAM family. TABLE 4 Truth Table: Operation Command Operation Device State CKE n-11)2) CKE n1)2) DQM 1)2) BA0 BA11)2) AP= A101)2) Addr. CS RAS CAS WE 1)2) 1)2) 1)2) 1)2) 1)2) Bank Active Idle3) H X X V V V L L H H Bank Precharge Any H X X V L X L L H L Precharge All Any H X X X H X L L H L Write Active3) H X X V L V L H L L Write with Auto precharge Active 3) H X X V H V L H L L Read Active3) H X X V L V L H L H 3) H X X V H V L H L H Read with Auto precharge Active Mode Register Set Idle H X X V V V L L L L No Operation Any H X X X X X L H H H Burst Stop Active H X X X X X L H H L Device Deselect Any H X X X X X H X X X Auto Refresh Idle H H X X X X L L L H Self Refresh Entry Idle H L X X X X L L L H Self Refresh Exit Idle (Self Refr.) L H X X X X H X X X L H H X Power Down/ Clock Suspend Entry Active or Idle or Burst H L X X X X H X X X L H H H Power Down/ Clock Suspend Exit Active or Idle or Burst L H X X X L H H H Data Write/ Output Enable Active H X L X X X X X X X Data Write/ Output Disable Active H X H X X X X X X X H X X X X 1) V = Valid, x = Don’t Care, L = Low Level, H = High Level 2) CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before the commands are provided. 3) This is the state of the banks designated by BA0, BA1 signals. Rev. 1.52, 2007-06 03292006-6Y91-0T2Z 9 Internet Data Sheet HY[I/B]39S512[40/80/16]0A[E/T] 512-Mbit Synchronous DRAM "! "! ! ! ! ! ! ! ! ! ! ! ! ! ! -/$% #, "4 ", W W W W REG ADDR ! -0"3 TABLE 5 Mode Register Definition (BA[1:0] = 00B) Field Bits Type Description BL [2:0] w Burst Length Number of sequential bits per DQ related to one read/write command, see Note: All other bit combinations are RESERVED 000B 001B 010B 011B 111B 1 2 4 8 Full Page (Sequential burst type only) BT 3 w Burst Type See Table 6 for internal address sequence of low order address bits. Sequential 0B Interleaved 1B CL [6:4] w CAS Latency Number of full clocks from read command to first data valid window. Note: All other bit combinations are RESERVED. 010B 2 011B 3 Mode [12:7] w Operation Mode Note: All other bit combinations are RESERVED. 0B 1B Rev. 1.52, 2007-06 03292006-6Y91-0T2Z Burst read/burst write Burst read/single write 10 Internet Data Sheet HY[I/B]39S512[40/80/16]0A[E/T] 512-Mbit Synchronous DRAM TABLE 6 Burst Length and Sequence Burst Length Starting Column Address A2 A1 A0 Type=Sequential Type=Interleaved 0 0–1 0–1 1 1–0 1–0 0 0 0–1–2–3 0–1–2–3 0 1 1–2–3–0 1–0–3–2 1 0 2–3–0–1 2–3–0–1 1 1 3–0–1–2 3–2–1–0 2 4 8 FullPage Order of Accesses Within a Burst 0 0 0 0–1–2–3–4–5–6–7 0–1–2–3–4–5–6–7 0 0 1 1–2–3–4–5–6–7–0 1–0–3–2–5–4–7–6 0 1 0 2–3–4–5–6–7–0–1 2–3–0–1–6–7–4–5 0 1 1 3–4–5–6–7–0–1–2 3–2–1–0–7–6–5–4 1 0 0 4–5–6–7–0–1–2–3 4–5–6–7–0–1–2–3 1 0 1 5–6–7–0–1–2–3–4 5–4–7–6–1–0–3–2 1 1 0 6–7–0–1–2–3–4–5 6–7–4–5–2–3–0–1 1 1 1 7–0–1–2–3–4–5–6 7–6–5–4–3–2–1–0 Cn, Cn+1, Cn+2 .... Not supported n Notes 1. 2. 3. 4. For a burst length of two, A1-Ai selects the two-data-element block; A0 selects the first access within the block. For a burst length of four, A2-Ai selects the four-data-element block; A0-A1 selects the first access within the block. For a burst length of eight, A3-Ai selects the eight-data- element block; A0-A2 selects the first access with in the block. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. Rev. 1.52, 2007-06 03292006-6Y91-0T2Z 11 Internet Data Sheet HY[I/B]39S512[40/80/16]0A[E/T] 512-Mbit Synchronous DRAM 4 Electrical Characteristics 4.1 Operating Conditions TABLE 7 Absolute Maximum Ratings Parameter Input / Output voltage relative to VSS Voltage on VDD supply relative to VSS Voltage on VDDQ supply relative to VSS Operating Temperature for HYB... Operating Temperature for HYI... Storage temperature range Power dissipation per SDRAM component Data out current (short circuit) Symbol Limit Values VIN, VOUT VDD VDDQ TA TA TSTG PD IOUT Unit Note/ Test Condition Min. Max. –1.0 +4.6 V — –1.0 +4.6 V — –1.0 +4.6 V — 0 +70 °C — –40 +85 °C — –55 +150 °C — — 1 W — — 50 mA — Attention: Stresses above the max. values listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. Rev. 1.52, 2007-06 03292006-6Y91-0T2Z 12 Internet Data Sheet HY[I/B]39S512[40/80/16]0A[E/T] 512-Mbit Synchronous DRAM TABLE 8 DC Characteristics Parameter Symbol Values Min. Max. VDD I/O Supply Voltage VDDQ Input high voltage VIH Input low voltage VIL Output high voltage (IOUT = – 4.0 mA) VOH Output low voltage (IOUT = 4.0 mA) VOL Input leakage current, any input (0 V < VIN < VDD, all other inputs = 0 V) IIL IOL Output leakage current (DQs are disabled, 0 V < VOUT < VDDQ) Supply Voltage Unit Note/ Test Condition 3.0 3.6 V 1) 3.0 3.6 V 1) 2.0 VDDQ + 0.3 V 1)2) –0.3 +0.8 V 1)2) 2.4 — V 1) — 0.4 V 1) –5 +5 µA — –5 +5 µA — 1) All voltages are referenced to VSS 2) VIH may overshoot to VDDQ + 2.0 V for pulse width of < 4ns with 3.3 V. VIL may undershoot to -2.0 V for pulse width < 4.0 ns with 3.3 V. Pulse width measured at 50% points with amplitude measured peak to DC reference. TABLE 9 Input and Output Capacitances Parameter Symbol Values Min. Max. Unit Note Input Capacitances: CK CI1 2.5 3.5 pF 1)2) Input Capacitance (A0-A12, BA0, BA1, RAS, CAS, WE, CS, CKE, DQM) CI2 2.5 3.8 pF 1)2) CI0 4.0 6.0 pF 1)2) Input/Output Capacitance (DQ) 1) VDD,VDDQ = 3.3 V ± 0.3 V, f = 1 MHz, TA see Table 7 2) Capacitance values are shown for TSOP-54 packages. Capacitance values for TFBGA packages are lower by 0.5 pF Rev. 1.52, 2007-06 03292006-6Y91-0T2Z 13 Internet Data Sheet HY[I/B]39S512[40/80/16]0A[E/T] 512-Mbit Synchronous DRAM TABLE 10 IDD Conditions Parameter Symbol Operating Current Precharge Standby Current IDD1 IDD2P IDD2N IDD3N IDD3P IDD4 IDD5 IDD6 One bank active, Burst length = 1 Power down mode Non-power down mode No Operating Current Active state (max. 4 banks) Burst Operating Current Read command cycling Auto Refresh Current Auto Refresh command cycling Self Refresh Current Self Refresh Mode, CKE=0.2 V, tCK=infinity TABLE 11 IDD Specifications and Conditions Symbol IDD1 IDD2P IDD2N IDD3N IDD3P IDD4 IDD5 Test Condition –7.5 tRC = tRC(min), IO = 0 mA CS =VIH (min.), CKE ≤VIL(max) CS =VIH (min.), CKE≥ VIH(min) CS = VIH(min), CKE ≥VIH(min.) CS = VIH(min), CKE ≤ VIL(max.) tRFC= tRFC(min) tRFC= 15.6 µs IDD6 Unit Note 1) Typ. Max. 123 145 mA 2)3) 0.6 3 mA 2) 23 31 mA 2) 26 35 mA 2) 2 4 mA 2) 97 123 mA 2)3) 255 300 mA 4) — — mA — 2.1 4 mA — 1) TA = 0 to 70 °C for HYB.., TA = -40 to 85 °C for i-temp part (HYI..); VSS = 0 V, VDD, VDDQ = +3.3 V ± 0.3 V 2) These parameters depend on the cycle rate. All values are measured at 133 MHz for “-7.5” components with the outputs open. Input signals are changed once during tck . 3) These parameters are measured with continuous data stream during read access and all DQ toggling. CL=3 and BL=4 is assumed and the VDDQ current is excluded. 4) tRFC= tRFC(min) “burst refresh”, tRFC= 15.6 µs “distributed refresh”. Rev. 1.52, 2007-06 03292006-6Y91-0T2Z 14 Internet Data Sheet HY[I/B]39S512[40/80/16]0A[E/T] 512-Mbit Synchronous DRAM 4.2 AC Characteristics TABLE 12 AC Timing - Absolute Specifications Parameter Symbol –7.5 Unit Note1)2)3) PC133–333 Min. Max. Clock and Clock Enable Clock Frequency tCK 7.5 10 — — ns ns CL3 CL2 Access Time from Clock tAC — — 5.4 6 ns ns CL3 CL2 3)4)5) Clock High Pulse Width Clock Low Pulse Width Transition time tCH tCL tT 2.5 — ns 2.5 — ns 0.3 1.2 ns tIS tIH tCKS tCKH tRSC tSB 1.5 — ns 6) 0.8 — ns 6) 1.5 — ns 6) 0.8 — ns 6) 2 — tCK 0 7.5 ns tRCD tRP tRAS tRC tRFC tRRD tCCD 20 — ns 7) 20 — ns 7) 45 100k ns 7) 67 — ns 7) 67 — ns 15 — ns 1 — tCK tREF tSREX tOH – 64 ms 1 — tCK 3 — ns tLZ tHZ tDQZ 1 — ns 3 7 ns — 2 tCK Setup and Hold Times Input Setup Time Input Hold Time CKE Setup Time CKE Hold Time Mode Register Set-up to Active delay Power Down Mode Entry Time Common Parameters Row to Column Delay Time Row Precharge Time Row Active Time Row Cycle Time Row Cycle Time during Auto Refresh Activate(a) to Activate(b) Command period CAS(a) to CAS(b) Command period 7) Refresh Cycle Refresh Period (8192 cycles) Self Refresh Exit Time Data Out Hold Time Read Cycle Data Out to Low Impedance Time Data Out to High Impedance Time DQM Data Out Disable Latency Rev. 1.52, 2007-06 03292006-6Y91-0T2Z 15 3)5) Internet Data Sheet HY[I/B]39S512[40/80/16]0A[E/T] 512-Mbit Synchronous DRAM Parameter Symbol –7.5 Unit Note1)2)3) PC133–333 Min. Max. Write Cycle Last Data Input to Precharge (Write without Auto Precharge) tWR 15 — ns 8) Last Data Input to Activate (Write with Auto Precharge) tDAL(min.) — — tCK 9) DQM Write Mask Latency tDQW 0 — tCK 1) TA = 0 to 70 °C for HYB..., TA = -40 to 85 °C for i-temp part (HYI..); VSS = 0 V, VDD, VDDQ = 3.3 V ± 0.3 V, tT = 1 ns 2) For proper power-up see the operation section of this data sheet. 3) AC timing tests for LV-TTL versions have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.4 V crossover point. The transition time is measured between VIH and VIL. All AC measurements assume tT = 1 ns with the AC output load circuit shown in figure below. Specified tAC and tOH parameters are measured with a 50 pF only, without any resistive termination and with an input signal of 1V / ns edge rate between 0.8 V and 2.0 V. 4) If clock rising time is longer than 1 ns, a time (tT/2 - 0.5) ns has to be added to this parameter. 5) Access time from clock tac is 4.6 ns for PC133 components with no termination and 0 pF load, Data out hold time toh is 1.8 ns for PC133 components with no termination and 0 pF load. 6) If tT is longer than 1 ns, a time (tT - 1) ns has to be added to this parameter. 7) These parameter account for the number of clock cycles and depend on the operating frequency of the clock, as follows: the number of clock cycles = specified value of timing period (counted in fractions as a whole number) 8) It is recommended to use two clock cycles between the last data-in and the precharge command in case of a write command without AutoPrecharge. One clock cycle between the last data-in and the precharge command is also supported, but restricted to cycle times tCK greater or equal the specified tWR value, where tck is equal to the actual system clock time. 9) When a Write command with Auto Precharge has been issued, a time of tDAL(min) has be fullfilled before the next Activate Command can be applied. For each of the terms, if not already an integer, round up to the next highest integer. tCK is equal to the actual system clock time. FIGURE 2 Measurement conditions for tAC and tOH t CH 2 .4 V 0 .4 V 1 .4 V C LO C K tCL t IS tT t IH 1 .4 V IN P U T tA C t LZ tA C t OH OUTPUT 1 .4 V t HZ IO.vsd Rev. 1.52, 2007-06 03292006-6Y91-0T2Z 16 Internet Data Sheet HY[I/B]39S512[40/80/16]0A[E/T] 512-Mbit Synchronous DRAM 5 Package Outlines FIGURE 3 *$8 *(3 /$1( [ [ 6($7 ,1 *3 /$1( 0 [ 0$ ; Package Outline PG-TSOPII-54 (top view) 0$ ; ,QGH[ 0D UNLQJ 'R HVQRWLQFOXGHS ODVWLFR UP HWD OSUR WUXV LRQR I P D [S HUV LGH 'R HVQRWLQFOXGHS ODVWLFS URWU XVLRQRI P D[S HUVLGH 'R HVQRWLQFOXGHG DPEDUSURWU XVLRQRI P D[S HUVLGH Rev. 1.52, 2007-06 03292006-6Y91-0T2Z 17 *3; Internet Data Sheet HY[I/B]39S512[40/80/16]0A[E/T] 512-Mbit Synchronous DRAM List of Figures Figure 1 Figure 2 Figure 3 Ball Configuration P(G)-TSOPII-54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Measurement conditions for tAC and tOH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Package Outline PG-TSOPII-54 (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Rev. 1.52, 2007-06 03292006-6Y91-0T2Z 18 Internet Data Sheet HY[I/B]39S512[40/80/16]0A[E/T] 512-Mbit Synchronous DRAM List of Tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Ordering Information for RoHS Compliant Products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Ball Configuration of the SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Truth Table: Operation Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Mode Register Definition (BA[1:0] = 00B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Burst Length and Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Input and Output Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 IDD Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 IDD Specifications and Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 AC Timing - Absolute Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Rev. 1.52, 2007-06 03292006-6Y91-0T2Z 19 Internet Data Sheet HY[I/B]39S512[40/80/16]0A[E/T] 512-Mbit Synchronous DRAM Table of Contents 1 1.1 1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 2.1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 4.1 4.2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Rev. 1.52, 2007-06 03292006-6Y91-0T2Z 20 Internet Data Sheet Edition 2007-06 Published by Qimonda AG Gustav-Heinemann-Ring 212 D-81739 München, Germany © Qimonda AG 2007. All Rights Reserved. Legal Disclaimer The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics (“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office. Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Qimonda Office. Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. www.qimonda.com