Qimonda HYI39S256800FT-7 256-mbit synchronous dram Datasheet

September 2007
HY[B/I]39S256[40/80/16]0FT(L)
HY[B/I]39S256[40/80/16]0FE(L)
HYB39S256[40/80/16]0FF(L)
HYB39S 256407 F E
256-MBit Synchronous DRAM
SDRAM
Internet Data Sheet
Rev. 1.42
Internet Data Sheet
HY[B/I]39S256[40/80/16][0/7]F[E/T/F](L)
256-MBit Synchronous DRAM
HY[B/I]39S256[40/80/16]0FT(L), HY[B/I]39S256[40/80/16]0FE(L), HYB39S256[40/80/16]0FF(L), HYB39S256407FE
Revision History: 2007-09, Rev. 1.42
Page
Subjects (major changes since last revision)
All
Adapted internet edition
7
Corrected SDRAM organization for x4 in Table 4
Previous Revision: 2007-09, Rev. 1.41
All
Editorial Change
4
Corrected HYB39S256407FF-7 to HYP39S256407FE-7
Previous Revision: 2007-04, Rev. 1.40
4
Corrected HYB39S256400FE-7 to HYB39S256400FF-7
Previous Revision: 2007-03, Rev. 1.30
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qag_techdoc_rev400 / 3.2 QAG / 2006-08-07
03292006-TMTK-JFEU
2
Internet Data Sheet
HY[B/I]39S256[40/80/16][0/7]F[E/T/F](L)
256-MBit Synchronous DRAM
1
Overview
This chapter lists all main features of the product family HYB39S256[400/800/160]F[E/T/F](L) and the ordering information.
1.1
•
•
•
•
•
•
•
•
•
•
Features
Fully Synchronous to Positive Clock Edge
0 to 70 °C Standard Operating Temperature
-40 to 85 °C Industrial Operating Temperature
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2 & 3
Programmable Wrap Sequence: Sequential or Interleave
Programmable Burst Length: 1, 2, 4, 8 and full page
Multiple Burst Read with Single Write Operation
Automatic and Controlled Precharge Command
Data Mask for Read / Write control (x4, x8)
•
•
•
•
•
•
•
•
Data Mask for Byte Control (x16)
Auto Refresh (CBR) and Self Refresh
Power Down and Clock Suspend Mode
8192 refresh cycles / 64 ms (7.8 μs)
Random Column Address every CLK (1-N Rule)
Single 3.3 V ± 0.3 V Power Supply
LVTTL Interface versions
Packages:
– P(G)–TSOPII–54 (400mil width)
– PG–TFBGA–54
TABLE 1
Performance
Poduct Type Speed Code
–6
–7
Unit
Speed Grade
PC166–333
PC133–222
—
166
143
MHz
6
7
ns
5.4
5.4
ns
7.5
7.5
ns
5.4
5.4
ns
Max. Clock Frequency
@CL3
@CL2
Rev. 1.42, 2007-09
03292006-TMTK-JFEU
fCK3
tCK3
tAC3
tCK2
tAC2
3
Internet Data Sheet
HY[B/I]39S256[40/80/16][0/7]F[E/T/F](L)
256-MBit Synchronous DRAM
1.2
Description
The HYB39S256[400/800/160]F[E/T/F](L) are four bank Synchronous DRAMs organized as 4 banks x 16 MBit x4,
4 banks x 8 MBit x8 and 4 banks x 4 Mbit x16 respectively. These synchronous devices achieve high speed data transfer rates
for CAS latencies by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a
system clock. The chip is fabricated with Qimonda’s advanced 0.11-μm 256-MBit DRAM process technology.
The device is designed to comply with all industry standards set for synchronous DRAM products, both electrically and
mechanically. All of the control, address, data input and output circuits are synchronized with the positive edge of an externally
supplied clock.
Operating the four memory banks in an interleave fashion allows random access operation to occur at a higher rate than is
possible with standard DRAMs. A sequential and gapless data rate is possible depending on burst length, CAS latency and
speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. These devices operate with a single 3.3 V ± 0.3 V power supply.
All 256-Mbit components are available in P(G)–TSOPII–54 and PG–TFBGA–54 packages.
TABLE 2
Ordering Information for RoHS Compliant Products
Product Type
Speed Grade
Description
Package
Note
143MHz 64M x 4 SDRAM
PG-TFBGA-54
1)
Standard Operating Temperature
HYB39S256407FE-7
PC133-222
HYB39S256400FF-7
PG-TFBGA-54
HYB39S256400FE-7
PG-TSOPII-54
HYB39S256400FFL-7
PG-TFBGA-54
HYB39S256400FEL-7
PG-TSOPII-54
HYB39S256800FF-7
143MHz 32M x 8 SDRAM
PG-TFBGA-54
HYB39S256800FE-7
PG-TSOPII-54
HYB39S256800FFL-7
PG-TFBGA-54
HYB39S256800FEL-7
PG-TSOPII-54
HYB39S256160FF-7
143MHz 16M x 16 SDRAM
PG-TFBGA-54
HYB39S256160FE-7
PG-TSOPII-54
HYB39S256160FFL-7
PG-TFBGA-54
HYB39S256160FEL-7
PG-TSOPII-54
HYB39S256160FF-6
166MHz 16M x 16 SDRAM
PG-TFBGA-54
HYB39S256160FE-6
PG-TSOPII-54
HYB39S256160FFL-6
PG-TFBGA-54
HYB39S256160FEL-6
PG-TSOPII-54
Industrial Operating Temperature
HYI39S256800FE-7
HYI39S256160FE-7
PC166-333
143MHz 32M x 8 SDRAM
PG-TSOPII-54
1)
143MHz 16M x 16 SDRAM
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 1.42, 2007-09
03292006-TMTK-JFEU
4
Internet Data Sheet
HY[B/I]39S256[40/80/16][0/7]F[E/T/F](L)
256-MBit Synchronous DRAM
TABLE 3
Ordering Information for Lead-Containing Products
Product Type
Speed Grade
Description
Package
143MHz 64M x 4 SDRAM
P-TSOPII-54
Standard Operating Temperature
HYB39S256400FT-7
PC133-222
HYB39S256400FTL-7
HYB39S256800FT-7
143MHz 32M x 8 SDRAM
HYB39S256800FTL-7
HYB39S256160FT-7
143MHz 16M x 16 SDRAM
HYB39S256160FTL-7
HYB39S256160FT-6
166MHz 16M x 16 SDRAM
Industrial Operating Temperature
HYI39S256800FT-7
PC133-222
143MHz 32M x 8 SDRAM
HYI39S256160FT-7
143MHz 16M x 16 SDRAM
Note: For product nomenclature see Chapter 6 of this data sheet
Rev. 1.42, 2007-09
03292006-TMTK-JFEU
5
P-TSOPII-54
Internet Data Sheet
HY[B/I]39S256[40/80/16][0/7]F[E/T/F](L)
256-MBit Synchronous DRAM
2
Configuration
This chapter contains the pin configuration table, the TSOP and FBGA package drawing, and the block diagrams for the ×4,
×8, ×16 organization of the SDRAM.
2.1
Pin Description
Listed below are the pin configurations sections for the various signals of the SDRAM.
TABLE 4
Pin Configuration of the SDRAM
Ball No.
Name
Pin
Type
Buffer
Type
Function
Clock Signals ×4/×8/×16 Organization
38,2F
CLK
I
LVTTL
Clock Signal CK
37, 3F
CKE
I
LVTTL
Clock Enable
Control Signals ×4/×8/×16 Organization
18, 8F
RAS
I
LVTTL
17, 7F
CAS
I
LVTTL
16, 9F
WE
I
LVTTL
19, 9G
CS
I
LVTTL
Row Address Strobe (RAS), Column Address Strobe (CAS), Write Enable (WE)
Chip Select
Address Signals ×4/×8/×16 Organization
20, 7G
BA0
I
LVTTL
21, 8G
BA1
I
LVTTL
23, 7H
A0
I
LVTTL
24, 8H
A1
I
LVTTL
25, 8J
A2
I
LVTTL
26, 7J
A3
I
LVTTL
29, 3J
A4
I
LVTTL
30, 2J
A5
I
LVTTL
31, 3H
A6
I
LVTTL
32, 2H
A7
I
LVTTL
33, 1H
A8
I
LVTTL
34, 3G
A9
I
LVTTL
22, 9H
A10
I
LVTTL
35, 2G
A11
I
LVTTL
36, 1G
A12
I
LVTTL
Rev. 1.42, 2007-09
03292006-TMTK-JFEU
Bank Address Signals 1:0
Address Signal 12:0, Address Signal 10/Auto precharge
6
Internet Data Sheet
HY[B/I]39S256[40/80/16][0/7]F[E/T/F](L)
256-MBit Synchronous DRAM
Ball No.
Name
Pin
Type
Buffer
Type
Function
Data Signals ×4 Organization
5, 8B
DQ0
I/O
LVTTL
11, 8D
DQ1
I/O
LVTTL
44, 2D
DQ2
I/O
LVTTL
50, 2B
DQ3
I/O
LVTTL
Data Signal Bus 3:0
Data Signals ×8 Organization
2, 8A
DQ0
I/O
LVTTL
5, 8B
DQ1
I/O
LVTTL
8, 8C
DQ2
I/O
LVTTL
11, 8D
DQ3
I/O
LVTTL
44, 2D
DQ4
I/O
LVTTL
47, 2C
DQ5
I/O
LVTTL
50, 2B
DQ6
I/O
LVTTL
53, 2A
DQ7
I/O
LVTTL
Data Signal Bus 7:0
Data Signals ×16 Organization
2, 8A
DQ0
I/O
LVTTL
4, 9B
DQ1
I/O
LVTTL
5, 8B
DQ2
I/O
LVTTL
7, 9C
DQ3
I/O
LVTTL
8, 8C
DQ4
I/O
LVTTL
10, 9D
DQ5
I/O
LVTTL
11, 8D
DQ6
I/O
LVTTL
13, 9E
DQ7
I/O
LVTTL
42, 1E
DQ8
I/O
LVTTL
44, 2D
DQ9
I/O
LVTTL
45, 1D
DQ10
I/O
LVTTL
47, 2C
DQ11
I/O
LVTTL
48, 1C
DQ12
I/O
LVTTL
50, 2B
DQ13
I/O
LVTTL
51, 1B
DQ14
I/O
LVTTL
53, 2A
DQ15
I/O
LVTTL
Data Signal Bus 15:0
Data Mask ×4/×8 Organization
39, 1F
DQM
I/O
LVTTL
Data Mask
Data Mask ×16 Organization
39, 1F
UDQM
I/O
LVTTL
Data Mask Upper Byte
15, 8E
LDQM
I/O
LVTTL
Data Mask Lower Byte
Power Supplies ×4/×8/×16 Organization
3B, 3D,
7A, 7C
VDDQ
PWR
Rev. 1.42, 2007-09
03292006-TMTK-JFEU
–
Power Supply
7
Internet Data Sheet
HY[B/I]39S256[40/80/16][0/7]F[E/T/F](L)
256-MBit Synchronous DRAM
Ball No.
Name
Pin
Type
Buffer
Type
Function
7E, 9A,
9J
VDD
PWR
–
Power Supply
3A, 3C,
7B, 7D
VSSQ
PWR
–
Power Supply Ground for DQs
1J, 1A,
3E
VSS
PWR
–
Power Supply Ground
Not connected ×4 Organization
2, 4, 7, 8, NC
10, 13,
15, 40,
42, 45,
47, 48,
51, 53,
1B, 1C,
1D, 1E,
2A, 2C,
2E, 8A,
8C, 8E,
9B, 9C,
9D, 9E
NC
–
Not connected
Not connected ×8 Organization
7, 10, 13, NC
15, 40,
42, 45,
48, 51,
1B, 1C,
1D, 1E,
2E, 8E,
9B, 9C,
9D, 9E
NC
–
Not connected
Not connected ×16 Organization
40, 2E
NC
NC
Rev. 1.42, 2007-09
03292006-TMTK-JFEU
–
Not connected
8
Internet Data Sheet
HY[B/I]39S256[40/80/16][0/7]F[E/T/F](L)
256-MBit Synchronous DRAM
2.2
Package P(G)–TSOPII–54
Listed below are the pin outs of the TSOP package.
FIGURE 1
Pinouts P(G)–TSOPII–54
0[ 0
[
0
[
6 ''
6''
6''
'4
'4
1&
6 ''4 6''4 6''4 '4
'4
1&
'4
1&
'4
6 664
6664 6664 '4
'4
1&
'4
1&
1&
6 ''4 6''4 6''4 '4
'4
1&
'4
1&
'4
6 664
6664 6664 '4
1&
1&
6 ''
6''
6''
/'4
0
:(
&$6
5$6
&6
%$
%$
$
$
3
$
$
$
$
1&
:(
&$6
5$6
&6
%$
%$
$
$3
$
$
$
$
1&
:(
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5$6
&6
%$
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$
$
$
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6 ''
6''
6''
6 66
666
666
1&
'4
'4
6 664
6664
6664
1&
'4
1&
'4
'4
'4
6 ''4 6''4 6''4
1&
1&
1&
'4
'4
'4
6 664
6664
6664
1&
'4
1&
'4
'4
'4
6 ''4 6''4 6''4
1&
1&
'4
6 66
666
666
1&
'40
&/.
&.(
$
$
$
$
$
$
$
$
1&
'40
&/.
&.(
$
$
$
$
$
$
$
$
1&
8'4
0
&/.
&.(
$
$
$
$
$
$
$
$
6 66
666
666
762
3,, P
LO[
PLO
P
PSLW FK
633
Rev. 1.42, 2007-09
03292006-TMTK-JFEU
9
Internet Data Sheet
HY[B/I]39S256[40/80/16][0/7]F[E/T/F](L)
256-MBit Synchronous DRAM
2.3
Package PG–TFBGA–54
Listed below are the ball outs of the TFBGA package.
• Figure 2 “Ballout for ×16 components, TFBGA-54 (top view)” on Page 10
• Figure 3 “Ballout for ×8 components, TFBGA-54 (top view)” on Page 11
• Figure 4 “Ballout for ×4 components, TFBGA-54 (top view)” on Page 12
FIGURE 2
Ballout for ×16 components, TFBGA-54 (top view)
666
'4
6664 $
6''4 '4
6''
'4 '4
6''4 %
6664 '4
'4
'4 '4
6664 &
6''4 '4
'4
'4
'4
6''4 '
6664 '4
'4
'4
1&
666
(
6''
/'4
0
'4
8'4
0
&/.
&.(
)
&$6
5$6
:(
$
$
$
*
%$
%$
&6
$
$
$
+
$
$
$
666
$
$
-
$
$
6''
033'
Rev. 1.42, 2007-09
03292006-TMTK-JFEU
10
Internet Data Sheet
HY[B/I]39S256[40/80/16][0/7]F[E/T/F](L)
256-MBit Synchronous DRAM
FIGURE 3
Ballout for ×8 components, TFBGA-54 (top view)
666
'4
6664 $
6''4 '4
6''
1&
'4
6''4 %
6664 '4
1&
1&
'4
6664 &
6''4 '4
1&
1&
'4
6''4 '
6664 '4
1&
1&
1&
666
(
6''
1&
1&
'40
&/.
&.(
)
&$6
5$6
:(
$
$
$
*
%$
%$
&6
$
$
$
+
$
$
$
666
$
$
-
$
$
6''
033'
Rev. 1.42, 2007-09
03292006-TMTK-JFEU
11
Internet Data Sheet
HY[B/I]39S256[40/80/16][0/7]F[E/T/F](L)
256-MBit Synchronous DRAM
FIGURE 4
Ballout for ×4 components, TFBGA-54 (top view)
$
6''4 1&
6''
6''4 %
6664 '4
1&
1&
6664 &
6''4 1&
1&
1&
'4
6''4 '
6664 '4
1&
1&
1&
666
(
6''
1&
1&
'40
&/.
&.(
)
&$6
5$6
:(
$
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$
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$
+
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666
$
$
-
$
$
6''
666
1&
6664 1&
'4
1&
033'
Rev. 1.42, 2007-09
03292006-TMTK-JFEU
12
Internet Data Sheet
HY[B/I]39S256[40/80/16][0/7]F[E/T/F](L)
256-MBit Synchronous DRAM
3
Functional Description
This chapter contains the functional description.
TABLE 5
Truth Table: Operation Command
Operation
Device State
CKE
n-11)2)
CKE
n1)2)
DQM
1)2)
BA0
BA11)2)
AP=
A101)2)
Addr. CS1 RAS
1)2)
)2)
1)2)
CAS1 WE
)2)
1)2)
Bank Active
Idle3)
H
X
X
V
V
V
L
L
H
H
Bank Precharge
Any
H
X
X
V
L
X
L
L
H
L
Precharge All
Any
H
X
X
X
H
X
L
L
H
L
Write
Active3)
H
X
X
V
L
V
L
H
L
L
Write with Auto precharge
Active
3)
H
X
X
V
H
V
L
H
L
L
Read
Active3)
H
X
X
V
L
V
L
H
L
H
3)
H
X
X
V
H
V
L
H
L
H
Read with Auto precharge
Active
Mode Register Set
Idle
H
X
X
V
V
V
L
L
L
L
No Operation
Any
H
X
X
X
X
X
L
H
H
H
Burst Stop
Active
H
X
X
X
X
X
L
H
H
L
Device Deselect
Any
H
X
X
X
X
X
H
X
X
X
Auto Refresh
Idle
H
H
X
X
X
X
L
L
L
H
Self Refresh Entry
Idle
H
L
X
X
X
X
L
L
L
H
Self Refresh Exit
Idle (Self Refr.)
L
H
X
X
X
X
H
X
X
X
L
H
H
X
Power Down/
Clock Suspend Entry
Active or Idle
or Burst
H
L
X
X
X
X
H
X
X
X
L
H
H
H
Power Down/
Clock Suspend Exit
Active or Idle
or Burst
L
H
X
X
X
L
H
H
H
Data Write/
Output Enable
Active
H
X
L
X
X
X
X
X
X
X
Data Write/
Output Disable
Active
H
X
H
X
X
X
X
X
X
X
H
X
X
X
X
1) V = Valid, x = Don’t Care, L = Low Level, H = High Level
2) CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before the commands are provided.
3) This is the state of the banks designated by BA0, BA1 signals.
Rev. 1.42, 2007-09
03292006-TMTK-JFEU
13
Internet Data Sheet
HY[B/I]39S256[40/80/16][0/7]F[E/T/F](L)
256-MBit Synchronous DRAM
%$ %$
$
$
$
$
:%/
$
$
70
Z
UHJDGGU
$
$
$
$
$
$
&/
%7
%/
Z
Z
Z
$
03%6
TABLE 6
Mode Register Definition (BA1:0 = 00B)
Field
Bits
Type
Description
BL
2:0
w
Burst Length
Note: All other bit combinations are RESERVED
000B
001B
010B
011B
111B
1
2
4
8
Full Page (Sequential burst type only)
BT
3
Burst Type
Sequential
0B
1B
Interleaved
CL
6:4
CAS Latency
Number of full clocks from read command to first data valid window.
Note: All other bit combinations are RESERVED.
010B 2
011B 3
TM
8:7
Test Mode
Note: All other bit combinations are RESERVED.
00B
WBL
Mode register set
9
Write Burst Length
0B
Burst write
1B
Single bit write
12:10
Reserved, set to zero
Rev. 1.42, 2007-09
03292006-TMTK-JFEU
14
Internet Data Sheet
HY[B/I]39S256[40/80/16][0/7]F[E/T/F](L)
256-MBit Synchronous DRAM
TABLE 7
Burst Length and Sequence
Burst Length
Starting Column Address
A2
A1
A0
Type=Sequential
Type=Interleaved
0
0–1
0–1
1
1–0
1–0
0
0
0–1–2–3
0–1–2–3
0
1
1–2–3–0
1–0–3–2
1
0
2–3–0–1
2–3–0–1
2
4
8
FullPage
Order of Accesses Within a Burst
1
1
3–0–1–2
3–2–1–0
0
0
0
0–1–2–3–4–5–6–7
0–1–2–3–4–5–6–7
0
0
1
1–2–3–4–5–6–7–0
1–0–3–2–5–4–7–6
0
1
0
2–3–4–5–6–7–0–1
2–3–0–1–6–7–4–5
0
1
1
3–4–5–6–7–0–1–2
3–2–1–0–7–6–5–4
1
0
0
4–5–6–7–0–1–2–3
4–5–6–7–0–1–2–3
1
0
1
5–6–7–0–1–2–3–4
5–4–7–6–1–0–3–2
1
1
0
6–7–0–1–2–3–4–5
6–7–4–5–2–3–0–1
1
1
1
7–0–1–2–3–4–5–6
7–6–5–4–3–2–1–0
Cn, Cn+1, Cn+2 ....
not supported
n
Notes
1.
2.
3.
4.
For a burst length of two, A1-Ai selects the two-data-element block; A0 selects the first access within the block.
For a burst length of four, A2-Ai selects the four-data-element block; A0-A1 selects the first access within the block.
For a burst length of eight, A3-Ai selects the eight-data- element block; A0-A2 selects the first access with in the block.
Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.
Rev. 1.42, 2007-09
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Internet Data Sheet
HY[B/I]39S256[40/80/16][0/7]F[E/T/F](L)
256-MBit Synchronous DRAM
4
Electrical Characteristics
This chapter lists the electrical characteristics.
4.1
Operating Conditions
This chapter describes the operating conditions.
TABLE 8
Absolute Maximum Ratings
Parameter
Input / Output voltage relative to VSS
Voltage on VDD supply relative to VSS
Voltage on VDDQ supply relative to VSS
Operating Temperature for HYB...
Operating Temperature for HYI...
Storage temperature range
Power dissipation per SDRAM component
Data out current (short circuit)
Symbol
Limit Values
VIN, VOUT
VDD
VDDQ
TA
TA
TSTG
PD
IOUT
Unit
Note/
Test Condition
Min.
Max.
– 1.0
+4.6
V
–
– 1.0
+4.6
V
–
– 1.0
+4.6
V
–
0
+70
°C
–
– 40
+85
°C
–
-55
+150
°C
–
–
1
W
–
–
50
mA
–
Attention: Stresses above the max. values listed here may cause permanent damage to the device. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings
are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated
circuit.
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Internet Data Sheet
HY[B/I]39S256[40/80/16][0/7]F[E/T/F](L)
256-MBit Synchronous DRAM
TABLE 9
DC Characteristics
Parameter
Symbol
Values
Min. Max.
VDD
I/O Supply Voltage
VDDQ
Input high voltage
VIH
Input low voltage
VIL
Output high voltage (IOUT = – 4.0 mA)
VOH
Output low voltage (IOUT = 4.0 mA)
VOL
Input leakage current, any input (0 V < VIN < VDD, all other inputs = 0 V) IIL
IOL
Output leakage current (DQs are disabled, 0 V < VOUT < VDDQ)
Supply Voltage
Unit Note1)/
Test Condition
3.0
3.6
V
2)
3.0
3.6
V
2)
2.0
VDDQ + 0.3 V
2)3)
– 0.3 +0.8
V
2)3)
2.4
–
V
2)
–
0.4
V
2)
–5
+5
μA
–
–5
+5
μA
–
1) TA = 0 to 70 °C
2) All voltages are referenced to VSS
3) VIH may overshoot to VDDQ + 2.0 V for pulse width of < 4ns with 3.3 V. VIL may undershoot to -2.0 V for pulse width < 4.0 ns with 3.3 V.
Pulse width measured at 50% points with amplitude measured peak to DC reference.
TABLE 10
Input and Output Capacitances
Parameter
Symbol
Values
1)
Min.
Max.
Unit
Note
2)
Input Capacitances: CK
CI1
2.5
3.5
pF
Input Capacitance
(A0-A12, BA0, BA1, RAS, CAS, WE, CS, CKE, DQM)
CI2
2.5
3.8
pF
Input/Output Capacitance (DQ)
CI0
4.0
6.0
pF
1) Capacitance values are shown for TSOP-54 packages. Capacitance values for TFBGA packages are lower by 0.5 pF
2) TA = 0 to 70 °C; VDD,VDDQ = 3.3 V ± 0.3 V, f = 1 MHz
TABLE 11
IDD Conditions
Parameter
Symbol
Operating Current
One bank active, Burst length = 1
IDD1
Precharge Standby Current in Power Down Mode
IDD2P
IDD2N
IDD3N
IDD3P
IDD4
Recharge Standby Current in Non-Power Down Mode
No Operating Current
Active state (max. 4 banks)
Burst Operating Current
Read command cycling
IDD5
Auto Refresh Current
Auto Refresh command cycling
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Internet Data Sheet
HY[B/I]39S256[40/80/16][0/7]F[E/T/F](L)
256-MBit Synchronous DRAM
Parameter
Symbol
Self Refresh Current (standard components)
Self Refresh Mode, CKE=0.2V, tCK=infinity
IDD6
Self Refresh Current (low power components)
Self Refresh Mode, CKE=0.2V, tCK=infinity
TABLE 12
IDD Specifications and Conditions
Symbol
–6
–7
Unit Note/ Test Condition1)2)
Max.
IDD1
IDD2P
IDD2N
IDD3N
IDD3P
IDD4
IDD5
tRC = tRC(min), IO = 0 mA
CS =VIH (min.), CKE ≤VIL(max)
CS =VIH (min.), CKE≥ VIH(min)
CS = VIH(min), CKE ≥VIH(min.)
CS = VIH(min), CKE ≤ VIL(max.)
tRFC = tRFC(min)
tRFC= 7.8 μs
IDD6
100
80
mA
3)4)
2
2
mA
2)
26
22
mA
2)
40
35
mA
2)
5
5
mA
2)
65
57
mA
2)3)
168
142
mA
5)
25
25
mA
3
3
mA
1.05 1.05 mA
Standard components
Low power components 6)
1) Currents values will be added when available.
2) TA = 0 to 70 °C; VSS = 0 V; VDD, VDDQ = 3.3 V ± 0.3 V
3) These parameters depend on the cycle rate. All values are measured at 166 MHz for -6, at 133 MHz for -7 and -7.5 and at 100 MHz for 8 components with the outputs open. Input signals are changed once during tCK.
4) These parameters are measured with continuous data stream during read access and all DQ toggling. CL=3 and BL=4 is assumed and
the VDDQ current is excluded.
5) tRFC = tRFC(min) “burst refresh”, tRFC =7.8 μs “distributed refresh“
6) 1.05 mA at 85 °C, 1.00 mA at 60 °C
Rev. 1.42, 2007-09
03292006-TMTK-JFEU
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Internet Data Sheet
HY[B/I]39S256[40/80/16][0/7]F[E/T/F](L)
256-MBit Synchronous DRAM
4.2
AC Characteristics
This chapter lists the AC characteristics.
TABLE 13
AC Timing - Absolute Specifications
Parameter
Symbol
–7
–6
PC143–333
PC166–333
Min.
Max.
Min.
Max.
Unit
Note1)2)3)
Clock and Clock Enable
Clock Frequency
tCK
7
7.5
—
—
6
7.5
—
—
ns
ns
CL3
CL2
Access Time from Clock
tAC
—
—
5.4
5.4
—
—
5.4
5.4
ns
ns
CL3
CL2
3)4)5)
Clock High Pulse Width
Clock Low Pulse Width
Transition time
tCH
tCL
tT
2.5
—
2
—
ns
2.5
—
2
—
ns
0.3
1.2
0.3
1.2
ns
tIS
tIH
tCKS
tCKH
tRSC
tSB
1.5
—
1.5
—
ns
6)
0.8
—
0.8
—
ns
6)
1.5
—
1.5
—
ns
6)
0.8
—
0.8
—
ns
6)
2
—
2
—
tCK
0
7
0
6
ns
tRCD
tRP
tRAS
tRC
tRFC
tRRD
tCCD
15
—
15
—
ns
7)
15
—
15
—
ns
7)
37
100k
36
100k
ns
7)
60
—
60
—
ns
7)
63
—
60
—
ns
14
—
12
—
ns
1
—
1
—
tCK
tREF
tSREX
tOH
–
64
–
64
ms
1
—
1
—
tCK
3
—
2.5
—
ns
tLZ
tHZ
tDQZ
0
—
0
—
ns
3
7
3
6
ns
—
2
—
2
tCK
Setup and Hold Times
Input Setup Time
Input Hold Time
CKE Setup Time
CKE Hold Time
Mode Register Set-up to Active delay
Power Down Mode Entry Time
Common Parameters
Row to Column Delay Time
Row Precharge Time
Row Active Time
Row Cycle Time
Row Cycle Time during Auto Refresh
Activate(a) to Activate(b) Command period
CAS(a) to CAS(b) Command period
7)
Refresh Cycle
Refresh Period (8192 cycles)
Self Refresh Exit Time
Data Out Hold Time
Read Cycle
Data Out to Low Impedance Time
Data Out to High Impedance Time
DQM Data Out Disable Latency
Rev. 1.42, 2007-09
03292006-TMTK-JFEU
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3)5)
Internet Data Sheet
HY[B/I]39S256[40/80/16][0/7]F[E/T/F](L)
256-MBit Synchronous DRAM
Parameter
Symbol
–7
–6
PC143–333
PC166–333
Unit
Note1)2)3)
Min.
Max.
Min.
Max.
14
—
12
—
ns
8)
9)
—
tCK
tCK
Write Cycle
tWR
Last Data Input to Precharge
(Write without Auto Precharge)
Last Data Input to Activate(Write with Auto Precharge) tDAL(min.)
tDQW
DQM Write Mask Latency
0
—
0
1) TA = 0 to 70 °C; VSS = 0 V; VDD, VDDQ = 3.3 V ± 0.3 V, tT = 1 ns
2) For proper power-up see the operation section of this data sheet.
3) AC timing tests for LV-TTL versions have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.4 V crossover point. The transition
time is measured between VIH and VIL. All AC measurements assume tT = 1 ns with the AC output load circuit shown in figure below.
Specified tAC and tOH parameters are measured with a 50 pF only, without any resistive termination and with an input signal of 1V / ns edge
rate between 0.8 V and 2.0 V.
4) If clock rising time is longer than 1 ns, a time (tT/2 - 0.5) ns has to be added to this parameter.
5) Access time from clock tac is 4.6 ns for PC133 components with no termination and 0 pF load,Data out hold time toh is 1.8 ns for PC133
components with no termination and 0 pF load.
6) If tT is longer than 1 ns, a time (tT - 1) ns has to be added to this parameter.
7) These parameter account for the number of clock cycles and depend on the operating frequency of the clock, as follows:the number of
clock cycles = specified value of timing period (counted in fractions as a whole number)
8) It is recommended to use two clock cycles between the last data-in and the precharge command in case of a write command without AutoPrecharge. One clock cycle between the last data-in and the precharge command is also supported, but restricted to cycle times tck greater
or equal the specified tWR value, where tck is equal to the actual system clock time.
9) When a Write command with Auto Precharge has been issued, a time of tDAL(min) has be fullfilled before the next Activate Command can
be applied. For each of the terms, if not already an integer, round up to the next highest integer. tCK is equal to the actual system clock time.
FIGURE 5
Measurement conditions for tAC and tOH
t CH
2 .4 V
0 .4 V
1 .4 V
CLO C K
tCL
t IS
tT
t IH
IN P U T
1 .4 V
tA C
t LZ
tAC
tOH
OUTPUT
1.4 V
I/O
t HZ
50 pF
IO.vsd
Rev. 1.42, 2007-09
03292006-TMTK-JFEU
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Measurement conditions for
tAC and tOH
Internet Data Sheet
HY[B/I]39S256[40/80/16][0/7]F[E/T/F](L)
256-MBit Synchronous DRAM
5
Package Outlines
This chapter contains the package outlines of the products.
FIGURE 6
*$8
*(3
/$1(
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ƒ“
ƒ “ [ [
6($7 ,1
*3
/$1(
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0 [
0$
;
“ ƒ “
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Package Outline P(G)-TSOPII-54 (top view)
0$
;
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D[S HUVLGH
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D[S HUVLGH
Notes
1. Drawing according to ISO 8015
2. Dimensions in mm
3. General tolerances +/- 0.15
Rev. 1.42, 2007-09
03292006-TMTK-JFEU
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*3; Internet Data Sheet
HY[B/I]39S256[40/80/16][0/7]F[E/T/F](L)
256-MBit Synchronous DRAM
FIGURE 7
Package Outline P(G)-TFBGA-54
[ 0
$;
%
$
[ 0$
;
&
0
,1
0
$;
&
¡“ [
¡0 &$ % &6($7,1
*3
/$1(
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LGGOHRI3DFN DJ HV(
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*3$ Notes
1. Drawing according to ISO 8015
2. Dimensions in mm
3. General tolerances +/- 0.15
Rev. 1.42, 2007-09
03292006-TMTK-JFEU
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Internet Data Sheet
HY[B/I]39S256[40/80/16][0/7]F[E/T/F](L)
256-MBit Synchronous DRAM
6
Product Nomenclature
For reference the Qimonda SDRAM component nomenclature is enclosed in this chapter.
TABLE 14
Examples for Nomenclature Fields
Example for
Field Number
1
2
3
4
5
SDRAM
HYB
39
S
256
SDRAM
HYI
39
S
256
6
7
8
9
10
11
80
0
F
F
–6
16
0
F
E
–7
TABLE 15
Memory Components
Field
Description
Values
Coding
1
Qimonda Component Prefix
HYB
Memory components
HYI
Memory components, industrial temperature range (-40°C – +85 °C)
2
Interface Voltage [V]
39
3.3 V
3
DRAM Technology
S
Single Data Rate SDRAM
4
Component Density [Mbit]
128
128 Mbit
256
256 Mbit
512
512 Mbit
40
×4
80
×8
16
×16
0 .. 9
look up table
5+6
Number of I/Os
7
Product Variations
8
Die Revision
9
Package,
Lead-Free Status
C
Third
D
Fourth
F
Fifth
E
TSOP, lead- and halogen-free
F
FBGA, lead- and halogen-free
10
Power
–
Standard power product
11
Speed Grade
–6
PC166-333
–7
PC143-333, PC133-222
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Internet Data Sheet
HY[B/I]39S256[40/80/16][0/7]F[E/T/F](L)
256-MBit Synchronous DRAM
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Pinouts P(G)–TSOPII–54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Ballout for ×16 components, TFBGA-54 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Ballout for ×8 components, TFBGA-54 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Ballout for ×4 components, TFBGA-54 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Measurement conditions for tAC and tOH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Package Outline P(G)-TSOPII-54 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Package Outline P(G)-TFBGA-54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
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03292006-TMTK-JFEU
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Internet Data Sheet
HY[B/I]39S256[40/80/16][0/7]F[E/T/F](L)
256-MBit Synchronous DRAM
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering Information for RoHS Compliant Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Ordering Information for Lead-Containing Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Configuration of the SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Truth Table: Operation Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Mode Register Definition (BA1:0 = 00B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Burst Length and Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Input and Output Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
IDD Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
IDD Specifications and Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
AC Timing - Absolute Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Examples for Nomenclature Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Memory Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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03292006-TMTK-JFEU
25
Internet Data Sheet
HY[B/I]39S256[40/80/16][0/7]F[E/T/F](L)
256-MBit Synchronous DRAM
Table of Contents
1
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
2.1
2.2
2.3
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Package P(G)–TSOPII–54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Package PG–TFBGA–54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4
4.1
4.2
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6
Product Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Rev. 1.42, 2007-09
03292006-TMTK-JFEU
26
Internet Data Sheet
Edition 2007-09
Published by Qimonda AG
Gustav-Heinemann-Ring 212
D-81739 München, Germany
© Qimonda AG 2007.
All Rights Reserved.
Legal Disclaimer
The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics
(“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind,
including without limitation warranties of non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office.
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in question please
contact your nearest Qimonda Office.
Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a
failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect
the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human
body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health
of the user or other persons may be endangered.
www.qimonda.com
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