Qimonda HYI39SC128160FE 128-mbit synchronous dram Datasheet

March 2007
HYB39S C12880 0 FE
HYB39S C12816 0 FE
HYI39SC128800FE
HYI39SC128160FE
128-MBit Synchronous DRAM
Green Product
SDRAM
Internet Data Sheet
Rev. 1.1
Internet Data Sheet
HY[B/I]39SC128[800/160]FE
128-MBit Synchronous DRAM
HYB39SC128800FE, HYB39SC128160FE, HYI39SC128800FE, HYI39SC128160FE
Revision History: 2007-02, Rev. 1.1
Page
Subjects (major changes since last revision)
All
Adapted internet edition
9
Corrected block diagram
13
Corrected mode register definition
Previous Revision: 2006-09, Rev. 1.0
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09072006-N4GC-EREN
2
Internet Data Sheet
HY[B/I]39SC128[800/160]FE
128-MBit Synchronous DRAM
1
Overview
This chapter lists all main features of the product family HY[B/I]39S128[800/160]FE and the ordering information.
1.1
•
•
•
•
•
•
•
•
•
Features
Fully Synchronous to Positive Clock Edge
0 to 70 °C Operating Temperature for HYB...
-40 to 85 °C Operating Temperature for HYI...
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2 & 3
Programmable Wrap Sequence: Sequential or Interleave
Programmable Burst Length: 1, 2, 4, 8 and full page
Multiple Burst Read with Single Write Operation
Automatic and Controlled Precharge Command
•
•
•
•
•
•
•
•
•
Data Mask for Read / Write control (×8)
Data Mask for Byte Control (×16)
Auto Refresh (CBR) and Self Refresh
Power Down and Clock Suspend Mode
4096 refresh cycles / 64 ms (15.6 µs)
Random Column Address every CLK (1-N Rule)
Single 3.3 V ± 0.3 V Power Supply
LVTTL Interface
Plastic Packages: PG–TSOPII–54 400 mil width
TABLE 1
Performance
Product Type Speed Code
–6
–7
Unit
Speed Grade
PC166–333
PC133–222
—
166
143
MHz
6
7
ns
5.4
5.4
ns
7.5
7.5
ns
5.4
5.4
ns
Max. Clock Frequency
@CL3
@CL2
1.2
fCK3
tCK3
tAC3
tCK2
tAC2
Description
The HY[B/I]39S128[800/160]FE are four bank Synchronous
DRAM’s
organized
as 16 MBit
×8
and 8 Mbit ×16
respectively. These synchronous devices achieve high speed
data transfer rates for CAS latencies by employing a chip
architecture that prefetches multiple bits and then
synchronizes the output data to a system clock. The chip is
fabricated with Qimonda advanced 0.11 µm 128-MBit DRAM
process technology.
The device is designed to comply with all industry standards
set for synchronous DRAM products, both electrically and
mechanically. All of the control, address, data input and
Rev. 1.1, 2007-02
09072006-N4GC-EREN
output circuits are synchronized with the positive edge of an
externally supplied clock.
Operating the four memory banks in an interleave fashion
allows random access operation to occur at a higher rate than
is possible with standard DRAMs. A sequential and gapless
data rate is possible depending on burst length, CAS latency
and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are
supported. These devices operate with a single 3.3 V ± 0.3 V
power supply. All 128-Mbit components are available in PG–
TSOPII–54 packages.
3
Internet Data Sheet
HY[B/I]39SC128[800/160]FE
128-MBit Synchronous DRAM
TABLE 2
Ordering Information for RoHS Compliant Products
Product Type
Speed Grade
Description
Package
Note
166MHz 16M ×SDRAM
PG-TSOPII-54
1)
PG-TSOPII-54
1)
Standard Operating Temperature
HYB39SC128800FE-6
PC166–333
166MHz 8M ×16 SDRAM
HYB39SC128160FE-6
HYB39SC128800FE-7
PC133–222
143MHz 16M ×8 SDRAM
143MHz 8M ×16 SDRAM
HYB39SC128160FE-7
Industrial Operating Temperature
HYI39SC128800FE-6
PC166–333
166MHz 8M ×16 SDRAM
HYI39SC128160FE-6
HYI39SC128800FE-7
HYI39SC128160FE-7
166MHz 16M ×8 SDRAM
PC133–222
143MHz 16M ×8 SDRAM
143MHz 8M ×16 SDRAM
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 1.1, 2007-02
09072006-N4GC-EREN
4
Internet Data Sheet
HY[B/I]39SC128[800/160]FE
128-MBit Synchronous DRAM
2
Pin Configuration
This chapter contains the pin configuration for the ×8, ×16 organization of the SDRAM.
2.1
Pin Configuration
Listed below are the pin configurations sections for the various signals of the SDRAM.
TABLE 3
Pin Configuration of the SDRAM
Ball No.
Name
Pin
Type
Buffer
Type
Function
Clock Signals ×8/×16 Organization
38
CLK
I
LVTTL
Clock Signal CK
37
CKE
I
LVTTL
Clock Enable
Control Signals ×8/×16 Organization
18
RAS
I
LVTTL
17
CAS
I
LVTTL
16
WE
I
LVTTL
19
CS
I
LVTTL
Row Address Strobe (RAS), Column Address Strobe (CAS), Write Enable (WE)
Chip Select
Address Signals ×8/×16 Organization
20
BA0
I
LVTTL
21
BA1
I
LVTTL
23
A0
I
LVTTL
24
A1
I
LVTTL
25
A2
I
LVTTL
26
A3
I
LVTTL
29
A4
I
LVTTL
30
A5
I
LVTTL
31
A6
I
LVTTL
32
A7
I
LVTTL
33
A8
I
LVTTL
34
A9
I
LVTTL
22
A10
I
LVTTL
35
A11
I
LVTTL
Rev. 1.1, 2007-02
09072006-N4GC-EREN
Bank Address Signals 1:0
Address Signal 9:0, Address Signal 10/Auto precharge
5
Internet Data Sheet
HY[B/I]39SC128[800/160]FE
128-MBit Synchronous DRAM
Ball No.
Name
Pin
Type
Buffer
Type
Function
Data Signals ×8 Organization
2
DQ0
I/O
LVTTL
5
DQ1
I/O
LVTTL
8
DQ2
I/O
LVTTL
11
DQ3
I/O
LVTTL
44
DQ4
I/O
LVTTL
47
DQ5
I/O
LVTTL
50
DQ6
I/O
LVTTL
53
DQ7
I/O
LVTTL
Data Signal Bus [15:0]
Data Signals ×16 Organization
2
DQ0
I/O
LVTTL
4
DQ1
I/O
LVTTL
5
DQ2
I/O
LVTTL
7
DQ3
I/O
LVTTL
8
DQ4
I/O
LVTTL
10
DQ5
I/O
LVTTL
11
DQ6
I/O
LVTTL
13
DQ7
I/O
LVTTL
42
DQ8
I/O
LVTTL
44
DQ9
I/O
LVTTL
45
DQ10
I/O
LVTTL
47
DQ11
I/O
LVTTL
48
DQ12
I/O
LVTTL
50
DQ13
I/O
LVTTL
51
DQ14
I/O
LVTTL
53
DQ15
I/O
LVTTL
Data Signal Bus [15:0]
Data Mask ×8 Organization
39
DQM
I/O
LVTTL
Data Mask
Data Mask ×16 Organization
39
UDQM
I/O
LVTTL
Data Mask Upper Byte
15
LDQM
I/O
LVTTL
Data Mask Lower Byte
Power Supplies ×8/×16 Organization
9
14
46
41
VDDQ
VDD
VSSQ
VSS
PWR
—
Power Supply
PWR
—
Power Supply
PWR
—
Power Supply Ground for DQs
PWR
—
Power Supply Ground
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6
Internet Data Sheet
HY[B/I]39SC128[800/160]FE
128-MBit Synchronous DRAM
Ball No.
Name
Pin
Type
Buffer
Type
Function
Not connected ×8 Organization
4, 7, 10,
13, 15,
36, 40,
42, 45,
48, 51
NC
NC
—
Not connected
Not connected ×16 Organization
36, 40
NC
NC
—
Not connected
FIGURE 1
Pin Configuration PG–TSOPII–54
[
[
9
'
'
9
'
'
'
4
'
4
9
'
'
4
9
'
'
4
'
4
'
4
1
&
'
4
9
6
6
4
9
6
6
4
'
4
'
4
1
&
'
4
9
'
'
4
9
'
'
4
'
4
'
4
1
&
'
4
9
6
6
4
9
6
6
4
'
4
1
&
9
'
'
9
'
'
/
'
4
0
:
(
&
$6
5
$6
&
6
%
$
%
$
$
$3
$
$
$
$
1
&
:
(
&
$6
5
$6
&
6
%
$
%
$
$
$3
$
$
$
$
9
'
'
9
'
'
9
6
6
9
6
6
'
4
'
4
9
9
6
6
4
6
6
4
1
&
'
4
'
4
'
4
9
'
'
4 9
'
'
4
1
&
'
4
'
4
'
4
9
9
6
6
4
6
6
4
1
&
'
4
'
4
'
4
9
'
'
4 9
'
'
4
4
1
&
'
9
6
6
9
6
6
1
&
'
4
0
&
/
.
&
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(
1&
$
$
$
$
$
$
$
1
&
8
'
4
0
&
/
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&
.
(
1&
$
$
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$
$
$
9
6
6
9
6
6
7
6
2
3
,
,
P
L
O[
PL
O
P
PSL
W
F
K
Rev. 1.1, 2007-02
09072006-N4GC-EREN
7
PSSV
Internet Data Sheet
HY[B/I]39SC128[800/160]FE
128-MBit Synchronous DRAM
3
Functional Description
This chapter lists all defined commands and their usage for this Synchronous DRAM.
TABLE 4
Truth Table: Operation Command
Operation
Device State
CKE
n-11)2)
CKE
n1)2)
DQM
1)2)
BA0
BA11)2)
AP=
A101)2)
Addr. CS1 RAS
1)2)
)2)
1)2)
CAS1 WE
)2)
1)2)
Bank Active
Idle3)
H
X
X
V
V
V
L
L
H
H
Bank Precharge
Any
H
X
X
V
L
X
L
L
H
L
Precharge All
Any
H
X
X
X
H
X
L
L
H
L
Write
Active3)
H
X
X
V
L
V
L
H
L
L
Write with Auto
precharge
Active
3)
H
X
X
V
H
V
L
H
L
L
Read
Active3)
H
X
X
V
L
V
L
H
L
H
3)
H
X
X
V
H
V
L
H
L
H
Read with Auto
precharge
Active
Mode Register Set
Idle
H
X
X
V
V
V
L
L
L
L
No Operation
Any
H
X
X
X
X
X
L
H
H
H
Burst Stop
Active
H
X
X
X
X
X
L
H
H
L
Device Deselect
Any
H
X
X
X
X
X
H
X
X
X
Auto Refresh
Idle
H
H
X
X
X
X
L
L
L
H
Self Refresh Entry
Idle
H
L
X
X
X
X
L
L
L
H
Self Refresh Exit
Idle
(Self Refr.)
L
H
X
X
X
X
H
X
X
X
L
H
H
X
Clock Suspend Entry
Active
H
L
X
X
X
X
X
X
X
X
Power Down Entry
(Precharge or active
standby)
Idle
H
L
X
X
X
X
H
X
X
X
L
H
H
H
Clock Suspend Exit
Active4)
L
H
X
X
X
X
X
X
X
X
Power Down Exit
Any
(Power Down)
L
H
X
X
X
X
H
X
X
X
L
H
H
L
Data Write/Output
Enable
Active
H
X
L
X
X
X
X
X
X
X
Data Write/Output
Disable
Active
H
X
H
X
X
X
X
X
X
X
1)
2)
3)
4)
Active
V = Valid, x = Don’t Care, L = Low Level, H = High Level
CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before the commands are provided.
This is the state of the banks designated by BA0, BA1 signals.
Power Down Mode can not be entered in a burst cycle. When this command asserted in the burst mode cycle device is in clock suspend
mode.
Rev. 1.1, 2007-02
09072006-N4GC-EREN
8
Internet Data Sheet
HY[B/I]39SC128[800/160]FE
128-MBit Synchronous DRAM
%$ %$
$
$
$
$
:%/
$
$
$
70
Z
UHJDGGU
$
$
$
$
$
&/
%7
%/
Z
Z
Z
$
03%6
TABLE 5
Mode Register Definition (BA[1:0] = 00B)
Field
Bits
Type
Description
BL
[2:0]
w
Burst Length
Number of sequential bits per DQ related to one read/write command, see
Table 6.
Note: All other bit combinations are RESERVED
000B
001B
010B
011B
111B
1
2
4
8
Full Page (Sequential burst type only)
BT
3
Burst Type
0B
Sequential
1B
Interleaved
CL
[6:4]
CAS Latency
Number of full clocks from read command to first data valid window.
Note: All other bit combinations are RESERVED.
010B 2
011B 3
TM
[8:7]
Test Mode
Note: All other bit combinations are RESERVED.
00B
Mode register set
WBL
9
Write Burst Length
0B
Burst write
1B
Single bit write
—
[12:10]
Reserved, set to zero
TABLE 6
Burst Length and Sequence
Burst Length
2
Starting Column Address
Order of Accesses Within a Burst
A2
A1
A0
Type=Sequential
Type=Interleaved
—
—
0
0–1
0–1
—
—
1
1–0
1–0
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09072006-N4GC-EREN
9
Internet Data Sheet
HY[B/I]39SC128[800/160]FE
128-MBit Synchronous DRAM
Burst Length
4
8
FullPage
Starting Column Address
Order of Accesses Within a Burst
A2
A1
A0
Type=Sequential
Type=Interleaved
—
0
0
0–1–2–3
0–1–2–3
—
0
1
1–2–3–0
1–0–3–2
—
1
0
2–3–0–1
2–3–0–1
—
1
1
3–0–1–2
3–2–1–0
0
0
0
0–1–2–3–4–5–6–7
0–1–2–3–4–5–6–7
0
0
1
1–2–3–4–5–6–7–0
1–0–3–2–5–4–7–6
0
1
0
2–3–4–5–6–7–0–1
2–3–0–1–6–7–4–5
0
1
1
3–4–5–6–7–0–1–2
3–2–1–0–7–6–5–4
1
0
0
4–5–6–7–0–1–2–3
4–5–6–7–0–1–2–3
1
0
1
5–6–7–0–1–2–3–4
5–4–7–6–1–0–3–2
1
1
0
6–7–0–1–2–3–4–5
6–7–4–5–2–3–0–1
1
1
1
7–0–1–2–3–4–5–6
7–6–5–4–3–2–1–0
Cn, Cn+1, Cn+2 ....
Not supported
n
Notes
1.
2.
3.
4.
For a burst length of two, A1-Ai selects the two-data-element block; A0 selects the first access within the block.
For a burst length of four, A2-Ai selects the four-data-element block; A0-A1 selects the first access within the block.
For a burst length of eight, A3-Ai selects the eight-data- element block; A0-A2 selects the first access with in the block.
Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.
Rev. 1.1, 2007-02
09072006-N4GC-EREN
10
Internet Data Sheet
HY[B/I]39SC128[800/160]FE
128-MBit Synchronous DRAM
4
Electrical Characteristics
4.1
Operating Conditions
TABLE 7
Absolute Maximum Ratings
Parameter
Input / Output voltage relative to VSS
Voltage on VDD supply relative to VSS
Voltage on VDDQ supply relative to VSS
Operating Temperature for HYB...
Operating Temperature for HYI...
Storage temperature range
Power dissipation per SDRAM component
Data out current (short circuit)
Symbol
Limit Values
VIN, VOUT
VDD
VDDQ
TA
TA
TSTG
PD
IOUT
Unit
Note/
Test Condition
Min.
Max.
–1.0
+4.6
V
—
–1.0
+4.6
V
—
–1.0
+4.6
V
—
0
+70
°C
—
–40
+85
°C
—
–55
+150
°C
—
—
1
W
—
—
50
mA
—
Attention: Stresses above the max. values listed here may cause permanent damage to the device. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings
are absolute ratings; exceeding only one of these values maycause irreversible damage to the integrated
circuit.
TABLE 8
DC Characteristics
Parameter
Supply Voltage
I/O Supply Voltage
Input high voltage
Input low voltage
Output high voltage (IOUT = – 4.0 mA)
Output low voltage (IOUT = 4.0 mA)
Input leakage current, any input
(0 V < VIN < VDD, all other inputs = 0 V)
Symbol
Values
VDD
VDDQ
VIH
VIL
VOH
VOL
IIL
Unit
Note/
Test Condition
Min.
Max.
3.0
3.6
V
1)
3.0
3.6
V
1)
2.0
VDDQ + 0.3
V
1)2)
–0.3
+0.8
V
1)2)
2.4
—
V
1)
—
0.4
V
1)
–5
+5
µA
—
Output leakage current
IOL
–5
+5
µA
—
(DQs are disabled, 0 V < VOUT < VDDQ)
1) All voltages are referenced to VSS
2) VIH may overshoot to VDDQ + 2.0 V for pulse width of < 4ns with 3.3 V. VIL may undershoot to -2.0 V for pulse width < 4.0 ns with 3.3 V.
Pulse width measured at 50 % points with amplitude measured peak to DC reference.
Rev. 1.1, 2007-02
09072006-N4GC-EREN
11
Internet Data Sheet
HY[B/I]39SC128[800/160]FE
128-MBit Synchronous DRAM
TABLE 9
Input and Output Capacitances
Parameter
Symbol
Values
Min.
Max.
Unit
Note
Input Capacitances: CK, CK
CI1
2.5
3.5
pF
1)2)
Input Capacitance
(A0-A11, BA0, BA1, RAS, CAS, WE, CS, CKE, DQM)
CI2
2.5
3.8
pF
1)2)
CI0
4.0
6.0
pF
1)2)
Input/Output Capacitance (DQ)
1) VDD,VDDQ = 3.3 V ± 0.3 V, f = 1 MHz, TA see Table 7
2) Capacitance values are shown for TSOP-54 packages. Capacitance values for TFBGA packages are lower by 0.5 pF
TABLE 10
IDD Conditions
Parameter
Symbol
Operating Current
One bank active, Burst length = 1
Precharge Standby Current
Power down mode
Non-power down mode
No Operating Current
Active state (max. 4 banks)
Burst Operating Current
Read command cycling
Auto Refresh Current
Auto Refresh command cycling
Self Refresh Current
Self Refresh Mode, CKE=0.2 V, tCK=infinity
Rev. 1.1, 2007-02
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12
IDD1
IDD2P
IDD2N
IDD3N
IDD3P
IDD4
IDD5
IDD6
Internet Data Sheet
HY[B/I]39SC128[800/160]FE
128-MBit Synchronous DRAM
TABLE 11
IDD Specifications and Conditions
Symbol
Test Condition
–6
–7
Unit
Note 1)
IDD1
IDD2P
IDD2N
IDD3N
IDD3P
IDD4
IDD5
tRC = tRC(min), IO = 0 mA
CS =VIH (min.), CKE ≤VIL(max)
CS =VIH (min.), CKE≥ VIH(min)
CS = VIH(min), CKE ≥VIH(min.)
CS = VIH(min), CKE ≤ VIL(max.)
100
80
mA
2)3)
2
2
mA
1)
26
22
mA
1)
40
35
mA
1)
5
5
mA
1)
—
65
57
mA
1)3)
tRFC= tRFC(min)
tRFC= 15.6 µs
168
142
mA
4)
25
25
mA
—
3
3
mA
Standard components
0.8
0.8
mA
Low power components , at 85 °C
IDD6
1) VSS = 0 V; VDD, VDDQ = 3.3 V ± 0.3 V, TA see Table 7
2) These parameters depend on the cycle rate. All values are measured at 133 MHz for -7 with the outputs open. Input signals are changed
once during tCK.
3) These parameters are measured with continuous data stream during read access and all DQ toggling. CL=3 and BL=4 is assumed and
the VDDQ current is excluded.
4) tRFC= tRFC(min) “burst refresh”, tRFC= 15.6 µs “distributed refresh”.
4.2
AC Characteristics
TABLE 12
AC Timing - Absolute Specifications
Parameter
Symbol
–7
–6
PC133–222
PC166–333
Unit
Note1)2)
3)
Min.
Max.
Min.
Max.
Clock and Clock Enable
Clock Frequency
tCK
—
—
–7
–7.5
—
—
–6
–7.5
ns
ns
CL3
CL2
Access Time from Clock
tAC
—
—
5.4
5.4
—
—
5.4
5.4
ns
ns
CL3
CL2
3)4)5)
Clock High Pulse Width
Clock Low Pulse Width
Transition time
tCH
tCL
tT
2.5
—
2
—
ns
2.5
—
2
—
ns
0.3
1.2
0.3
1.2
ns
tIS
tIH
tCK
1.5
—
1.5
—
ns
6)
0.8
—
0.8
—
ns
6)
1.5
—
1.5
—
ns
6)
Setup and Hold Times
Input Setup Time
Input Hold Time
CKE Setup Time
Rev. 1.1, 2007-02
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Internet Data Sheet
HY[B/I]39SC128[800/160]FE
128-MBit Synchronous DRAM
Parameter
Symbol
–7
–6
PC133–222
PC166–333
Unit
Note1)2)
3)
Min.
Max.
Min.
Max.
tCKH
tRSC
tSB
0.8
—
0.8
—
2
—
2
—
tCK
0
7
0
6
ns
tRCD
tRP
tRAS
tRC
tRFC
tRRD
tCCD
15
—
15
—
ns
7)
15
—
15
—
ns
7)
37
100k
36
100k
ns
7)
60
—
60
—
ns
7)
63
—
60
—
ns
14
—
12
—
ns
1
—
1
—
tCK
tREF
tSREX
tOH
–
64
–
64
ms
1
—
1
—
tCK
3
—
2.5
—
ns
tLZ
tHZ
tDQZ
0
—
0
—
ns
3
7
3
6
ns
—
2
—
2
tCK
Last Data Input to Precharge
(Write without Auto Precharge)
tWR
14
—
12
—
ns
8)
Last Data Input to Activate
(Write with Auto Precharge)
tDAL(min.)
—
—
—
—
tCK
9)
0
—
0
—
tCK
CKE Hold Time
Mode Register Set-up to Active delay
Power Down Mode Entry Time
ns
6)
Common Parameters
Row to Column Delay Time
Row Precharge Time
Row Active Time
Row Cycle Time
Row Cycle Time during Auto Refresh
Activate(a) to Activate(b) Command period
CAS(a) to CAS(b) Command period
7)
Refresh Cycle
Refresh Period (4096 cycles)
Self Refresh Exit Time
Data Out Hold Time
3)5)
Read Cycle
Data Out to Low Impedance Time
Data Out to High Impedance Time
DQM Data Out Disable Latency
Write Cycle
DQM Write Mask Latency
tDQW
1) TA = 0 to 70 °C; VSS = 0 V; VDD, VDDQ = 3.3 V ± 0.3 V, tT = 1 ns
2) For proper power-up see the operation section of this data sheet.
3) AC timing tests for LV-TTL versions have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.4 V crossover point. The transition
time is measured between VIH and VIL. All AC measurements assume tT = 1 ns with the AC output load circuit shown in figure below.
Specified tAC and tOH parameters are measured with a 50 pF only, without any resistive termination and with an input signal of 1V / ns edge
rate between 0.8 V and 2.0 V.
4) If clock rising time is longer than 1 ns, a time (tT/2 - 0.5) ns has to be added to this parameter.
5) Access time from clock tac is 4.6 ns for PC133 components with no termination and 0 pF load,
Data out hold time toh is 1.8 ns for PC133 components with no termination and 0 pF load.
6) If tT is longer than 1 ns, a time (tT - 1) ns has to be added to this parameter.
7) These parameter account for the number of clock cycles and depend on the operating frequency of the clock, as follows:
the number of clock cycles = specified value of timing period (counted in fractions as a whole number)
8) It is recommended to use two clock cycles between the last data-in and the precharge command in case of a write command without AutoPrecharge. One clock cycle between the last data-in and the precharge command is also supported, but restricted to cycle times tCK greater
or equal the specified tWR value, where tck is equal to the actual system clock time.
9) When a Write command with Auto Precharge has been issued, a time of tDAL(min) has be fullfilled before the next Activate Command can
be applied. For each of the terms, if not already an integer, round up to the next highest integer. tCK is equal to the actual system clock time.
Rev. 1.1, 2007-02
09072006-N4GC-EREN
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Internet Data Sheet
HY[B/I]39SC128[800/160]FE
128-MBit Synchronous DRAM
FIGURE 2
Measurement conditions for tAC and tOH
t CH
2 .4 V
0 .4 V
1 .4 V
CLO C K
tCL
t IS
tT
t IH
1 .4 V
IN P U T
tA C
t LZ
tAC
tOH
OUTPUT
1.4 V
I/O
t HZ
50 pF
Measurement conditions for
tAC and tOH
IO.vsd
Rev. 1.1, 2007-02
09072006-N4GC-EREN
15
Internet Data Sheet
HY[B/I]39SC128[800/160]FE
128-MBit Synchronous DRAM
5
Package Outlines
FIGURE 3
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Package Outline PG-TSOPII-54 (top view)
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Rev. 1.1, 2007-02
09072006-N4GC-EREN
16
*3; Internet Data Sheet
HY[B/I]39SC128[800/160]FE
128-MBit Synchronous DRAM
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering Information for RoHS Compliant Products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Configuration of the SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Truth Table: Operation Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Mode Register Definition (BA[1:0] = 00B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Burst Length and Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Input and Output Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
IDD Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
IDD Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
AC Timing - Absolute Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Rev. 1.1, 2007-02
09072006-N4GC-EREN
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Internet Data Sheet
HY[B/I]39SC128[800/160]FE
128-MBit Synchronous DRAM
List of Figures
Figure 1
Figure 2
Figure 3
Pin Configuration PG–TSOPII–54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Measurement conditions for tAC and tOH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Package Outline PG-TSOPII-54 (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Rev. 1.1, 2007-02
09072006-N4GC-EREN
18
Internet Data Sheet
HY[B/I]39SC128[800/160]FE
128-MBit Synchronous DRAM
Table of Contents
1
1.1
1.2
2.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
3
3
5
3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4
4.1
4.2
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Rev. 1.1, 2007-02
09072006-N4GC-EREN
19
Internet Data Sheet
Edition 2007-02
Published by Qimonda AG
Gustav-Heinemann-Ring 212
D-81739 München, Germany
© Qimonda AG 2007.
All Rights Reserved.
Legal Disclaimer
The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics
(“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind,
including without limitation warranties of non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office.
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in question please
contact your nearest Qimonda Office.
Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a
failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect
the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human
body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health
of the user or other persons may be endangered.
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