Qimonda HYS64T256022EDL-3.7-B 200-pin dual die small-outline-ddr2-sdram module Datasheet

November 2006
HYS64T256022EDL–[25F/2.5]–B
HYS64T256022EDL–[3/3S]–B
HYS64T256022EDL–3.7–B
200-Pin Dual Die Small-Outline-DDR2-SDRAM Modules
DDR2 SDRAM
SO-DIMM SDRAM
RoHS Compliant
Internet Data Sheet
Rev. 1.0
Internet Data Sheet
HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B
Small Outline DDR2 SDRAM Modules
HYS64T256022EDL–[25F/2.5]–B; HYS64T256022EDL–[3/3S]–B; HYS64T256022EDL–3.7–B
Revision History: 2006-11, Rev. 1.0
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Internet Data Sheet
HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B
Small Outline DDR2 SDRAM Modules
1
Overview
This chapter gives an overview of the 200-Pin Dual Die Small-Outline-DDR2-SDRAM Modules product family and describes
its main characteristics.
1.1
Features
• 200-Pin PC2-6400, PC2–5300 and PC2-4200 DDR2
SDRAM memory modules.
• 256M × 64 module organization, and 2 × 128M × 8 chip
organization
• Standard Double-Data-Rate-Two Synchronous DRAMs
(DDR2 SDRAM) with a single + 1.8 V (± 0.1 V) power
supply
• 2GB Modules built with stacked 1Gb DDR2 SDRAMs in
PG-TFBGA-71 chipsize packages
• All speed grades faster than DDR2-400 comply with
DDR2-400 timing specifications.
• Programmable CAS Latencies (3, 4, 5 and 6), Burst
Length (8 & 4) and Burst Type
• Burst Refresh, Distributed Refresh and Self Refresh
• Programmable self refresh rate via EMRS2 setting
• Programmable partial array refresh via EMRS2 settings
• Average Refresh Period 7.8 µs at a TCASE lower than 85°C,
3.9µs between 85°C and 95°C.
• DCC enabling via EMRS2 setting
• All inputs and outputs SSTL_18 compatible
• Off-Chip Driver Impedance Adjustment (OCD) and On-Die
Termination (ODT)
• Serial Presence Detect with E2PROM
• SO-DIMM Dimensions (nominal):
30 mm high, 67.6 mm wide
• Based on Standard reference layouts Raw Card “D”
• RoHS Compliant Products1)
TABLE 1
Performance Table
Product Type Speed Code
–25F
–2.5
–3
–3S
–3.7
Unit
Speed Grade
PC2–6400
5–5–5
PC2–6400
6–6–6
PC2–5300
4–4–4
PC2–5300
5–5–5
PC2–4200
4–4–4
—
400
400
–
–
–
MHz
400
333
333
333
266
MHz
266
266
333
266
266
MHz
200
200
200
200
200
MHz
12.5
15
12
15
15
ns
12.5
15
12
15
15
ns
45
45
45
45
45
ns
57.5
60
57
60
60
ns
Max. Clock Frequency
@CL6
@CL5
@CL4
@CL3
Min. RAS-CAS-Delay
Min. Row Precharge Time
Min. Row Active Time
Min. Row Cycle Time
fCK6
fCK5
fCK4
fCK3
tRCD
tRP
tRAS
tRC
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 1.0, 2006-11
11172006-DXYK-2PPW
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Internet Data Sheet
HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B
Small Outline DDR2 SDRAM Modules
1.2
Description
The Qimonda HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B
module family are Small Outline modules “SO-DIMMs” with
30 mm height based on DDR2 technology. DIMMs are
available as non-ECC modules in 256M × 64 (2 GB)
organization and density, intended for mounting into 200-pin
connector sockets.
The memory array is designed with stacked 1 Gbit DoubleData-Rate-Two (DDR2) Synchronous DRAMs. Decoupling
capacitors are mounted on the PCB. The DIMMs feature
serial presence detect based on a serial E2PROM device
using the 2-pin I2C protocol. The first 128 bytes are
programmed with configuration data and are write protected;
the second 128 bytes are available to the customer.
TABLE 2
Ordering Information for RoHS Compliant Products
Product Type
1)
Compliance Code
2)
Description
SDRAM Technology
2GB 2R×8 PC2–6400S–555–12–D0
2 Ranks, Non-ECC
1 Gbit (×8)
2GB 2R×8 PC2–6400S–666–12–D0
2 Ranks, Non-ECC
1 Gbit (×8)
2GB 2R×8 PC2–5300S–444–12–D0
2 Ranks, Non-ECC
1 Gbit (×8)
2GB 2R×8 PC2–5300S–555–12–D0
2 Ranks, Non-ECC
1 Gbit (×8)
2GB 2R×8 PC2–4200S–444–12–D0
2 Ranks, Non-ECC
1 Gbit (×8)
PC2–6400
HYS64T256022EDL–25F–B
PC2–6400
HYS64T256022EDL–2.5–B
PC2–5300
HYS64T256022EDL–3–B
PC2–5300
HYS64T256022EDL–3S–B
PC2–4200
HYS64T256022EDL–3.7–B
1) All Product Type numbers end with a place code, designating the silicon die revision. Example: HYS64T256022EDL–3.7–B, indicating
Rev. “B” dies are used for DDR2 SDRAM components. For all Qimonda DDR2 module and component nomenclature see Chapter 6 of
this data sheet.
2) The Compliance Code is printed on the module label and describes the speed grade, for example “PC2–4200S–444–12–D0”, where
4200S means SO-DIMM modules with 4.26 GB/sec Module Bandwidth and “444–12” means Column Address Strobe (CAS) latency = 4,
Row Column Delay (RCD) latency = 4 and Row Precharge (RP) latency = 4 using the latest JEDEC SPD Revision 1.2 and produced on
the Raw Card “D”.
TABLE 3
Address Format
DIMM Density
Module
Organization
Memory
Ranks
ECC/
Non-ECC
# of
SDRAMs
# of row/bank/columns bits
Raw Card
2 GByte
256M ×64
2
Non-ECC
16
14/3/10
D
TABLE 4
Components on Modules
Product Type
1)
HYS64T256022EDL
1)
DRAM Components
HYB18T2G802BF
DRAM Density
2 ×1 Gbit
DRAM Organisation
Note
2× 128M ×8
2)
1) Green Product
2) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet.
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Internet Data Sheet
HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B
Small Outline DDR2 SDRAM Modules
2
Pin Configuration
The pin configuration of the Small Outline DDR2 SDRAM DIMM is listed by function in Table 5 (200 pins). The abbreviations
used in columns Pin and Buffer Type are explained in Table 6 and Table 7 respectively. The pin numbering is depicted in
Figure 1
TABLE 5
Pin Configuration of SO-DIMM
Ball No.
Name
Pin
Type
Buffer
Type
Function
30
CK0
I
SSTL
Clock Signals 2:0, Complement Clock Signals 2:0
164
CK1
I
SSTL
32
CK0
I
SSTL
166
CK1
I
SSTL
79
CKE0
I
SSTL
80
CKE1
I
SSTL
NC
NC
—
Not Connected
Note: 1-rank module
110
S0
I
SSTL
Chip Select Rank 1:0
115
S1
I
SSTL
NC
NC
—
Not Connected
Note: 1-rank module
108
RAS
I
SSTL
Row Address Strobe
113
CAS
I
SSTL
Column Address Strobe
109
WE
I
SSTL
Write Enable
107
BA0
I
SSTL
Bank Address Bus 2:0
106
BA1
I
SSTL
85
BA2
I
SSTL
Bank Address Bus 2
Greater than 512Mb DDR2 SDRAMS
NC
NC
SSTL
Less than 1Gb DDR2 SDRAMS
Clock Signals
Clock Enable Rank 1:0
Note: 2 Ranks module
Control Signals
Address Signals
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Internet Data Sheet
HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B
Small Outline DDR2 SDRAM Modules
Ball No.
Name
Pin
Type
Buffer
Type
Function
102
A0
I
SSTL
Address Bus 12:0
101
A1
I
SSTL
100
A2
I
SSTL
99
A3
I
SSTL
98
A4
I
SSTL
97
A5
I
SSTL
94
A6
I
SSTL
92
A7
I
SSTL
93
A8
I
SSTL
91
A9
I
SSTL
105
A10
I
SSTL
AP
I
SSTL
90
A11
I
SSTL
89
A12
I
SSTL
Address Signal 12
Note: Module based on 256 Mbit or larger dies
116
A13
I
SSTL
Address Signal 13
Note: 1 Gbit based module
NC
NC
—
Not Connected
Note: Module based on 512 Mbit or smaller dies
5
DQ0
I/O
SSTL
7
DQ1
I/O
SSTL
Data Bus 63:0
Note: Data Input/Output pins
17
DQ2
I/O
SSTL
19
DQ3
I/O
SSTL
4
DQ4
I/O
SSTL
6
DQ5
I/O
SSTL
14
DQ6
I/O
SSTL
16
DQ7
I/O
SSTL
23
DQ8
I/O
SSTL
25
DQ9
I/O
SSTL
35
DQ10
I/O
SSTL
37
DQ11
I/O
SSTL
Data Signals
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Internet Data Sheet
HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B
Small Outline DDR2 SDRAM Modules
Ball No.
Name
Pin
Type
Buffer
Type
Function
20
DQ12
I/O
SSTL
22
DQ13
I/O
SSTL
Data Bus 63:0
Data Input/Output pins
36
DQ14
I/O
SSTL
38
DQ15
I/O
SSTL
43
DQ16
I/O
SSTL
45
DQ17
I/O
SSTL
55
DQ18
I/O
SSTL
57
DQ19
I/O
SSTL
44
DQ20
I/O
SSTL
46
DQ21
I/O
SSTL
56
DQ22
I/O
SSTL
58
DQ23
I/O
SSTL
61
DQ24
I/O
SSTL
63
DQ25
I/O
SSTL
73
DQ26
I/O
SSTL
75
DQ27
I/O
SSTL
62
DQ28
I/O
SSTL
64
DQ29
I/O
SSTL
74
DQ30
I/O
SSTL
76
DQ31
I/O
SSTL
123
DQ32
I/O
SSTL
125
DQ33
I/O
SSTL
135
DQ34
I/O
SSTL
137
DQ35
I/O
SSTL
124
DQ36
I/O
SSTL
126
DQ37
I/O
SSTL
134
DQ38
I/O
SSTL
136
DQ39
I/O
SSTL
141
DQ40
I/O
SSTL
143
DQ41
I/O
SSTL
151
DQ42
I/O
SSTL
153
DQ43
I/O
SSTL
140
DQ44
I/O
SSTL
142
DQ45
I/O
SSTL
152
DQ46
I/O
SSTL
154
DQ47
I/O
SSTL
157
DQ48
I/O
SSTL
159
DQ49
I/O
SSTL
173
DQ50
I/O
SSTL
175
DQ51
I/O
SSTL
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Internet Data Sheet
HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B
Small Outline DDR2 SDRAM Modules
Ball No.
Name
Pin
Type
Buffer
Type
Function
158
DQ52
I/O
SSTL
Data Bus 63:0
160
DQ53
I/O
SSTL
174
DQ54
I/O
SSTL
176
DQ55
I/O
SSTL
179
DQ56
I/O
SSTL
181
DQ57
I/O
SSTL
189
DQ58
I/O
SSTL
191
DQ59
I/O
SSTL
180
DQ60
I/O
SSTL
182
DQ61
I/O
SSTL
192
DQ62
I/O
SSTL
194
DQ63
I/O
SSTL
13
DQS0
I/O
SSTL
11
DQS0
I/O
SSTL
31
DQS1
I/O
SSTL
29
DQS1
I/O
SSTL
51
DQS2
I/O
SSTL
49
DQS2
I/O
SSTL
70
DQS3
I/O
SSTL
68
DQS3
I/O
SSTL
131
DQS4
I/O
SSTL
129
DQS4
I/O
SSTL
148
DQS5
I/O
SSTL
146
DQS5
I/O
SSTL
169
DQS6
I/O
SSTL
167
DQS6
I/O
SSTL
188
DQS7
I/O
SSTL
186
DQS7
I/O
SSTL
10
DM0
I
SSTL
26
DM1
I
SSTL
52
DM2
I
SSTL
67
DM3
I
SSTL
130
DM4
I
SSTL
147
DM5
I
SSTL
170
DM6
I
SSTL
185
DM7
I
SSTL
Data Strobe Signals
Data Strobe Bus 7:0
Data Mask Signals
Rev. 1.0, 2006-11
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Data Mask Bus 7:0
8
Internet Data Sheet
HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B
Small Outline DDR2 SDRAM Modules
Ball No.
Name
Pin
Type
Buffer
Type
Function
197
SCL
I
CMOS
Serial Bus Clock
195
SDA
I/O
OD
Serial Bus Data
198
SA0
I
CMOS
Serial Address Select Bus 2:0
200
SA1
I
CMOS
VREF
VDDSPD
VDD
AI
—
I/O Reference Voltage
PWR
—
EEPROM Power Supply
PWR
—
Power Supply
GND
—
Ground Plane
EEPROM
Power Supplies
1
199
81,82,87,88,95,96,103,104,
111,112,117,118
2,3,8,9,12,15,18,21,24,27,28,
VSS
33,34,39,40,41,42,47,48,53,
54,59,60,65,66,71,72,77,78,
121,122,127,128,132,133,138,13
9,144,145,149,150,155,156,,
161,162,165,171,172,177,
178,183,184,187,190,193,196
Other Pins
114
ODT0
I
SSTL
On-Die Termination Control 1:0
119
ODT1
I
SSTL
On-Die Termination Control 1
Note: 2 Rank modules
NC
NC
—
Not Connected
Note: 1 Rank modules
NC
NC
—
Not connected
50,69,83,84,120,163,168
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Internet Data Sheet
HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B
Small Outline DDR2 SDRAM Modules
TABLE 6
Abbreviations for Pin Type
Abbreviation
Description
I
Standard input-only pin. Digital levels.
O
Output. Digital levels.
I/O
I/O is a bidirectional input/output signal.
AI
Input. Analog levels.
PWR
Power
GND
Ground
NC
Not Connected
TABLE 7
Abbreviations for Buffer Type
Abbreviation
Description
SSTL
Serial Stub Terminated Logic (SSTL_18)
LV-CMOS
Low Voltage CMOS
CMOS
CMOS Levels
OD
Open Drain. The corresponding pin has 2 operational states, active low and tristate, and
allows multiple devices to share as a wire-OR.
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Internet Data Sheet
HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B
Small Outline DDR2 SDRAM Modules
FIGURE 1
Pin Configuration SO-DIMM (200 Pin)
95() 3LQ
'4 3LQ
966 3LQ
'46 3LQ
'4 3LQ
966 3LQ
'4 3LQ
'46 3LQ
966 3LQ
'4 3LQ
966 3LQ
'4 3LQ
'46 3LQ
966 3LQ
'4 3LQ
'4 3LQ
966 3LQ
1& 3LQ
'4 3LQ
966 3LQ
9'' 3LQ
1&%$ 3LQ
$ 3LQ
$ 3LQ
$ 3LQ
$ 3LQ
$$3 3LQ
:( 3LQ
&$6 3LQ
9'' 3LQ
966 3LQ
'4 3LQ
'46 3LQ
966 3LQ
'4
3LQ
'4 3LQ
966 3LQ
966 3LQ
'4 3LQ
'4 3LQ
966 3LQ
966 3LQ
'46 3LQ
'4 3LQ
966 3LQ
'4 3LQ
'0 3LQ
'4 3LQ
966 3LQ
6&/ 3LQ
966 3LQ
3LQ
'4
3LQ
966
3LQ
966
3LQ
'4
3LQ
'4
3LQ
966
3LQ
966
3LQ
&.
3LQ
'4
3LQ
966
'4 3LQ
'46 3LQ
966 3LQ
'4 3LQ
'4 3LQ
966 3LQ
'46 3LQ
'4 3LQ
966 3LQ
'4 3LQ
966 3LQ
'46 3LQ
'4 3LQ
966 3LQ
'4 3LQ
'0 3LQ
966 3LQ
'4 3LQ
&.( 3LQ
1& 3LQ
9'' 3LQ
$ 3LQ
9'' 3LQ
$ 3LQ
9'' 3LQ
%$ 3LQ
9'' 3LQ
1&6 3LQ
1&2'7 3LQ
'4 3LQ
966 3LQ
'46 3LQ
'4 3LQ
966 3LQ
'4 3LQ
'0 3LQ
'4 3LQ
966 3LQ
'4 3LQ
1& 3LQ
'46 3LQ
966 3LQ
'4 3LQ
'4 3LQ
966 3LQ
966 3LQ
'4 3LQ
6'$ 3LQ
9''63' 3LQ
)
5
2
1
7
6
,
'
(
%
$
&
.
6
,
'
(
3LQ
'4
3LQ
966
3LQ
'0
3LQ
'4
3LQ
966
3LQ
'4
3LQ
'46
3LQ
966
3LQ
'4
3LQ
1&&.(
3LQ
1&
3LQ
9''
3LQ
$
3LQ
9''
3LQ
$
3LQ
9''
3LQ
5$6
3LQ
9''
3LQ
1&$
3LQ
1&
3LQ
'4
3LQ
966
3LQ
966
3LQ
'4
3LQ
'4
3LQ
966
3LQ
'46
3LQ
'4
3LQ
966
3LQ
'4
3LQ
&.
3LQ
966
3LQ
966
3LQ
'4
3LQ
'4
3LQ
966
3LQ
'46
3LQ
'4
3LQ
966
3LQ
6$
3LQ 966
3LQ '4
3LQ '0
3LQ '4
3LQ 966
3LQ '4
3LQ '0
3LQ &.
3LQ 966
3LQ '4
3LQ 966
3LQ '4
3LQ 1&(9(17
3LQ 966
3LQ '4
3LQ '4
3LQ 966
3LQ '46
3LQ '4
3LQ 966
3LQ 9''
3LQ 1&$
3LQ $
3LQ $
3LQ $
3LQ $
3LQ %$
3LQ 6
3LQ 2'7
3LQ 9''
3LQ 966
3LQ '4
3LQ '0
3LQ '4
3LQ 966
3LQ '4
3LQ '46
3LQ 966
3LQ '4
3LQ '4
3LQ 966
3LQ &.
3LQ '0
3LQ '4
3LQ 966
3LQ '4
3LQ '46
3LQ 966
3LQ '4
3LQ 6$
033
7
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Internet Data Sheet
HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B
Small Outline DDR2 SDRAM Modules
3
Electrical Characteristics
3.1
Absolute Maximum Ratings
Caution is needed not to exceed absolute maximum ratings of the DRAM device listed in Table 8 at any time.
TABLE 8
Absolute Maximum Ratings
Symbol
VDD
VDDQ
VDDL
VIN, VOUT
TSTG
Parameter
Rating
Unit
Note
Min.
Max.
Voltage on VDD pin relative to VSS
–1.0
+2.3
V
1)
Voltage on VDDQ pin relative to VSS
–0.5
+2.3
V
1)2)
Voltage on VDDL pin relative to VSS
–0.5
+2.3
V
1)2)
Voltage on any pin relative to VSS
–0.5
+2.3
V
1)
°C
1)2)
Storage Temperature
–55
+100
1) When VDD and VDDQ and VDDL are less than 500 mV; VREF may be equal to or less than 300 mV.
2) Storage Temperature is the case surface temperature on the center/top side of the DRAM.
Attention: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
TABLE 9
DRAM Component Operating Temperature Range
Symbol
TOPER
Parameter
Rating
Operating Temperature
Min.
Max.
0
95
Unit
Note
°C
1)2)3)4)
1) Operating Temperature is the case surface temperature on the center / top side of the DRAM.
2) The operating temperature range are the temperatures where all DRAM specification will be supported. During operation, the DRAM case
temperature must be maintained between 0 - 95 °C under all other specification parameters.
3) Above 85 °C the Auto-Refresh command interval has to be reduced to tREFI= 3.9 µs
4) When operating this product in the 85 °C to 95 °C TCASE temperature range, the High Temperature Self Refresh has to be enabled by
setting EMR(2) bit A7 to “1”. When the High Temperature Self Refresh is enabled there is an increase of IDD6 by approximately 50%
Rev. 1.0, 2006-11
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Internet Data Sheet
HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B
Small Outline DDR2 SDRAM Modules
3.2
DC Operating Conditions
TABLE 10
Operating Conditions
Parameter
Symbol
Values
Unit
Min.
Max.
0
+65
°C
0
+95
°C
Storage Temperature
TOPR
TCASE
TSTG
– 50
+100
°C
Barometric Pressure (operating & storage)
PBar
+69
+105
kPa
Operating Humidity (relative)
HOPR
10
90
%
Operating temperature (ambient)
DRAM Case Temperature
Note
1)2)3)4)
5)
1)
2)
3)
4)
DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the DRAMs.
Within the DRAM Component Case Temperature Range all DRAM specifications will be supported
Above 85 °C DRAM Case Temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 µs
When operating this product in the 85 °C to 95 °C TCASE temperature range, the High Temperature Self Refresh has to be enabled by
setting EMR(2) bit A7 to “1”. When the High Temperature Self Refresh is enabled there is an increase of IDD6 by approximately 50%.
5) Up to 3000 m.
TABLE 11
Supply Voltage Levels and DC Operating Conditions
Parameter
Device Supply Voltage
Output Supply Voltage
Input Reference Voltage
SPD Supply Voltage
DC Input Logic High
DC Input Logic Low
Symbol
VDD
VDDQ
VREF
VDDSPD
VIH(DC)
VIL (DC)
IL
Values
Unit
Min.
Typ.
Max.
1.7
1.8
1.9
V
1.7
1.8
1.9
V
1)
0.49 × VDDQ
0.5 × VDDQ
0.51 × VDDQ
V
2)
1.7
—
3.6
V
VREF + 0.125
—
V
– 0.30
—
VDDQ + 0.3
VREF – 0.125
V
In / Output Leakage Current
–5
—
5
µA
1) Under all conditions, VDDQ must be less than or equal to VDD
2) Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC).VREF is also expected to track noise in VDDQ.
3) Input voltage for any connector pin under test of 0 V ≤ VIN ≤ VDDQ + 0.3 V; all other pins at 0 V. Current is per pin
Rev. 1.0, 2006-11
11172006-DXYK-2PPW
Note
13
3)
Internet Data Sheet
HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B
Small Outline DDR2 SDRAM Modules
3.3
Timing Characteristics
3.3.1
Speed Grade Definitions
All Speed grades faster than DDR2-400B comply with DDR2-400B timing specifications(tCK = 5ns with tRAS = 40ns).
Speed Grade Definition: Table 12 for DDR2–800, Table 13 for DDR2–667D and Table 14 for DDR2–533C
TABLE 12
Speed Grade Definition Speed Bins for DDR2–800
Speed Grade
DDR2–800D
DDR2–800E
QAG Sort Name
–2.5F
–2.5
CAS-RCD-RP latencies
5–5–5
6–6–6
Parameter
Clock Frequency
@ CL = 3
@ CL = 4
@ CL = 5
@ CL = 6
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
Unit
Note
tCK
Symbol
Min.
Max.
Min.
Max.
—
tCK
tCK
tCK
tCK
tRAS
tRC
tRCD
tRP
5
8
5
8
ns
1)2)3)4)
3.75
8
3.75
8
ns
1)2)3)4)
2.5
8
3
8
ns
1)2)3)4)
2.5
8
2.5
8
ns
1)2)3)4)
45
70000
45
70000
ns
1)2)3)4)5)
57.5
—
60
—
ns
1)2)3)4)
12.5
—
15
—
ns
1)2)3)4)
12.5
—
15
—
ns
1)2)3)4)
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0)
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode.
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
4) The output timing reference voltage level is VTT.
5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI.
Rev. 1.0, 2006-11
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Internet Data Sheet
HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B
Small Outline DDR2 SDRAM Modules
TABLE 13
Speed Grade Definition Speed Bins for DDR2–667
Speed Grade
DDR2–667C
DDR2–667D
QAG Sort Name
–3
–3S
CAS-RCD-RP latencies
4–4–4
5–5–5
Parameter
Clock Frequency
@ CL = 3
@ CL = 4
@ CL = 5
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
Unit
Note
tCK
Symbol
Min.
Max.
Min.
Max.
—
tCK
tCK
tCK
tRAS
tRC
tRCD
tRP
5
8
5
8
ns
1)2)3)4)
3
8
3.75
8
ns
1)2)3)4)
3
8
3
8
ns
1)2)3)4)
45
70000
45
70000
ns
1)2)3)4)5)
57
—
60
—
ns
1)2)3)4)
12
—
15
—
ns
1)2)3)4)
12
—
15
—
ns
1)2)3)4)
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0) .
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
4) The output timing reference voltage level is VTT.
5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI.
Rev. 1.0, 2006-11
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15
Internet Data Sheet
HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B
Small Outline DDR2 SDRAM Modules
TABLE 14
Speed Grade Definition Speed Bins for DDR2–533C
Speed Grade
DDR2–533C
QAG Sort Name
–3.7
CAS-RCD-RP latencies
4–4–4
Parameter
Clock Frequency
@ CL = 3
@ CL = 4
@ CL = 5
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
Unit
Note
tCK
Symbol
Min.
Max.
—
tCK
tCK
tCK
tRAS
tRC
tRCD
tRP
5
8
ns
1)2)3)4)
3.75
8
ns
1)2)3)4)
3.75
8
ns
1)2)3)4)
45
70000
ns
1)2)3)4)5)
60
—
ns
1)2)3)4)
15
—
ns
1)2)3)4)
15
—
ns
1)2)3)4)
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0)
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode.
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
4) The output timing reference voltage level is VTT.
5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI.
Rev. 1.0, 2006-11
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16
Internet Data Sheet
HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B
Small Outline DDR2 SDRAM Modules
3.3.2
Component AC Timing Parameters
Timing Parameters: Table 15 for DDR2–800, Table 16 for DDR2–667D and Table 17 for DDR2–533C
TABLE 15
DRAM Component Timing Parameter by Speed Grade - DDR2–800
Parameter
Symbol
DDR2–800
Unit
Note
1)2)3)4)5)6)7)8)
Min.
Max.
tAC
tCCD
tCH.AVG
tCK.AVG
tCKE
–400
+400
ps
2
—
nCK
0.48
0.52
tCK.AVG
10)11)
2500
8000
ps
10)11)
3
—
nCK
12)
tCL.AVG
Auto-Precharge write recovery + precharge time tDAL
Minimum time clocks remain ON after CKE
tDELAY
0.48
0.52
tCK.AVG
10)11)
WR + tnRP
—
nCK
13)14)
tIS + tCK .AVG +
tIH
—
ns
tDH.BASE
DQ and DM input pulse width for each input
tDIPW
DQS output access time from CK / CK
tDQSCK
DQS input high pulse width
tDQSH
DQS input low pulse width
tDQSL
DQS-DQ skew for DQS & associated DQ signals tDQSQ
DQS latching rising transition to associated clock tDQSS
125
—
ps
0.35
—
tCK.AVG
–350
+350
ps
0.35
—
0.35
—
tCK.AVG
tCK.AVG
—
200
ps
16)
– 0.25
+ 0.25
tCK.AVG
17)
tDS.BASE
DQS falling edge hold time from CK
tDSH
DQS falling edge to CK setup time
tDSS
Four Activate Window for 1KB page size products tFAW
Four Activate Window for 2KB page size products tFAW
CK half pulse width
tHP
50
—
ps
18)19)20)
17)
tHZ
Address and control input hold time
tIH.BASE
Control & address input pulse width for each input tIPW
Address and control input setup time
tIS.BASE
DQ low impedance time from CK/CK
tLZ.DQ
DQS/DQS low-impedance time from CK / CK
tLZ.DQS
MRS command to ODT update delay
tMOD
Mode register set command cycle time
tMRD
tOIT
OCD drive mode output delay
DQ/DQS output hold time from DQS
tQH
DQ output access time from CK / CK
CAS to CAS command delay
Average clock high pulse width
Average clock period
CKE minimum pulse width ( high and low pulse
width)
Average clock low pulse width
asynchronously drops LOW
DQ and DM input hold time
edges
DQ and DM input setup time
Data-out high-impedance time from CK / CK
Rev. 1.0, 2006-11
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17
9)
19)20)15)
9)
0.2
—
0.2
—
tCK.AVG
tCK.AVG
35
—
ns
31)
45
—
ns
31)
Min(tCH.ABS,
tCL.ABS)
__
ps
21)
—
tAC.MAX
ps
9)22)
250
—
ps
23)25)
17)
0.6
—
tCK.AVG
175
—
ps
24)25)
2 × tAC.MIN
tAC.MAX
ps
9)22)
tAC.MIN
tAC.MAX
ps
9)22)
0
12
ns
31)
2
—
nCK
0
12
ns
31)
tHP – tQHS
—
ps
26)
Internet Data Sheet
HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B
Small Outline DDR2 SDRAM Modules
Parameter
Symbol
DDR2–800
Unit
Note
1)2)3)4)5)6)7)8)
Min.
Max.
tQHS
tRPRE
tRPST
tRRD
—
300
ps
27)
0.9
1.1
28)29)
0.4
0.6
tCK.AVG
tCK.AVG
7.5
—
ns
31)
Active to active command period for 2KB page
size products
tRRD
10
—
ns
31)
Internal Read to Precharge command delay
tRTP
tWPRE
tWPST
tWR
tWTR
tXARD
tXARDS
7.5
—
ns
31)
0.35
—
0.4
0.6
tCK.AVG
tCK.AVG
15
—
ns
31)
7.5
—
ns
31)32)
2
—
nCK
8 – AL
—
nCK
Exit precharge power-down to any valid
command (other than NOP or Deselect)
tXP
2
—
nCK
Exit self-refresh to a non-read command
tRFC +10
—
ns
Exit self-refresh to read command
tXSNR
tXSRD
200
—
nCK
Write command to DQS associated clock edges
WL
RL – 1
DQ hold skew factor
Read preamble
Read postamble
Active to active command period for 1KB page
size products
Write preamble
Write postamble
Write recovery time
Internal write to read command delay
Exit power down to read command
Exit active power-down mode to read command
(slow exit, lower power)
28)30)
31)
nCK
1) For details and notes see the relevant Qimonda component data sheet
2) VDDQ = 1.8 V ± 0.1V; VDD = 1.8 V ± 0.1 V. See notes 5)6)7)8)
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode.
6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
7) The output timing reference voltage level is VTT.
8) New units, ‘tCK.AVG‘ and ‘nCK‘, are introduced in DDR2–667 and DDR2–800. Unit ‘tCK.AVG‘ represents the actual tCK.AVG of the input clock
under operation. Unit ‘nCK‘ represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2–400 and
DDR2–533, ‘tCK‘ is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command
may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x tCK.AVG + tERR.2PER(Min).
9) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(6-10per) of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tERR(6-10PER).MIN = – 272
ps and tERR(6- 10PER).MAX = + 293 ps, then tDQSCK.MIN(DERATED) = tDQSCK.MIN – tERR(6-10PER).MAX = – 400 ps – 293 ps = – 693 ps and
tDQSCK.MAX(DERATED) = tDQSCK.MAX – tERR(6-10PER).MIN = 400 ps + 272 ps = + 672 ps. Similarly, tLZ.DQ for DDR2–667 derates to tLZ.DQ.MIN(DERATED)
= - 900 ps – 293 ps = – 1193 ps and tLZ.DQ.MAX(DERATED) = 450 ps + 272 ps = + 722 ps. (Caution on the MIN/MAX usage!)
10) Input clock jitter spec parameter. These parameters are referred to as 'input clock jitter spec parameters' and these parameters apply to
DDR2–667 and DDR2–800 only. The jitter specified is a random jitter meeting a Gaussian distribution.
11) These parameters are specified per their average values, however it is understood that the relationship between the average timing and
the absolute instantaneous timing holds all the times (min. and max of SPEC values are to be used for calculations ).
12) tCKE.MIN of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the
entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during
the time period of tIS + 2 x tCK + tIH.
Rev. 1.0, 2006-11
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18
Internet Data Sheet
HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B
Small Outline DDR2 SDRAM Modules
13) DAL = WR + RU{tRP(ns) / tCK(ns)}, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For tRP, if the result
of the division is not already an integer, round up to the next highest integer. tCK refers to the application clock period. Example: For
DDR2–533 at tCK = 3.75 ns with tWR programmed to 4 clocks. tDAL = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks.
14) tDAL.nCK = WR [nCK] + tnRP.nCK = WR + RU{tRP [ps] / tCK.AVG[ps] }, where WR is the value programmed in the EMR.
15) Input waveform timing tDH with differential data strobe enabled MR[bit10] = 0, is referenced from the differential data strobe crosspoint to
the input signal crossing at the VIH.DC level for a falling signal and from the differential data strobe crosspoint to the input signal crossing
at the VIL.DC level for a rising signal applied to the device under test. DQS, DQS signals must be monotonic between VIL.DC.MAX and
VIH.DC.MIN. See Figure 3.
16) tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output
slew rate mismatch between DQS / DQS and associated DQ in any given cycle.
17) These parameters are measured from a data strobe signal ((L/U/R)DQS / DQS) crossing to its respective clock signal (CK / CK) crossing.
The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC, etc.), as these are relative to the clock signal
crossing. That is, these parameters should be met whether clock jitter is present or not.
18) Input waveform timing tDS with differential data strobe enabled MR[bit10] = 0, is referenced from the input signal crossing at the VIH.AC level
to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL.AC level to the differential data strobe
crosspoint for a falling signal applied to the device under test. DQS, DQS signals must be monotonic between Vil(DC)MAX and Vih(DC)MIN. See
Figure 3.
19) If tDS or tDH is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed.
20) These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal
((L/U/R)DQS / DQS) crossing.
21) tHP is the minimum of the absolute half period of the actual input clock. tHP is an input parameter but not an input specification parameter.
It is used in conjunction with tQHS to derive the DRAM output timing tQH. The value to be used for tQH calculation is determined by the
following equation; tHP = MIN (tCH.ABS, tCL.ABS), where, tCH.ABS is the minimum of the actual instantaneous clock high time; tCL.ABS is the
minimum of the actual instantaneous clock low time.
22) tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level
which specifies when the device output is no longer driving (tHZ), or begins driving (tLZ) .
23) Input waveform timing is referenced from the input signal crossing at the VIL.DC level for a rising signal and VIH.DC for a falling signal applied
to the device under test. See Figure 4.
24) Input waveform timing is referenced from the input signal crossing at the VIH.AC level for a rising signal and VIL.AC for a falling signal applied
to the device under test. See Figure 4.
25) These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to
its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC,
etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should
be met whether clock jitter is present or not.
26) tQH = tHP – tQHS, where: tHP is the minimum of the absolute half period of the actual input clock; and tQHS is the specification value under the
max column. {The less half-pulse width distortion present, the larger the tQH value is; and the larger the valid data eye will be.}
Examples: 1) If the system provides tHP of 1315 ps into a DDR2–667 SDRAM, the DRAM provides tQH of 975 ps minimum. 2) If the system
provides tHP of 1420 ps into a DDR2–667 SDRAM, the DRAM provides tQH of 1080 ps minimum.
27) tQHS accounts for: 1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual tHP at the input is
transferred to the output; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next
transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channel variation
of the output drivers.
28) tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving
(tRPST), or begins driving (tRPRE). Figure 2 shows a method to calculate these points when the device is no longer driving (tRPST), or begins
driving (tRPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the
calculation is consistent.
29) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.PER of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tJIT.PER.MIN = – 72 ps
and tJIT.PER.MAX = + 93 ps, then tRPRE.MIN(DERATED) = tRPRE.MIN + tJIT.PER.MIN = 0.9 x tCK.AVG – 72 ps = + 2178 ps and tRPRE.MAX(DERATED) = tRPRE.MAX
+ tJIT.PER.MAX = 1.1 x tCK.AVG + 93 ps = + 2843 ps. (Caution on the MIN/MAX usage!).
30) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.DUTY of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tJIT.DUTY.MIN = – 72 ps
and tJIT.DUTY.MAX = + 93 ps, then tRPST.MIN(DERATED) = tRPST.MIN + tJIT.DUTY.MIN = 0.4 x tCK.AVG – 72 ps = + 928 ps and tRPST.MAX(DERATED) = tRPST.MAX
+ tJIT.DUTY.MAX = 0.6 x tCK.AVG + 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!).
31) For these parameters, the DDR2 SDRAM device is characterized and verified to support tnPARAM = RU{tPARAM / tCK.AVG}, which is in clock
cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP / tCK.AVG}, which is in
clock cycles, if all input clock jitter specifications are met. This means: For DDR2–667 5–5–5, of which tRP = 15 ns, the device will support
tnRP = RU{tRP / tCK.AVG} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at
Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter.
Rev. 1.0, 2006-11
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19
Internet Data Sheet
HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B
Small Outline DDR2 SDRAM Modules
32) tWTR is at lease two clocks (2 x tCK) independent of operation frequency.
TABLE 16
DRAM Component Timing Parameter by Speed Grade - DDR2–667
Parameter
Symbol
DDR2–667
Unit
Note
1)2)3)4)5)6)7)8)
Min.
Max.
tAC
tCCD
tCH.AVG
tCK.AVG
tCKE
–450
+450
ps
2
—
nCK
0.48
0.52
tCK.AVG
3000
8000
ps
3
—
nCK
12)
tCL.AVG
Auto-Precharge write recovery + precharge time tDAL
Minimum time clocks remain ON after CKE
tDELAY
0.48
0.52
tCK.AVG
10)11)
WR + tnRP
—
nCK
13)14)
tIS + tCK .AVG +
tIH
—
ns
tDH.BASE
DQ and DM input pulse width for each input
tDIPW
DQS output access time from CK / CK
tDQSCK
DQS input high pulse width
tDQSH
DQS input low pulse width
tDQSL
DQS-DQ skew for DQS & associated DQ signals tDQSQ
DQS latching rising transition to associated clock tDQSS
175
—
ps
0.35
—
tCK.AVG
–400
+400
ps
0.35
—
0.35
—
tCK.AVG
tCK.AVG
—
240
ps
16)
– 0.25
+ 0.25
tCK.AVG
17)
tDS.BASE
DQS falling edge hold time from CK
tDSH
DQS falling edge to CK setup time
tDSS
Four Activate Window for 1KB page size products tFAW
Four Activate Window for 2KB page size products tFAW
CK half pulse width
tHP
100
––
ps
18)19)20)
0.2
—
17)
0.2
—
tCK.AVG
tCK.AVG
37.5
—
ns
31)
50
—
ns
31)
Min(tCH.ABS,
tCL.ABS)
—
ps
21)
tHZ
Address and control input hold time
tIH.BASE
Control & address input pulse width for each input tIPW
Address and control input setup time
tIS.BASE
DQ low impedance time from CK/CK
tLZ.DQ
DQS/DQS low-impedance time from CK / CK
tLZ.DQS
MRS command to ODT update delay
tMOD
Mode register set command cycle time
tMRD
OCD drive mode output delay
tOIT
DQ/DQS output hold time from DQS
tQH
DQ hold skew factor
tQHS
—
tAC.MAX
ps
9)22)
275
—
ps
25)23)
0.6
—
tCK.AVG
200
—
ps
24)25)
2 × tAC.MIN
ps
9)22)
tAC.MIN
tAC.MAX
tAC.MAX
ps
9)22)
0
12
ns
31)
2
—
nCK
0
12
ns
31)
tHP – tQHS
—
ps
26)
—
340
ps
27)
DQ output access time from CK / CK
CAS to CAS command delay
Average clock high pulse width
Average clock period
CKE minimum pulse width ( high and low pulse
width)
Average clock low pulse width
asynchronously drops LOW
DQ and DM input hold time
edges
DQ and DM input setup time
Data-out high-impedance time from CK / CK
Rev. 1.0, 2006-11
11172006-DXYK-2PPW
20
9)
10)11)
19)20)15)
9)
17)
Internet Data Sheet
HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B
Small Outline DDR2 SDRAM Modules
Parameter
Symbol
DDR2–667
Unit
Note
1)2)3)4)5)6)7)8)
Min.
Max.
tRPRE
tRPST
tRRD
0.9
1.1
0.4
Active to active command period for 2KB page
size products
Internal Read to Precharge command delay
28)29)
0.6
tCK.AVG
tCK.AVG
7.5
—
ns
31)
tRRD
10
—
ns
31)
tRTP
tWPRE
tWPST
tWR
tWTR
tXARD
tXARDS
7.5
—
ns
31)
0.35
—
Exit precharge power-down to any valid
command (other than NOP or Deselect)
Exit self-refresh to a non-read command
Read preamble
Read postamble
Active to active command period for 1KB page
size products
28)30)
0.4
0.6
tCK.AVG
tCK.AVG
15
—
ns
31)
7.5
—
ns
31)32)
2
—
nCK
7 – AL
—
nCK
tXP
2
—
nCK
tRFC +10
—
ns
Exit self-refresh to read command
tXSNR
tXSRD
200
—
Write command to DQS associated clock edges
WL
RL–1
Write preamble
Write postamble
Write recovery time
Internal write to read command delay
Exit power down to read command
Exit active power-down mode to read command
(slow exit, lower power)
31)
nCK
nCK
1) For details and notes see the relevant Qimonda component data sheet
2) VDDQ = 1.8 V ± 0.1V; VDD = 1.8 V ± 0.1 V. See notes 5)6)7)8)
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode.
6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
7) The output timing reference voltage level is VTT.
8) New units, ‘tCK.AVG‘ and ‘nCK‘, are introduced in DDR2–667 and DDR2–800. Unit ‘tCK.AVG‘ represents the actual tCK.AVG of the input clock
under operation. Unit ‘nCK‘ represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2–400 and
DDR2–533, ‘tCK‘ is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command
may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x tCK.AVG + tERR.2PER(Min).
9) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(6-10per) of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tERR(6-10PER).MIN = – 272
ps and tERR(6- 10PER).MAX = + 293 ps, then tDQSCK.MIN(DERATED) = tDQSCK.MIN – tERR(6-10PER).MAX = – 400 ps – 293 ps = – 693 ps and
tDQSCK.MAX(DERATED) = tDQSCK.MAX – tERR(6-10PER).MIN = 400 ps + 272 ps = + 672 ps. Similarly, tLZ.DQ for DDR2–667 derates to tLZ.DQ.MIN(DERATED)
= - 900 ps – 293 ps = – 1193 ps and tLZ.DQ.MAX(DERATED) = 450 ps + 272 ps = + 722 ps. (Caution on the MIN/MAX usage!)
10) Input clock jitter spec parameter. These parameters are referred to as 'input clock jitter spec parameters' and these parameters apply to
DDR2–667 and DDR2–800 only. The jitter specified is a random jitter meeting a Gaussian distribution.
11) These parameters are specified per their average values, however it is understood that the relationship between the average timing and
the absolute instantaneous timing holds all the times (min. and max of SPEC values are to be used for calculations ).
12) tCKE.MIN of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the
entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during
the time period of tIS + 2 x tCK + tIH.
13) DAL = WR + RU{tRP(ns) / tCK(ns)}, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For tRP, if the result
of the division is not already an integer, round up to the next highest integer. tCK refers to the application clock period. Example: For
DDR2–533 at tCK = 3.75 ns with tWR programmed to 4 clocks. tDAL = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks.
Rev. 1.0, 2006-11
11172006-DXYK-2PPW
21
Internet Data Sheet
HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B
Small Outline DDR2 SDRAM Modules
14) tDAL.nCK = WR [nCK] + tnRP.nCK = WR + RU{tRP [ps] / tCK.AVG[ps] }, where WR is the value programmed in the EMR.
15) Input waveform timing tDH with differential data strobe enabled MR[bit10] = 0, is referenced from the differential data strobe crosspoint to
the input signal crossing at the VIH.DC level for a falling signal and from the differential data strobe crosspoint to the input signal crossing
at the VIL.DC level for a rising signal applied to the device under test. DQS, DQS signals must be monotonic between VIL.DC.MAX and
VIH.DC.MIN. See Figure 3.
16) tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output
slew rate mismatch between DQS / DQS and associated DQ in any given cycle.
17) These parameters are measured from a data strobe signal ((L/U/R)DQS / DQS) crossing to its respective clock signal (CK / CK) crossing.
The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC, etc.), as these are relative to the clock signal
crossing. That is, these parameters should be met whether clock jitter is present or not.
18) Input waveform timing tDS with differential data strobe enabled MR[bit10] = 0, is referenced from the input signal crossing at the VIH.AC level
to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL.AC level to the differential data strobe
crosspoint for a falling signal applied to the device under test. DQS, DQS signals must be monotonic between Vil(DC)MAX and Vih(DC)MIN. See
Figure 3.
19) If tDS or tDH is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed.
20) These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal
((L/U/R)DQS / DQS) crossing.
21) tHP is the minimum of the absolute half period of the actual input clock. tHP is an input parameter but not an input specification parameter.
It is used in conjunction with tQHS to derive the DRAM output timing tQH. The value to be used for tQH calculation is determined by the
following equation; tHP = MIN (tCH.ABS, tCL.ABS), where, tCH.ABS is the minimum of the actual instantaneous clock high time; tCL.ABS is the
minimum of the actual instantaneous clock low time.
22) tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level
which specifies when the device output is no longer driving (tHZ), or begins driving (tLZ) .
23) Input waveform timing is referenced from the input signal crossing at the VIL.DC level for a rising signal and VIH.DC for a falling signal applied
to the device under test. See Figure 4.
24) Input waveform timing is referenced from the input signal crossing at the VIH.AC level for a rising signal and VIL.AC for a falling signal applied
to the device under test. See Figure 4.
25) These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to
its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC,
etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should
be met whether clock jitter is present or not.
26) tQH = tHP – tQHS, where: tHP is the minimum of the absolute half period of the actual input clock; and tQHS is the specification value under the
max column. {The less half-pulse width distortion present, the larger the tQH value is; and the larger the valid data eye will be.}
Examples: 1) If the system provides tHP of 1315 ps into a DDR2–667 SDRAM, the DRAM provides tQH of 975 ps minimum. 2) If the system
provides tHP of 1420 ps into a DDR2–667 SDRAM, the DRAM provides tQH of 1080 ps minimum.
27) tQHS accounts for: 1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual tHP at the input is
transferred to the output; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next
transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channel variation
of the output drivers.
28) tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving
(tRPST), or begins driving (tRPRE). Figure 2 shows a method to calculate these points when the device is no longer driving (tRPST), or begins
driving (tRPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the
calculation is consistent.
29) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.PER of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tJIT.PER.MIN = – 72 ps
and tJIT.PER.MAX = + 93 ps, then tRPRE.MIN(DERATED) = tRPRE.MIN + tJIT.PER.MIN = 0.9 x tCK.AVG – 72 ps = + 2178 ps and tRPRE.MAX(DERATED) = tRPRE.MAX
+ tJIT.PER.MAX = 1.1 x tCK.AVG + 93 ps = + 2843 ps. (Caution on the MIN/MAX usage!).
30) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.DUTY of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tJIT.DUTY.MIN = – 72 ps
and tJIT.DUTY.MAX = + 93 ps, then tRPST.MIN(DERATED) = tRPST.MIN + tJIT.DUTY.MIN = 0.4 x tCK.AVG – 72 ps = + 928 ps and tRPST.MAX(DERATED) = tRPST.MAX
+ tJIT.DUTY.MAX = 0.6 x tCK.AVG + 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!).
31) For these parameters, the DDR2 SDRAM device is characterized and verified to support tnPARAM = RU{tPARAM / tCK.AVG}, which is in clock
cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP / tCK.AVG}, which is in
clock cycles, if all input clock jitter specifications are met. This means: For DDR2–667 5–5–5, of which tRP = 15 ns, the device will support
tnRP = RU{tRP / tCK.AVG} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at
Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter.
32) tWTR is at lease two clocks (2 x tCK) independent of operation frequency.
Rev. 1.0, 2006-11
11172006-DXYK-2PPW
22
Internet Data Sheet
HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B
Small Outline DDR2 SDRAM Modules
FIGURE 2
Method for calculating transitions and endpoint
92+[P9
977[P9
92+[P9
977[P9
W/=
W+=
W535(EHJLQSRLQW
W5367
H QGSRLQW
92/[P9
977[P9
92/[P9
977[P9
7 7
7 7
W+=W5367
HQGSRLQW 77
W/=W535(
E HJLQSRLQW 7
7
FIGURE 3
Differential input waveform timing - tDS and tDS
'46
'46
W'6
W'+
W'6
W'+
9''4
9,+ DF PL
Q
9,+ GF PL
Q
95() GF 9,/ GF PD
[
[
9,/ DF PD
966
FIGURE 4
Differential input waveform timing - tlS and tlH
&.
&.
W,6
W,+
W,6
W,+
9''4
9,+DF PLQ
9,+GF PLQ
95() GF 9,/ GF PD[
9,/ DF PD[
966
Rev. 1.0, 2006-11
11172006-DXYK-2PPW
23
Internet Data Sheet
HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B
Small Outline DDR2 SDRAM Modules
TABLE 17
DRAM Component Timing Parameter by Speed Grade - DDR2–533
Parameter
Symbol
DDR2–533
Unit
Note
1)2)3)4)5)6)7)
Min.
Max.
tAC
tCCD
tCH
tCKE
tCL
tDAL
–500
+500
ps
2
—
0.45
0.55
3
—
0.45
0.55
WR + tRP
—
tCK
tCK
tCK
tCK
tCK
Minimum time clocks remain ON after CKE
asynchronously drops LOW
tDELAY
tIS + tCK + tIH
—
ns
9)
DQ and DM input hold time (differential data
strobe)
tDH(base)
225
—
ps
10)
–25
—
ps
11)
tDIPW
tDQSCK
tDQSL,H
tDQSQ
0.35
—
tCK
–450
+450
ps
0.35
—
tCK
—
300
ps
tDQSS
tDS(base)
– 0.25
+ 0.25
tCK
100
—
ps
11)
–25
—
ps
11)
tDSH
0.2
—
tCK
DQS falling edge to CK setup time (write cycle) tDSS
0.2
—
tCK
tFAW
tFAW
tHP
tHZ
tIH(base)
tIPW
37.5
—
ns
50
—
ns
tIS(base)
tLZ(DQ)
tLZ(DQS)
tMRD
tOIT
tQH
DQ output access time from CK / CK
CAS A to CAS B command period
CK, CK high-level width
CKE minimum high and low pulse width
CK, CK low-level width
Auto-Precharge write recovery + precharge
time
DQ and DM input hold time (single ended data tDH1(base)
strobe)
DQ and DM input pulse width (each input)
DQS output access time from CK / CK
DQS input low (high) pulse width (write cycle)
DQS-DQ skew (for DQS & associated DQ
signals)
Write command to 1st DQS latching transition
DQ and DM input setup time (differential data
strobe)
DQ and DM input setup time (single ended data tDS1(base)
strobe)
DQS falling edge hold time from CK (write
cycle)
Four Activate Window period
Four Activate Window period
Clock half period
Data-out high-impedance time from CK / CK
Address and control input hold time
Address and control input pulse width
(each input)
Address and control input setup time
DQ low-impedance time from CK / CK
DQS low-impedance from CK / CK
Mode register set command cycle time
OCD drive mode output delay
Data output hold time from DQS
Rev. 1.0, 2006-11
11172006-DXYK-2PPW
11)
13)
12)
MIN. (tCL, tCH)
24
8)18)
—
tAC.MAX
ps
13)
375
—
ps
11)
0.6
—
tCK
250
—
ps
11)
2 × tAC.MIN
ps
14)
tAC.MIN
tAC.MAX
tAC.MAX
ps
14)
2
—
tCK
0
12
ns
tHP –tQHS
—
Internet Data Sheet
HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B
Small Outline DDR2 SDRAM Modules
Parameter
Symbol
DDR2–533
Unit
Note
1)2)3)4)5)6)7)
Min.
Max.
tQHS
tREFI
tREFI
tRFC
—
400
ps
—
7.8
µs
14)15)
—
3.9
µs
16)18)
127.5
—
ns
17)
tRP
tRP
tRPRE
tRPST
tRRD
tRP + 1tCK
15 + 1tCK
—
ns
—
ns
0.9
1.1
14)
0.40
0.60
tCK
tCK
7.5
—
ns
14)18)
Active bank A to Active bank B command
period
tRRD
10
—
ns
16)22)
Internal Read to Precharge command delay
tRTP
tWPRE
tWPST
tWR
7.5
—
ns
0.25
—
0.40
0.60
tCK
tCK
15
—
ns
tWTR
tXARD
7.5
—
ns
20)
2
—
tCK
21)
Exit active power-down mode to Read
command (slow exit, lower power)
tXARDS
6 – AL
—
tCK
21)
Exit precharge power-down to any valid
command (other than NOP or Deselect)
tXP
2
—
tCK
Exit Self-Refresh to non-Read command
tXSNR
tXSRD
tRFC +10
—
ns
200
—
WR
tWR/tCK
—
tCK
tCK
Data hold skew factor
Average periodic refresh Interval
Average periodic refresh Interval
Auto-Refresh to Active/Auto-Refresh
command period
Precharge-All (4 banks) command period
Precharge-All (8 banks) command period
Read preamble
Read postamble
Active bank A to Active bank B command
period
Write preamble
Write postamble
Write recovery time for write without AutoPrecharge
Internal Write to Read command delay
Exit power down to any valid command
(other than NOP or Deselect)
Exit Self-Refresh to Read command
Write recovery time for write with AutoPrecharge
14)
19)
22)
1) For details and notes see the relevant Qimonda component data sheet
2) VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ±0.1 V. See notes 5)6)7)8)
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS/ RDQS,
input reference level is the crosspoint when in differential strobe mode.
6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
7) The output timing reference voltage level is VTT.
8) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to
the WR parameter stored in the MR.
9) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode.
10) For timing definition, refer to the Component data sheet.
11) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate
mis-match between DQS / DQS and associated DQ in any given cycle.
Rev. 1.0, 2006-11
11172006-DXYK-2PPW
25
Internet Data Sheet
HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B
Small Outline DDR2 SDRAM Modules
12) MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can
be greater than the minimum specification limits for tCL and tCH).
13) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving
(tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as valid data transitions.These
parameters are verified by design and characterization, but not subject to production test.
14) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C
and 95 °C.
15) 0 °C≤ TCASE ≤ 85 °C
16) 85 °C < TCASE ≤ 95 °C
17) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
18) The tRRD timing parameter depends on the page size of the DRAM organization. See Table 2 “Ordering Information for RoHS
Compliant Products” on Page 4.
19) The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
20) Minimum tWTR is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz.
21) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard active powerdown mode” (MR, A12 = “0”) a fast power-down exit timing tXARD can be used. In “low active power-down mode” (MR, A12 =”1”) a slow
power-down exit timing tXARDS has to be satisfied.
22) WR must be programmed to fulfill the minimum requirement for the tWR timing parameter, where WRMIN[cycles] = tWR(ns)/tCK(ns) rounded
up to the next integer value. tDAL = WR + (tRP/tCK). For each of the terms, if not already an integer, round to the next highest integer. tCK
refers to the application clock period. WR refers to the WR parameter stored in the MRS.
3.3.3
ODT AC Electrical Characteristics
ODT AC Character. & Operating Conditions: Table 18 for DDR2–800 & DDR2–667 and Table 19 for DDR2–533
TABLE 18
ODT AC Character. and Operating Conditions for DDR2-800 and DDR2-667
Symbol
tAOND
tAON
tAONPD
tAOFD
tAOF
tAOFPD
tANPD
tAXPD
Parameter / Condition
Values
Unit
Note
Min.
Max.
ODT turn-on delay
2
2
nCK
1)
ODT turn-on
tAC.MAX + 0.7 ns
2 tCK + tAC.MAX + 1 ns
ns
1)2)
ODT turn-on (Power-Down Modes)
tAC.MIN
tAC.MIN + 2 ns
ns
1)
ODT turn-off delay
2.5
2.5
nCK
1)
ODT turn-off
tAC.MAX + 0.6 ns
2.5 tCK + tAC.MAX + 1 ns
ns
1)3)
ODT turn-off (Power-Down Modes)
tAC.MIN
tAC.MIN + 2 ns
ns
1)
ODT to Power Down Mode Entry Latency
3
—
nCK
1)
1)
ODT Power Down Exit Latency
8
—
nCK
1) New units, 'tCK.AVG' and 'nCK', are introduced in DDR2-667 and DDR2-800. Unit 'tCK.AVG' represents the actual tCK.AVG of the input clock
under operation. Unit 'nCK' represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2-400 and
DDR2-533, 'tCK' is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may
be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 × tCK.AVG+ tEPR.2PER(MIN).
2) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when
the ODT resistance is fully on. Both are measured from tAOND, which is interpreted differently per speed bin. For DDR2-667/800, tAOND is
2 clock cycles after the clock edge that registered a first ODT HIGH counting the actual input clock edges.
3) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
Both are measured from tAOFD. Both are measured from tAOFD, which is interpreted differently per speed bin. For DDR2-667/800,if tCK.AVG =
3 ns is assumed, tAOFD= 1.5 ns (0.5 × 3 ns) after the second trailing clock edge counting from the clock edge that registered a first ODT
LOW and by counting the actual input clock edge.
Rev. 1.0, 2006-11
11172006-DXYK-2PPW
26
Internet Data Sheet
HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B
Small Outline DDR2 SDRAM Modules
TABLE 19
ODT AC Character. and Operating Conditions for DDR2-533
Symbol
Parameter / Condition
Values
Min.
tAOND
tAON
tAONPD
tAOFD
tAOF
tAOFPD
tANPD
tAXPD
Unit
Note
Max.
ODT turn-on delay
2
2
tCK
ODT turn-on
tAC.MAX + 1 ns
2 tCK + tAC.MAX + 1 ns
ns
ODT turn-on (Power-Down Modes)
tAC.MIN
tAC.MIN + 2 ns
ODT turn-off delay
2.5
2.5
tCK
ODT turn-off
tAC.MAX + 0.6 ns
2.5 tCK + tAC.MAX + 1 ns
ns
ODT turn-off (Power-Down Modes)
tAC.MIN
tAC.MIN + 2 ns
ODT to Power Down Mode Entry Latency
3
—
ODT Power Down Exit Latency
8
—
tCK
tCK
1)
ns
2)
ns
1) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when
the ODT resistance is fully on. Both are measured from tAOND, which is interpreted differently per speed bin. For DDR2-400/533, tAOND is
10 ns (= 2 x 5 ns) after the clock edge that registered a first ODT HIGH if tCK = 5 ns.
2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
Both are measured from tAOFD. Both are measured from tAOFD, which is interpreted differently per speed bin. For DDR2-400/533, tAOFD is
12.5 ns (= 2.5 x 5 ns) after the clock edge that registered a first ODT HIGH if tCK = 5 ns.
Rev. 1.0, 2006-11
11172006-DXYK-2PPW
27
Internet Data Sheet
HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B
Small Outline DDR2 SDRAM Modules
3.4
IDD Specifications and Conditions
List of Idd Specification Tables:
• Table 20 “IDD Measurement Conditions” on Page 28
• Table 21 “Definitions for IDD” on Page 29
• Table 22 “IDD Specification for HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B” on Page 30
TABLE 20
IDD Measurement Conditions
Parameter
Symbol Note
1)2)3)4)5)
Operating Current 0
IDD0
One bank Active - Precharge; tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN, CKE is HIGH, CS is HIGH between
valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING.
Operating Current 1
One bank Active - Read - Precharge; IOUT = 0 mA, BL = 4, tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN,
tRCD = tRCD.MIN, AL = 0, CL = CLMIN; CKE is HIGH, CS is HIGH between valid commands. Address and
control inputs are SWITCHING, Databus inputs are SWITCHING.
IDD1
6)
Precharge Standby Current
IDD2N
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are SWITCHING,
Databus inputs are SWITCHING.
Precharge Power-Down Current
Other control and address inputs are STABLE, Data bus inputs are FLOATING.
IDD2P
Precharge Quiet Standby Current
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are STABLE,
Data bus inputs are FLOATING.
IDD2Q
Active Standby Current
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN;
tRAS = tRAS.MAX, tRP = tRP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA.
IDD3N
Active Power-Down Current
IDD3P(0)
All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs
are FLOATING. MRS A12 bit is set to LOW (Fast Power-down Exit);
Active Power-Down Current
IDD3P(1)
All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs
are FLOATING. MRS A12 bit is set to HIGH (Slow Power-down Exit);
Operating Current - Burst Read
IDD4R
All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCKMIN; tRAS = tRASMAX;
tRP = tRPMIN; CKE is HIGH, CS is HIGH between valid commands; Address inputs are SWITCHING; Data
bus inputs are SWITCHING; IOUT = 0mA.
Operating Current - Burst Write
All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN;
tRAS = tRAS.MAX., tRP = tRP.MAX; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING;
IDD4W
Burst Refresh Current
tCK = tCK.MIN., Refresh command every tRFC = tRFC.MIN interval, CKE is HIGH, CS is HIGH between valid
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
IDD5B
Rev. 1.0, 2006-11
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28
6)
Internet Data Sheet
HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B
Small Outline DDR2 SDRAM Modules
Parameter
Symbol Note
1)2)3)4)5)
Distributed Refresh Current
tCK = tCK.MIN., Refresh command every tRFC = tREFI interval, CKE is LOW and CS is HIGH between valid
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
IDD5D
Self-Refresh Current
IDD6
CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING, Data
bus inputs are FLOATING. IDD6 current values are guaranteed up to TCASE of 85 °C max.
All Bank Interleave Read Current
IDD7
All banks are being interleaved at minimum tRC without violating tRRD using a burst length of 4. Control
and address bus inputs are STABLE during DESELECTS. Iout = 0 mA.
1) VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V
2) IDD specifications are tested after the device is properly initialized and IDD parameter are specified with ODT disabled.
3) Definitions for IDD see Table 21
4) For two rank modules: for all active current measurements the other rank is in Precharge Power-Down Mode IDD2P
6)
5) For details and notes see the relevant Qimonda component data sheet
6) IDD1, IDD4R and IDD7 current measurements are defined with the outputs disabled (IOUT = 0 mA). To achieve this on module level the output
buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to HIGH.
TABLE 21
Definitions for IDD
Parameter
Description
LOW
VIN ≤ VIL(ac).MAX, HIGH is defined as VIN ≥ VIH(ac).MIN
STABLE
Inputs are stable at a HIGH or LOW level
FLOATING
Inputs are VREF = VDDQ /2
SWITCHING
Inputs are changing between HIGH and LOW every other clock (once per 2 cycles) for address and control
signals, and inputs changing between HIGH and LOW every other data transfer (once per cycle) for DQ
signals not including mask or strobes
Rev. 1.0, 2006-11
11172006-DXYK-2PPW
29
Internet Data Sheet
HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B
Small Outline DDR2 SDRAM Modules
TABLE 22
Product Type
HYS64T256022EDL–25F–B
HYS64T256022EDL–2.5–B
HYS64T256022EDL–3–B
HYS64T256022EDL–3S–B
HYS64T256022EDL–3.7–B
IDD Specification for HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B
Organization
2 GB
2 GB
2 GB
2 GB
2 GB
×64
×64
×64
×64
×64
2 Ranks
2 Ranks
2 Ranks
2 Ranks
2 Ranks
–25F
–2.5
–3
–3S
–3.7
1096
1096
976
980
1176
1176
1056
1120
1120
192
IDD0
IDD1
IDD2N
IDD2P
IDD2Q
IDD3N
IDD3P_0 (fast)
IDD3P_1 (slow)
IDD4R
IDD4W
IDD5B
IDD5D
IDD6
IDD7
Units
Note1)
900
mA
2)
1060
940
mA
2)
1040
1040
880
mA
3)
192
192
190
190
mA
3)
1040
1040
960
960
800
mA
3)
1440
1440
1120
1120
960
mA
3)
768
768
720
720
610
mA
3)4)
240
240
240
240
240
mA
3)5)
1696
1696
1456
1460
1300
mA
2)
1696
1696
1456
1460
1300
mA
2)
1896
1896
1776
1780
1700
mA
2)
208
208
208
210
210
mA
3)6)
128
128
128
128
128
mA
3)6)
2256
2256
1936
1940
1900
mA
1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7, are defined with the outputs disabled.
2) The other rank is in IDD2P Precharge Power-Down Current mode
3) Both ranks are in the same IDDcurrent mode
4) Fast: MRS(12)=0
5) Slow: MRS(12)=1
6) IDD5D and IDD6 values are for 0°C ≤ TCase ≤ 85°C
Rev. 1.0, 2006-11
11172006-DXYK-2PPW
30
2)
Internet Data Sheet
HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B
Small Outline DDR2 SDRAM Modules
4
SPD Codes
This chapter lists all hexadecimal byte values stored in the EEPROM of the products described in this data sheet. SPD stands
for serial presence detect. All values with XX in the table are module specific bytes which are defined during production.
TABLE 23
Product Type
HYS64T256022EDL–25F–B
HYS64T256022EDL–2.5–B
HYS64T256022EDL–3–B
HYS64T256022EDL–3S–B
HYS64T256022EDL–3.7–B
SPD codes for HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B
Organization
2 GByte
2 GByte
2 GByte
2 GByte
2 GByte
×64
×64
×64
×64
×64
2 Ranks
(×8)
2 Ranks
(×8)
2 Ranks
(×8)
2 Ranks
(×8)
2 Ranks
(×8)
Label Code
PC2–
6400S–
555
PC2–
6400S–
666
PC2–
5300S–
444
PC2–
5300S–
555
PC2–
4200S–
444
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
HEX
HEX
0
Programmed SPD Bytes in EEPROM
80
80
80
80
80
1
Total number of Bytes in EEPROM
08
08
08
08
08
2
Memory Type (DDR2)
08
08
08
08
08
3
Number of Row Addresses
0E
0E
0E
0E
0E
4
Number of Column Addresses
0A
0A
0A
0A
0A
5
DIMM Rank and Stacking Information
71
71
71
71
71
6
Data Width
40
40
40
40
40
7
Not used
00
00
00
00
00
8
Interface Voltage Level
05
05
05
05
05
9
tCK @ CLMAX (Byte 18) [ns]
tAC SDRAM @ CLMAX (Byte 18) [ns]
25
25
30
30
3D
10
40
40
45
45
50
11
Error Correction Support (non-ECC, ECC)
00
00
00
00
00
12
Refresh Rate and Type
82
82
82
82
82
13
Primary SDRAM Width
08
08
08
08
08
14
Error Checking SDRAM Width
00
00
00
00
00
Rev. 1.0, 2006-11
11172006-DXYK-2PPW
31
Internet Data Sheet
Product Type
HYS64T256022EDL–25F–B
HYS64T256022EDL–2.5–B
HYS64T256022EDL–3–B
HYS64T256022EDL–3S–B
HYS64T256022EDL–3.7–B
HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B
Small Outline DDR2 SDRAM Modules
Organization
2 GByte
2 GByte
2 GByte
2 GByte
2 GByte
×64
×64
×64
×64
×64
2 Ranks
(×8)
2 Ranks
(×8)
2 Ranks
(×8)
2 Ranks
(×8)
2 Ranks
(×8)
Label Code
PC2–
6400S–
555
PC2–
6400S–
666
PC2–
5300S–
444
PC2–
5300S–
555
PC2–
4200S–
444
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
HEX
HEX
15
Not used
00
00
00
00
00
16
Burst Length Supported
0C
0C
0C
0C
0C
17
Number of Banks on SDRAM Device
08
08
08
08
08
18
Supported CAS Latencies
70
70
38
38
38
19
DIMM Mechanical Characteristics
01
01
01
01
01
20
DIMM Type Information
04
04
04
04
04
21
DIMM Attributes
00
00
00
00
00
22
Component Attributes
07
07
07
07
07
23
25
30
30
3D
3D
30
tCK @ CLMAX -1 (Byte 18) [ns]
tAC SDRAM @ CLMAX -1 [ns]
tCK @ CLMAX -2 (Byte 18) [ns]
tAC SDRAM @ CLMAX -2 [ns]
tRP.MIN [ns]
tRRD.MIN [ns]
tRCD.MIN [ns]
tRAS.MIN [ns]
2D
2D
2D
2D
2D
31
Module Density per Rank
01
01
01
01
01
32
tAS.MIN and tCS.MIN [ns]
tAH.MIN and tCH.MIN [ns]
tDS.MIN [ns]
tDH.MIN [ns]
tWR.MIN [ns]
tWTR.MIN [ns]
24
25
26
27
28
29
33
34
35
36
37
Rev. 1.0, 2006-11
11172006-DXYK-2PPW
32
40
45
45
50
50
3D
3D
50
50
50
50
50
60
60
60
32
3C
30
3C
3C
1E
1E
1E
1E
1E
32
3C
30
3C
3C
17
17
20
20
25
25
25
27
27
37
05
05
10
10
10
12
12
17
17
22
3C
3C
3C
3C
3C
1E
1E
1E
1E
1E
Internet Data Sheet
Product Type
HYS64T256022EDL–25F–B
HYS64T256022EDL–2.5–B
HYS64T256022EDL–3–B
HYS64T256022EDL–3S–B
HYS64T256022EDL–3.7–B
HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B
Small Outline DDR2 SDRAM Modules
Organization
2 GByte
2 GByte
2 GByte
2 GByte
2 GByte
×64
×64
×64
×64
×64
2 Ranks
(×8)
2 Ranks
(×8)
2 Ranks
(×8)
2 Ranks
(×8)
2 Ranks
(×8)
Label Code
PC2–
6400S–
555
PC2–
6400S–
666
PC2–
5300S–
444
PC2–
5300S–
555
PC2–
4200S–
444
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
HEX
HEX
38
tRTP.MIN [ns]
1E
1E
1E
1E
1E
39
Analysis Characteristics
00
00
00
00
00
40
06
06
06
06
06
39
3C
39
3C
3C
7F
7F
7F
7F
7F
80
80
80
80
80
14
14
18
18
1E
45
tRC and tRFC Extension
tRC.MIN [ns]
tRFC.MIN [ns]
tCK.MAX [ns]
tDQSQ.MAX [ns]
tQHS.MAX [ns]
1E
1E
22
22
28
46
PLL Relock Time
00
00
00
00
00
41
42
43
44
47
TCASE.MAX Delta / ∆T4R4W Delta
57
50
50
50
50
48
Psi(T-A) DRAM
60
00
00
00
00
49
∆T0 (DT0)
5F
00
00
00
00
50
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM)
40
00
00
00
00
51
∆T2P (DT2P)
2B
00
00
00
00
52
∆T3N (DT3N)
2E
00
00
00
00
53
∆T3P.fast (DT3P fast)
49
00
00
00
00
54
∆T3P.slow (DT3P slow)
21
00
00
00
00
55
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)
4E
00
00
00
00
56
∆T5B (DT5B)
25
00
00
00
00
57
∆T7 (DT7)
39
00
00
00
00
58
Psi(ca) PLL
00
00
00
00
00
59
Psi(ca) REG
00
00
00
00
00
60
∆TPLL (DTPLL)
00
00
00
00
00
Rev. 1.0, 2006-11
11172006-DXYK-2PPW
33
Internet Data Sheet
Product Type
HYS64T256022EDL–25F–B
HYS64T256022EDL–2.5–B
HYS64T256022EDL–3–B
HYS64T256022EDL–3S–B
HYS64T256022EDL–3.7–B
HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B
Small Outline DDR2 SDRAM Modules
Organization
2 GByte
2 GByte
2 GByte
2 GByte
2 GByte
×64
×64
×64
×64
×64
2 Ranks
(×8)
2 Ranks
(×8)
2 Ranks
(×8)
2 Ranks
(×8)
2 Ranks
(×8)
Label Code
PC2–
6400S–
555
PC2–
6400S–
666
PC2–
5300S–
444
PC2–
5300S–
555
PC2–
4200S–
444
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
HEX
HEX
61
∆TREG (DTREG) / Toggle Rate
00
00
00
00
00
62
SPD Revision
12
12
12
12
12
63
Checksum of Bytes 0-62
91
43
46
79
BD
64
Manufacturer’s JEDEC ID Code (1)
7F
7F
7F
7F
7F
65
Manufacturer’s JEDEC ID Code (2)
7F
7F
7F
7F
7F
66
Manufacturer’s JEDEC ID Code (3)
7F
7F
7F
7F
7F
67
Manufacturer’s JEDEC ID Code (4)
7F
7F
7F
7F
7F
68
Manufacturer’s JEDEC ID Code (5)
7F
7F
7F
7F
7F
69
Manufacturer’s JEDEC ID Code (6)
51
51
51
51
51
70
Manufacturer’s JEDEC ID Code (7)
00
00
00
00
00
71
Manufacturer’s JEDEC ID Code (8)
00
00
00
00
00
72
Module Manufacturer Location
xx
xx
xx
xx
xx
73
Product Type, Char 1
36
36
36
36
36
74
Product Type, Char 2
34
34
34
34
34
75
Product Type, Char 3
54
54
54
54
54
76
Product Type, Char 4
32
32
32
32
32
77
Product Type, Char 5
35
35
35
35
35
78
Product Type, Char 6
36
36
36
36
36
79
Product Type, Char 7
30
30
30
30
30
80
Product Type, Char 8
32
32
32
32
32
81
Product Type, Char 9
32
32
32
32
32
82
Product Type, Char 10
45
45
45
45
45
83
Product Type, Char 11
44
44
44
44
44
Rev. 1.0, 2006-11
11172006-DXYK-2PPW
34
Internet Data Sheet
Product Type
HYS64T256022EDL–25F–B
HYS64T256022EDL–2.5–B
HYS64T256022EDL–3–B
HYS64T256022EDL–3S–B
HYS64T256022EDL–3.7–B
HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B
Small Outline DDR2 SDRAM Modules
Organization
2 GByte
2 GByte
2 GByte
2 GByte
2 GByte
×64
×64
×64
×64
×64
2 Ranks
(×8)
2 Ranks
(×8)
2 Ranks
(×8)
2 Ranks
(×8)
2 Ranks
(×8)
Label Code
PC2–
6400S–
555
PC2–
6400S–
666
PC2–
5300S–
444
PC2–
5300S–
555
PC2–
4200S–
444
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
HEX
HEX
84
Product Type, Char 12
4C
4C
4C
4C
4C
85
Product Type, Char 13
32
32
33
33
33
86
Product Type, Char 14
35
2E
42
53
2E
87
Product Type, Char 15
46
35
20
42
37
88
Product Type, Char 16
42
42
20
20
42
89
Product Type, Char 17
20
20
20
20
20
90
Product Type, Char 18
20
20
20
20
20
91
Module Revision Code
0x
3x
3x
3x
3x
92
Test Program Revision Code
xx
xx
xx
xx
xx
93
Module Manufacturing Date Year
xx
xx
xx
xx
xx
94
Module Manufacturing Date Week
xx
xx
xx
xx
xx
95 - 98
Module Serial Number
xx
xx
xx
xx
xx
99 - 127 Not used
00
00
00
00
00
128 255
FF
FF
FF
FF
FF
Blank for customer use
Rev. 1.0, 2006-11
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35
Internet Data Sheet
HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B
Small Outline DDR2 SDRAM Modules
5
Package Outlines
FIGURE 5
Package Outline Raw Card D L-DIM-200-33
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63'
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Notes
1. Drawing according to ISO 8015
2. Dimensions in mm
3. General tolerances +/- 0.15
Rev. 1.0, 2006-11
11172006-DXYK-2PPW
36
Internet Data Sheet
HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B
Small Outline DDR2 SDRAM Modules
6
Product Type Nomenclature
Qimonda’s nomenclature uses simple coding combined with some proprietary coding. Table 24 provides examples for module
and component product type number as well as the field number. The detailed field description together with possible values
and coding explanation is listed for modules in Table 25 and for components in Table 26.
TABLE 24
Nomenclature Fields and Examples
Example for
Field Number
1
2
3
4
5
6
7
8
9
10
11
Micro-DIMM
HYS
64
T
64/128
0
2
0
K
M
–5
–A
DDR2 DRAM
HYB
18
T
512/1G 16
0
A
C
–5
TABLE 25
DDR2 DIMM Nomenclature
Field
Description
Values
Coding
1
Qimonda Module Prefix
HYS
Constant
2
Module Data Width [bit]
64
Non-ECC
72
ECC
3
DRAM Technology
T
DDR2
4
Memory Density per I/O [Mbit];
Module Density1)
32
256 MByte
64
512 MByte
128
1 GByte
256
2 GByte
512
4 GByte
5
Raw Card Generation
0 .. 9
Look up table
6
Number of Module Ranks
0, 2, 4
1, 2, 4
7
Product Variations
0 .. 9
Look up table
8
Package, Lead-Free Status
A .. Z
Look up table
9
Module Type
D
SO-DIMM
M
Micro-DIMM
R
Registered
U
Unbuffered
F
Fully Buffered
Rev. 1.0, 2006-11
11172006-DXYK-2PPW
37
Internet Data Sheet
HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B
Small Outline DDR2 SDRAM Modules
Field
Description
Values
Coding
10
Speed Grade
–2.5F
PC2–6400 5–5–5
–2.5
PC2–6400 6–6–6
11
Die Revision
–3
PC2–5300 4–4–4
–3S
PC2–5300 5–5–5
–3.7
PC2–4200 4–4–4
–5
PC2–3200 3–3–3
–A
First
–B
Second
1) Multiplying “Memory Density per I/O” with “Module Data Width” and dividing by 8 for Non-ECC and 9 for ECC modules gives the overall
module memory density in MBytes as listed in column “Coding”.
TABLE 26
DDR2 DRAM Nomenclature
Field
Description
Values
Coding
1
Qimonda Component Prefix
HYB
Constant
2
Interface Voltage [V]
18
SSTL_18
3
DRAM Technology
T
DDR2
4
Component Density [Mbit]
256
256 Mbit
512
512 Mbit
1G
1 Gbit
2G
2 Gbit
40
×4
80
×8
16
×16
5+6
Number of I/Os
7
Product Variations
0 .. 9
Look up table
8
Die Revision
A
First
B
Second
9
10
Package, Lead-Free Status
Speed Grade
Rev. 1.0, 2006-11
11172006-DXYK-2PPW
C
FBGA, lead-containing
F
FBGA, lead-free
–25F
DDR2-800 5-5-5
–2.5
DDR2-800 6-6-6
–3
DDR2-667 4-4-4
–3S
DDR2-667 5-5-5
–3.7
DDR2-533 4-4-4
–5
DDR2-400 3-3-3
38
Internet Data Sheet
HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B
Small Outline DDR2 SDRAM Modules
Table of Contents
1
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
3.1
3.2
3.3
3.3.1
3.3.2
3.3.3
3.4
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Speed Grade Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Component AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ODT AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IDD Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6
Product Type Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
12
12
13
14
14
17
26
28
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Rev. 1.0, 2006-11
11172006-DXYK-2PPW
39
Internet Data Sheet
Edition 2006-11
Published by Qimonda AG
Gustav-Heinemann-Ring 212
D-81739 München, Germany
© Qimonda AG 2006.
All Rights Reserved.
Legal Disclaimer
The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics
(“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind,
including without limitation warranties of non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office.
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in question please
contact your nearest Qimonda Office.
Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a
failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect
the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human
body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health
of the user or other persons may be endangered.
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