September 2006 HYS64D32301HU–[5/6]–C HYS[7 2/64]D 64 3 0 0 H U– [ 5 / 6 ] – C HYS[64/72]D128320HU–[5/6]–C 184-Pin Unbuffered Double Data Rate SDRAM UDIMM DDR SDRAM RoHS Compliant Products Internet Data Sheet Rev. 1.21 Internet Data Sheet HYS[64/72]D[16/32/128]3xxHU–[5/6]–C Unbuffered DDR SDRAM Modules HYS64D32301HU–[5/6]–C, HYS[72/64]D64300HU–[5/6]–C, HYS[64/72]D128320HU–[5/6]–C Revision History: 2006-09, Rev. 1.21 Page Subjects (major changes since last revision) All Adapted internet edition Previous Revision: Rev. 1.20, 2005-12 14 changed component configuration for 256MB to 32M x16 26 changed DDR400 tRFC from 70 ns to 65 ns Previous Revision: Rev. 1.10, 2005-05 We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: [email protected] qag_techdoc_rev400 / 3.2 QAG / 2006-08-01 03292006-RA8T-MSZL 2 Internet Data Sheet HYS[64/72]D[16/32/128]3xxHU–[5/6]–C Unbuffered DDR SDRAM Modules 1 Overview This chapter gives an overview of the 184-Pin Unbuffered Double Data Rate SDRAM product family and describes its main characteristics. 1.1 Features • 184-Pin Unbuffered Double Data Rate SDRAM (ECC and non-parity) for PC and Workstation main memory applications • One rank 32M ×64, 64M ×64, 64M ×72 ,and two ranks 128M ×64 ,128M ×72 organization • Standard Double Data Rate Synchronous DRAMs (DDR SDRAM) Single +2.5V (±0.2V) and +2.6V (±0.1V) power supply for DDR400 • Built with 512 Mbit DDR SDRAM in P-TSOPII-66-1 package • Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) • Auto Refresh (CBR) and Self Refresh • RAS-lockout supported tRAP=tRCD • All inputs and outputs SSTL_2 compatible • Serial Presence Detect with E2PROM • Standard MO-206 form factor: 133.35 mm × 31.75 mm × 4.00 mm max. • Standard reference layout for raw cards: A, B and C • Gold plated contacts • RoHS Compliant Product1) TABLE 1 Performance Part Number Speed Code Speed Grade Component Module max. Clock Frequency @CL3 @CL2.5 @CL2 fCK3 fCK2.5 fCK2 –5 –6 Unit DDR400B DDR333B — PC3200–3033 PC2700–2533 — 200 166 MHz 166 166 MHz 133 133 MHz 1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers. Rev. 1.21, 2006-09 03292006-RA8T-MSZL 3 Internet Data Sheet HYS[64/72]D[16/32/128]3xxHU–[5/6]–C Unbuffered DDR SDRAM Modules 1.2 Description The HYS64D32301HU–[5/6]–C, HYS[72/64]D64300HU– [5/6]–C, HYS[64/72]D128320HU–[5/6]–C, and are industry standard 184-Pin Unbuffered Double Data Rate SDRAM (UDIMM) organized as 32M × 64 (256 MB), 64M × 64 (512 MB), 128M × 64 (1 GB) for non-parity and 64M × 72 (512 MB), 128M × 72 (1 GB) for ECC main memory applications. The memory array is designed with 512Mbit Double Data Rate Synchronous DRAMs. A variety of decoupling capacitors are mounted on the printed circuit board. The DIMMs feature serial presence detect (SPD) based on a serial E2PROM device using the 2pin I2C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer TABLE 2 Ordering Information for Lead-Free Products (RoHSCompliant Product) Product Type 1) Compliance Code2) Description SDRAM Technology PC3200 (CL=3.0) HYS64D32301HU–5–C PC3200U–30331–C3 one rank 256 MB DIMM 512 Mbit (×16) HYS64D64300HU–5–C PC3200U–30331–A1 one rank 512 MB DIMM 512 Mbit (×8) HYS72D64300HU–5–C PC3200U–30331–A1 one rank 512 MB ECC-DIMM 512 Mbit (×8) HYS64D128320HU–5–C PC3200U–30331–B2 two ranks 1 GB DIMM 512 Mbit (×8) HYS72D128320HU–5–C PC3200U–30331–B2 two ranks 1 GB ECC-DIMM 512 Mbit (×8) HYS64D32301HU–6–C PC2700U–25331–C3 one rank 256 MB DIMM 512 Mbit (×16) HYS64D64300HU–6–C PC2700U–25331–A1 one rank 512 MB DIMM 512 Mbit (×8) HYS72D64300HU–6–C PC2700U–25331–A1 one rank 512 MB ECC-DIMM 512 Mbit (×8) HYS64D128320HU–6–C PC2700U–25331–B2 two ranks 1 GB DIMM 512 Mbit (×8) HYS72D128320HU–6–C PC2700U–25331–B2 two ranks 1 GB ECC-DIMM 512 Mbit (×8) PC2700 (CL=2.5) 1) All product types end with a place code designating the silicon-die revision. Reference information available on request. Example: HYS64D128320HU–5–C, indicating Rev.C die are used for SDRAM components. 2) The Compliance Code is printed on the module labels and describes the speed sort (for example “PC3200”), the latencies (for example “30330” means CAS latency of 3.0 clocks, Row-Column-Delay (RCD) latency of 3 clocks and Row Precharge latency of 3 clocks), JEDEC SPD code definition version 0, and the Raw Card used for this module. Rev. 1.21, 2006-09 03292006-RA8T-MSZL 4 Internet Data Sheet HYS[64/72]D[16/32/128]3xxHU–[5/6]–C Unbuffered DDR SDRAM Modules 2 Pin Configuration The pin configuration of the Unbuffered DDR SDRAM DIMM is listed by function in Table 3 (184 pins). The abbreviations used in columns Pin and Buffer Type are explained in Table 4 and Table 5 respectively. The pin numbering is depicted in Figure 1. TABLE 3 Pin Configuration of UDIMM Pin# Name Pin Type Buffer Type Function CK0 I SSTL Clock Signals 2:0 NC NC – CK1 I SSTL 76 CK2 I SSTL 138 CK0 I SSTL NC NC – 17 CK1 I SSTL 75 CK2 I SSTL 21 CKE0 I SSTL Clock Enable Rank 0 111 CKE1 I SSTL Clock Enable Rank 1 Note: 2-rank module NC NC – Note: 1-rank module Clock Signals 137 16 Complement Clock Signals 2:0 Control Signals 157 S0 I SSTL Chip Select Rank 0 158 S1 I SSTL Chip Select Rank 1 Note: 2-rank module NC NC – Note: 1-rank module 154 RAS I SSTL Row Address Strobe 65 CAS I SSTL Column Address Strobe 63 WE I SSTL Write Enable Bank Address Bus 2:0 Address Signals 59 BA0 I SSTL 52 BA1 I SSTL Rev. 1.21, 2006-09 03292006-RA8T-MSZL 5 Internet Data Sheet HYS[64/72]D[16/32/128]3xxHU–[5/6]–C Unbuffered DDR SDRAM Modules Pin# Name Pin Type Buffer Type Function 48 A0 I SSTL Address Bus 11:0 43 A1 I SSTL 41 A2 I SSTL 130 A3 I SSTL 37 A4 I SSTL 32 A5 I SSTL 125 A6 I SSTL 29 A7 I SSTL 122 A8 I SSTL 27 A9 I SSTL 141 A10 I SSTL AP I SSTL 118 A11 I SSTL 115 A12 I SSTL Address Signal 12 Note: Module based on 256 Mbit or larger dies NC NC – Note: 128 Mbit based module A13 I SSTL Address Signal 13 Note: 1 Gbit based module NC NC – Note: Module based on 512 Mbit or smaller dies 167 Rev. 1.21, 2006-09 03292006-RA8T-MSZL Address Bus 11:0 6 Internet Data Sheet HYS[64/72]D[16/32/128]3xxHU–[5/6]–C Unbuffered DDR SDRAM Modules Pin# Name Pin Type Buffer Type Function Data Bus 63:0 Data Signals 2 DQ0 I/O SSTL 4 DQ1 I/O SSTL 6 DQ2 I/O SSTL 8 DQ3 I/O SSTL 94 DQ4 I/O SSTL 95 DQ5 I/O SSTL 98 DQ6 I/O SSTL 99 DQ7 I/O SSTL 12 DQ8 I/O SSTL 13 DQ9 I/O SSTL 19 DQ10 I/O SSTL 20 DQ11 I/O SSTL 105 DQ12 I/O SSTL 106 DQ13 I/O SSTL 109 DQ14 I/O SSTL 110 DQ15 I/O SSTL 23 DQ16 I/O SSTL 24 DQ17 I/O SSTL 28 DQ18 I/O SSTL 31 DQ19 I/O SSTL 114 DQ20 I/O SSTL 117 DQ21 I/O SSTL Rev. 1.21, 2006-09 03292006-RA8T-MSZL 7 Internet Data Sheet HYS[64/72]D[16/32/128]3xxHU–[5/6]–C Unbuffered DDR SDRAM Modules Pin# Name Pin Type Buffer Type Function 121 DQ22 I/O SSTL Data Bus 63:0 123 DQ23 I/O SSTL 33 DQ24 I/O SSTL 35 DQ25 I/O SSTL 39 DQ26 I/O SSTL 40 DQ27 I/O SSTL 126 DQ28 I/O SSTL 127 DQ29 I/O SSTL 131 DQ30 I/O SSTL 133 DQ31 I/O SSTL 53 DQ32 I/O SSTL 55 DQ33 I/O SSTL 57 DQ34 I/O SSTL 60 DQ35 I/O SSTL 146 DQ36 I/O SSTL 147 DQ37 I/O SSTL 150 DQ38 I/O SSTL 151 DQ39 I/O SSTL 61 DQ40 I/O SSTL 64 DQ41 I/O SSTL 68 DQ42 I/O SSTL 69 DQ43 I/O SSTL 153 DQ44 I/O SSTL 155 DQ45 I/O SSTL 161 DQ46 I/O SSTL 162 DQ47 I/O SSTL 72 DQ48 I/O SSTL 73 DQ49 I/O SSTL 79 DQ50 I/O SSTL 80 DQ51 I/O SSTL 165 DQ52 I/O SSTL 166 DQ53 I/O SSTL 170 DQ54 I/O SSTL 171 DQ55 I/O SSTL 83 DQ56 I/O SSTL 84 DQ57 I/O SSTL 87 DQ58 I/O SSTL 88 DQ59 I/O SSTL 174 DQ60 I/O SSTL 175 DQ61 I/O SSTL Rev. 1.21, 2006-09 03292006-RA8T-MSZL 8 Internet Data Sheet HYS[64/72]D[16/32/128]3xxHU–[5/6]–C Unbuffered DDR SDRAM Modules Pin# Name Pin Type Buffer Type Function 178 DQ62 I/O SSTL Data Bus 63:0 179 DQ63 I/O SSTL 44 CB0 I/O SSTL NC NC – CB1 I/O SSTL NC NC – 49 CB2 I/O SSTL NC NC – 51 CB3 I/O SSTL NC NC – 134 CB4 I/O SSTL NC NC – CB5 I/O SSTL NC NC – 142 CB6 I/O SSTL NC NC – 144 CB7 I/O SSTL NC NC – 5 DQS0 I/O SSTL 14 DQS1 I/O SSTL 25 DQS2 I/O SSTL 36 DQS3 I/O SSTL 56 DQS4 I/O SSTL 67 DQS5 I/O SSTL 78 DQS6 I/O SSTL 86 DQS7 I/O SSTL 47 DQS8 I/O SSTL NC NC – 97 DM0 I SSTL 107 DM1 I SSTL 119 DM2 I SSTL 129 DM3 I SSTL 149 DM4 I SSTL 159 DM5 I SSTL 169 DM6 I SSTL 177 DM7 I SSTL 140 DM8 I SSTL NC NC – SCL I CMOS 45 135 Check Bit 0 Check Bit 1 Check Bit 2 Check Bit 3 Check Bit 4 Check Bit 5 Check Bit 6 Check Bit 7 Data Strobe Bus 7:0 Data Strobe 8 Data Mask Bus 7:0 Data Mask 8 EEPROM 92 Rev. 1.21, 2006-09 03292006-RA8T-MSZL Serial Bus Clock 9 Internet Data Sheet HYS[64/72]D[16/32/128]3xxHU–[5/6]–C Unbuffered DDR SDRAM Modules Pin# Name Pin Type Buffer Type Function 91 SDA I/O OD Serial Bus Data Slave Address Select Bus 2:0 181 SA0 I CMOS 182 SA1 I CMOS 183 SA2 I CMOS Power Supplies 1 VREF AI – I/O Reference Voltage 184 VDDSPD PWR – EEPROM Power Supply 15, 22, 30, 54, 62, 77, 96, 104, 112, 128, 136, 143, 156, 164, 172, 180 VDDQ PWR – I/O Driver Power Supply 7, 38, 46, 70, 85, 108, 120, 148, 168 VDD PWR – Power Supply Rev. 1.21, 2006-09 03292006-RA8T-MSZL 10 Internet Data Sheet HYS[64/72]D[16/32/128]3xxHU–[5/6]–C Unbuffered DDR SDRAM Modules Pin# Name Pin Type Buffer Type Function 3, 11, 18, 26, 34, 42, 50, 58, 66, 74, 81, 89, 93, 100, 116, 124, 132, 139, 145, 152, 160, 176 VSS GND – Ground Plane 82 VDDID O OD VDD Identification 9, 10, 71, 90, 101, 102, 103, 113, 163, 173 NC NC – Not connected Other Pins Rev. 1.21, 2006-09 03292006-RA8T-MSZL 11 Internet Data Sheet HYS[64/72]D[16/32/128]3xxHU–[5/6]–C Unbuffered DDR SDRAM Modules TABLE 4 Abbreviations for Pin Type Abbreviation Description I Standard input-only pin. Digital levels. O Output. Digital levels. I/O I/O is a bidirectional input/output signal. AI Input. Analog levels. PWR Power GND Ground NC Not Connected TABLE 5 Abbreviations for Buffer Type Abbreviation Description SSTL Serial Stub Terminated Logic (SSTL2) LV-CMOS Low Voltage CMOS CMOS CMOS Levels OD Open Drain. The corresponding pin has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-OR. Rev. 1.21, 2006-09 03292006-RA8T-MSZL 12 Internet Data Sheet HYS[64/72]D[16/32/128]3xxHU–[5/6]–C Unbuffered DDR SDRAM Modules FIGURE 1 Pin Configuration 184-Pin, UDIMM 95() 3LQ 966 3LQ '46 3LQ 9'' 3LQ 1& 3LQ 966 3LQ '4 3LQ 9''4 3LQ &. 3LQ '4 3LQ &.( 3LQ '4 3LQ '46 3LQ $ 3LQ $ 3LQ '4 3LQ '4 3LQ '4 3LQ $ 3LQ '4 3LQ $ 3LQ $ 3LQ &% 1& 3LQ '46 1& 3LQ &% 1& 3LQ &% 1& 3LQ '4 3LQ '4 3LQ '4 3LQ %$ 3LQ '4 3LQ :( 3LQ &$6 3LQ '46 3LQ '4 3LQ 1& 3LQ '4 3LQ &. 3LQ 9''4 3LQ '4 3LQ 966 3LQ '4 3LQ 9'' 3LQ '4 3LQ 966 3LQ 6'$ 3LQ '4 3LQ '4 3LQ '4 3LQ '4 3LQ 1& 3LQ '4 3LQ '46 3LQ &. 3LQ 966 3LQ '4 3LQ 9''4 3LQ '4 3LQ 966 3LQ '4 3LQ 9''4 3LQ $ 3LQ 966 3LQ '46 3LQ 9'' 3LQ '4 3LQ 966 3LQ &% 1& 3LQ 9'' 3LQ $ 3LQ 966 3LQ %$ 3LQ 3LQ '4 3LQ 9''4 3LQ '4 3LQ 966 3LQ 1& 3LQ 9''4 3LQ '4 3LQ 9'' 3LQ '4 3LQ 9''4 ) 5 2 1 7 6 , ' ( % $ & . 6 , ' ( 3LQ '4 3LQ 966 3LQ $ 3LQ 9'' 3LQ $ 3LQ 966 3LQ '4 3LQ 9''4 3LQ $ 3LQ 966 3LQ &%1& 3LQ 9''4 3LQ &.1& 3LQ '01& 3LQ &%1& 3LQ &%1& 9''4 3LQ '46 3LQ 966 3LQ '4 3LQ 9''4 3LQ '4 3LQ 966 3LQ '4 3LQ 9'' 3LQ '4 3LQ 966 3LQ &. 3LQ '46 3LQ '4 3LQ 9'',' 3LQ '4 3LQ '46 3LQ '4 3LQ 1& 3LQ 6&/ 3LQ 3LQ '4 3LQ 9'' 3LQ '4 3LQ 966 3LQ 5$6 3LQ 9''4 3LQ 61& 3LQ 966 3LQ '4 3LQ 9''4 3LQ '4 3LQ 9'' 3LQ '4 3LQ 9''4 '4 3LQ 3LQ 966 3LQ '4 3LQ 9''4 3LQ 6$ 3LQ 9''63 ' 3LQ 966 3LQ '4 3LQ '0 3LQ '4 3LQ 1& 3LQ 1& 3LQ '4 3LQ '0 3LQ '4 3LQ &.(1& 3LQ 1& 3LQ $ 1& 3LQ '4 3LQ '0 3LQ '4 3LQ '4 3LQ $ 3LQ '4 3LQ '0 3LQ '4 3LQ '4 3LQ &%1& 3LQ &.1& 3LQ 966 3LQ $ $3 3LQ 9''4 3LQ 966 3LQ '4 3LQ '0 3LQ '4 3LQ '4 3LQ '4 3LQ 6 3LQ '0 3LQ '4 3LQ 1& 3LQ '4 1& 3LQ $ 3LQ '0 3LQ '4 1& 3LQ 3LQ '4 3LQ '0 3LQ '4 3LQ 6$ 3LQ 6$ 033 ' 2. DQ, DQS, DM resistors are 22 Ω ±5 % 3. BAn, An, RAS, CAS, WE resistors are 3 Ω ±5 % Notes 1. VDD = VDDQ, therefore VDDID strap open Rev. 1.21, 2006-09 03292006-RA8T-MSZL 13 Internet Data Sheet HYS[64/72]D[16/32/128]3xxHU–[5/6]–C Unbuffered DDR SDRAM Modules TABLE 6 Address Format Density Organization Memory Ranks SDRAMs # of SDRAMs # of row/bank/ columns bits Refresh Period Interval 256 MB 32M ×64 1 32M ×16 4 13/2/10 8K 64 ms 7.8 ms 512 MB 64M ×64 1 64M ×8 8 13/2/11 8K 64 ms 7.8 ms 512 MB 64M ×72 1 64M ×8 9 13/2/11 8K 64 ms 7.8 ms 1 GB 128M ×64 2 64M ×8 16 13/2/11 8K 64 ms 7.8 ms 1 GB 128M ×72 2 64M ×8 18 13/2/11 8K 64 ms 7.8 ms Rev. 1.21, 2006-09 03292006-RA8T-MSZL 14 Internet Data Sheet HYS[64/72]D[16/32/128]3xxHU–[5/6]–C Unbuffered DDR SDRAM Modules 3 Electrical Characteristics 3.1 Operating Conditions TABLE 12 Absolute Maximum Ratings Parameter Symbol Values Unit Note/ Test Condition min. typ. max. –0.5 – VDDQ + 0.5 V – –1 – +3.6 V – –1 – +3.6 V – Storage temperature (plastic) VIN, VOUT VIN VDD VDDQ TA TSTG Power dissipation (per SDRAM component) Short circuit output current Voltage on I/O pins relative to VSS Voltage on inputs relative to VSS Voltage on VDD supply relative to VSS Voltage on VDDQ supply relative to VSS Operating temperature (ambient) –1 – +3.6 V – 0 – +70 °C – -55 – +150 °C – PD – 1 – W – IOUT – 50 – mA – Attention: Permanent damage to the device may occur if “Absolute Maximum Ratings” are exceeded. This is a stress rating only, and functional operation should be restricted to recommended operation conditions. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability and exceeding only one of the values may cause irreversible damage to the integrated circuit. TABLE 13 Electrical Characteristics and DC Operating Conditions Parameter Symbol Unit Note/Test Condition 1) Values Min. Typ. Max. Device Supply Voltage VDD 2.3 2.5 2.7 V fck ≤ 166 MHz Device Supply Voltage VDD 2.5 2.6 2.7 V fck ≤ 166 MHz 2) Output Supply Voltage VDDQ 2.3 2.5 2.7 V fck ≤ 166 MHz 3) Output Supply Voltage VDDQ 2.5 2.6 2.7 V fck ≤ 166 MHz 2)3) EEPROM supply voltage VDDSPD 2.3 2.5 3.6 V — Supply Voltage, I/O Supply Voltage VSS, VSSQ 0 0 V — Input Reference Voltage VREF 0.49 × VDDQ 0.51 × VDDQ V 4) I/O Termination Voltage (System) VTT VREF – 0.04 VREF + 0.04 V 5) Rev. 1.21, 2006-09 03292006-RA8T-MSZL 0.5 × VDDQ 21 Internet Data Sheet HYS[64/72]D[16/32/128]3xxHU–[5/6]–C Unbuffered DDR SDRAM Modules Parameter Symbol Unit Note/Test Condition 1) Values Min. Typ. Max. Input High (Logic1) Voltage VIH(DC) VREF + 0.15 VDDQ + 0.3 V 6) Input Low (Logic0) Voltage VIL(DC) –0.3 VREF – 0.15 V 6) Input Voltage Level, CK and CK Inputs VIN(DC) –0.3 VDDQ + 0.3 V 6) Input Differential Voltage, CK and CK Inputs VID(DC) 0.36 VDDQ + 0.6 V 6)7) VI-Matching Pull-up Current to Pull-down Current VIRatio 0.71 1.4 — 8) Input Leakage Current II –2 2 µA Any input 0 V ≤ VIN ≤ VDD; All other pins not under test = 0 V 9) Output Leakage Current IOZ –5 5 µA DQs are disabled; 0 V ≤ VOUT ≤ VDDQ 9) Output High Current, Normal IOH Strength Driver — –16.2 mA VOUT = 1.95 V Output Low Current, Normal Strength Driver 16.2 — mA VOUT = 0.35 V 1) 2) 3) 4) 5) 6) 7) 8) 9) IOL 0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V; VDDQ = 2.6 V ± 0.1 V, VDD = +2.6 V ± 0.1 V (DDR400); DDR400 conditions apply for all clock frequencies above 166 MHz Under all conditions, VDDQ must be less than or equal to VDD. Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC). VREF is also expected to track noise variations in VDDQ. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. Inputs are not recognized as valid until VREF stabilizes. VID is the magnitude of the difference between the input level on CK and the input level on CK. The ratio of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the maximum difference between pull-up and pull-down drivers due to process variation. Values are shown per pin. Rev. 1.21, 2006-09 03292006-RA8T-MSZL 22 Internet Data Sheet HYS[64/72]D[16/32/128]3xxHU–[5/6]–C Unbuffered DDR SDRAM Modules 3.2 IDD Specification and Conditions TABLE 14 IDD Conditions Parameter Symbol Operating Current 0 one bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once every two clock cycles. IDD0 Operating Current 1 one bank; active/read/precharge; Burst Length = 4; see component data sheet. IDD1 Precharge Power-Down Standby Current all banks idle; power-down mode; CKE ≤ VIL,MAX IDD2P Precharge Floating Standby Current CS ≥ VIH,,MIN, all banks idle; CKE ≥ VIH,MIN; address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS and DM. IDD2F Precharge Quiet Standby Current CS ≥ VIHMIN, all banks idle; CKE ≥ VIH,MIN; VIN = VREF for DQ, DQS and DM; address and other control inputs stable at ≥ VIH,MIN or ≤ VIL,MAX. IDD2Q Active Power-Down Standby Current one bank active; power-down mode; CKE ≤ VILMAX; VIN = VREF for DQ, DQS and DM. IDD3P Active Standby Current one bank active; CS ≥ VIH,MIN; CKE ≥ VIH,MIN; tRC = tRAS,MAX; DQ, DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle. IDD3N Operating Current Read one bank active; Burst Length = 2; reads; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B; IOUT = 0 mA IDD4R Operating Current Write one bank active; Burst Length = 2; writes; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B IDD4W Auto-Refresh Current tRC = tRFCMIN, burst refresh IDD5 Self-Refresh Current CKE ≤ 0.2 V; external clock on IDD6 Operating Current 7 four bank interleaving with Burst Length = 4; see component data sheet. IDD7 Rev. 1.21, 2006-09 03292006-RA8T-MSZL 23 Internet Data Sheet HYS[64/72]D[16/32/128]3xxHU–[5/6]–C Unbuffered DDR SDRAM Modules TABLE 15 Product Type HYS64D32301HU–5–C HYS64D64300HU–5–C HYS72D64300HU–5–C HYS64D128320HU–5–C HYS72D128320HU–5–C IDD Specification for HYS[64/72]D[32/64/128]3xxHU–5–C Organization 256MB 512MB 512MB 1GB 1GB ×64 ×64 ×72 ×64 ×72 1 Rank 1 Rank 1 Rank 2 Ranks 2 Ranks –5 –5 –5 –5 –5 Unit Note 1)2) Symbol Typ. Max. Typ. Max. Typ. Max. Typ. Max. Typ. Max. IDD0 300 360 480 600 540 680 760 940 860 1050 mA 3) IDD1 360 440 560 680 630 770 840 1020 950 1140 mA 3)4) IDD2P 4 18 9 37 10 41 18 74 20 83 mA 5) IDD2F 100 120 200 240 230 270 400 480 450 540 mA 5) IDD2Q 70 90 140 180 150 210 270 370 310 410 mA 5) IDD3P 50 60 100 130 110 140 190 260 220 290 mA 5) IDD3N 150 180 280 340 320 380 560 670 630 760 mA 5) IDD4R 440 540 640 720 720 810 920 1060 1040 1190 mA 3)4) IDD4W 460 540 680 760 770 860 960 1100 1080 1230 mA 3) IDD5 580 760 1160 1520 1310 1710 1440 1860 620 2090 mA 3) IDD6 6 20 13 40 14 45 26 80 29 90 mA 5) IDD7 840 1000 1560 1840 1760 2070 1840 2180 2070 2450 mA 3)4) 1) DRAM component currents only 2) Test condition for maximum values: VDD = 2.7 V, TA = 10 °C 3) The module IDDx values are calculated from the component IDDx data sheet values as: m × IDDx[component] + n × IDD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules 4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions 5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) × IDDx[component] Rev. 1.21, 2006-09 03292006-RA8T-MSZL 24 Internet Data Sheet HYS[64/72]D[16/32/128]3xxHU–[5/6]–C Unbuffered DDR SDRAM Modules TABLE 16 Product Type HYS64D32301HU–6–C HYS64D64300HU–6–C HYS72D64300HU–6–C HYS64D128320HU–6–C HYS72D128320HU–6–C IDD Specification for HYS[64/72]D[32/64/128]3xxHU–6–C Organization 256MB 512MB 512MB 1GB 1GB ×64 ×64 ×72 ×64 ×72 1 Rank 1 Rank 1 Rank 2 Ranks 2 Ranks –6 –6 –6 –6 –6 Unit Note 1)2) Symbol Typ. Max. Typ. Max. Typ. Max. Typ. Max. Typ. Max. IDD0 280 340 480 560 540 630 740 860 830 960 mA 3) IDD1 320 380 520 640 590 720 780 940 870 1050 mA 3)4) IDD2P 4 18 9 37 10 41 18 74 20 83 mA 5) IDD2F 80 100 170 200 190 230 340 400 380 450 mA 5) IDD2Q 60 90 120 180 140 200 240 350 270 400 mA 5) IDD3P 40 60 90 120 100 140 180 240 200 270 mA 5) IDD3N 130 160 260 300 290 330 510 590 580 670 mA 5) IDD4R 380 460 560 680 630 770 820 980 920 1100 mA 3)4) IDD4W 400 480 600 720 680 810 860 1020 960 1140 mA 3) IDD5 520 700 1040 1400 1170 1580 1300 1700 1460 1910 mA 3) IDD6 6.4 20 12.8 40 14.4 45 25.6 80 28.8 90 mA 5) IDD7 760 920 1400 1640 1580 1850 1660 1940 1860 2180 mA 3)4) 1) DRAM component currents only 2) Test condition for maximum values: VDD = 2.6 V, TA = 10 °C 3) The module IDDx values are calculated from the component IDDx data sheet values as: m × IDDx[component] + n × IDD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules 4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions 5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) × IDDx[component] Rev. 1.21, 2006-09 03292006-RA8T-MSZL 25 Internet Data Sheet HYS[64/72]D[16/32/128]3xxHU–[5/6]–C Unbuffered DDR SDRAM Modules 3.3 AC Characteristics TABLE 17 AC Timing - Absolute Specifications for PC3200 and PC2700 Parameter Symbol –5 –6 DDR400B DDR333 Min. Max. Min. Max. Unit Note/ Test Condition 1) DQ output access time from CK/CK tAC –0.7 +0.5 –0.7 +0.7 ns 2)3)4)5) CK high-level width tCH 0.45 0.55 0.45 0.55 tCK 2)3)4)5) Clock cycle time tCK 5 8 6 12 ns CL = 3.0 2)3)4)5) 6 12 6 12 ns CL = 2.5 2)3)4)5) 7.5 12 7.5 12 ns CL = 2.0 2)3)4)5) 0.55 0.45 0.55 tCK 2)3)4)5) tCK 2)3)4)5)6) CK low-level width tCL 0.45 Auto precharge write recovery + precharge time tDAL (tWR/tCK) + (tRP/tCK) DQ and DM input hold time tDH 0.4 — 0.45 — ns 2)3)4)5) DQ and DM input pulse width (each input) tDIPW 1.75 — 1.75 — ns 2)3)4)5)6) DQS output access time from CK/CK tDQSCK –0.5 +0.5 –0.6 +0.6 ns 2)3)4)5) DQS input low (high) pulse width tDQSL,H (write cycle) 0.35 — 0.35 — tCK 2)3)4)5) DQS-DQ skew (DQS and associated DQ signals) tDQSQ — +0.40 — +0.45 ns TSOPII 2)3)4)5) Write command to 1st DQS latching transition tDQSS 0.72 1.25 0.75 1.25 tCK 2)3)4)5) DQ and DM input setup time tDS 0.4 — 0.45 — ns 2)3)4)5) DQS falling edge hold time from CK (write cycle) tDSH 0.2 — 0.2 — tCK 2)3)4)5) DQS falling edge to CK setup time (write cycle) tDSS 0.2 — 0.2 — tCK 2)3)4)5) Clock Half Period tHP min. (tCL, tCH) — min. (tCL, tCH) — ns 2)3)4)5) Data-out high-impedance time from CK/CK tHZ +0.7 –0.7 +0.7 ns 2)3)4)5)7) Address and control input hold time tIH — 0.75 — ns fast slew rate 0.6 3)4)5)6)8) 0.7 — 0.8 — ns slow slew rate 3)4)5)6)8) Control and Addr. input pulse width (each input) Rev. 1.21, 2006-09 03292006-RA8T-MSZL tIPW 2.2 — 26 2.2 — ns 2)3)4)5)9) Internet Data Sheet HYS[64/72]D[16/32/128]3xxHU–[5/6]–C Unbuffered DDR SDRAM Modules Parameter Address and control input setup time Symbol tIS –5 –6 DDR400B DDR333 Min. Max. Min. Max. 0.6 — 0.75 — Unit Note/ Test Condition 1) ns fast slew rate 3)4)5)6)10) 0.7 — 0.8 — ns slow slew rate 3)4)5)6)10) Data-out low-impedance time from CK/CK tLZ –0.7 +0.7 –0.7 +0.7 ns 2)3)4)5)7) Mode register set command cycle time tMRD 2 — 2 — tCK 2)3)4)5) DQ/DQS output hold time tQH tHP – tQHS — tHP – tQHS — ns 2)3)4)5) Data hold skew factor tQHS — +0.50 — +0.55 ns TSOPII 2)3)4)5) Active to Autoprecharge delay tRAP tRCD — tRCD — ns 2)3)4)5) Active to Precharge command tRAS 40 70E+3 42 70E+3 ns 2)3)4)5) Active to Active/Auto-refresh command period tRC 55 — 60 — ns 2)3)4)5) Active to Read or Write delay tRCD 15 — 18 — ns 2)3)4)5) Average Periodic Refresh Interval tREFI — 7.8 — 7.8 µs 2)3)4)5)8) Auto-refresh to Active/Autorefresh command period tRFC 65 — 72 — ns 2)3)4)5) Precharge command period tRP 15 — 18 — ns 2)3)4)5) Read preamble tRPRE 0.9 1.1 0.9 1.1 tCK 2)3)4)5) Read postamble tRPST 0.40 0.60 0.40 0.60 tCK 2)3)4)5) 2)3)4)5) Active bank A to Active bank B command tRRD 10 — 12 — ns Write preamble tWPRE 0.25 — 0.25 — tCK 2)3)4)5) Write preamble setup time tWPRES 0 — 0 — ns 2)3)4)5)11) Write postamble tWPST 0.40 0.60 0.40 0.60 tCK 2)3)4)5)12) Write recovery time tWR 15 — 15 — ns 2)3)4)5) Internal write to read command delay tWTR 2 — 1 — tCK 2)3)4)5) Exit self-refresh to non-read command tXSNR 75 — 75 — ns 2)3)4)5) Exit self-refresh to read command tXSRD 200 — 200 — tCK 2)3)4)5) 1) 0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V (DDR333); VDDQ = 2.6 V ± 0.1 V, VDD = +2.6 V ± 0.1 V (DDR400) 2) Input slew rate ≥ 1 V/ns for DDR400, DDR333 3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals other than CK/CK, is VREF. CK/CK slew rate are ≥ 1.0 V/ns. 4) Inputs are not recognized as valid until VREF stabilizes. 5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT. 6) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time. 7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). Rev. 1.21, 2006-09 03292006-RA8T-MSZL 27 Internet Data Sheet HYS[64/72]D[16/32/128]3xxHU–[5/6]–C Unbuffered DDR SDRAM Modules 8) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device. 9) These parameters guarantee device timing, but they are not necessarily tested on each device. 10) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured between VOH(ac) and VOL(ac). 11) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 12) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. Rev. 1.21, 2006-09 03292006-RA8T-MSZL 28 Internet Data Sheet HYS[64/72]D[16/32/128]3xxHU–[5/6]–C Unbuffered DDR SDRAM Modules 4 SPD Codes This chapter lists all hexadecimal byte values stored in the EEPROM of the products described in this data sheet. SPD stands for serial presence detect. All values with XX in the table are module specific bytes which are defined during production. List of SPD Code Tables • Table 18 “SPD Codes for HYS64D32301HU–[5/6]–C” on Page 29 • Table 19 “SPD Codes for HYS[72/64]D64300HU–[5/6]–C” on Page 32 • Table 20 “SPD Codes for HYS[64/72]D128320HU–[5/6]–C” on Page 36 TABLE 18 SPD Codes for HYS64D32301HU–[5/6]–C Product Type HYS64D32301HU–5–C HYS64D32301HU–6–C Organization 256MB 256MB ×64 ×64 1 Rank (×16) 1 Rank (×16) Label Code PC3200U–30331 PC2700U–25331 JEDEC SPD Revision Rev. 1.0 Rev. 1.0 HEX HEX Byte# Description 2 0 Programmed SPD Bytes in E PROM 80 80 1 Total number of Bytes in E2PROM 08 08 2 Memory Type (DDR = 07h) 07 07 3 Number of Row Addresses 0D 0D 4 Number of Column Addresses 0A 0A 5 Number of DIMM Ranks 01 01 6 Data Width (LSB) 40 40 7 Data Width (MSB) 00 00 8 Interface Voltage Levels 04 04 9 tCK @ CLmax (Byte 18) [ns] 50 60 10 tAC SDRAM @ CLmax (Byte 18) [ns] 70 70 11 Error Correction Support 00 00 12 Refresh Rate 82 82 13 Primary SDRAM Width 10 10 14 Error Checking SDRAM Width 00 00 15 tCCD [cycles] 01 01 16 Burst Length Supported 0E 0E 17 Number of Banks on SDRAM Device 04 04 18 CAS Latency 1C 0C 19 CS Latency 01 01 Rev. 1.21, 2006-09 03292006-RA8T-MSZL 29 Internet Data Sheet HYS[64/72]D[16/32/128]3xxHU–[5/6]–C Unbuffered DDR SDRAM Modules Product Type HYS64D32301HU–5–C HYS64D32301HU–6–C Organization 256MB 256MB ×64 ×64 1 Rank (×16) 1 Rank (×16) Label Code PC3200U–30331 PC2700U–25331 JEDEC SPD Revision Rev. 1.0 Rev. 1.0 Byte# Description HEX HEX 20 Write Latency 02 02 21 DIMM Attributes 20 20 22 Component Attributes C1 C1 23 tCK @ CLmax -0.5 (Byte 18) [ns] 60 75 24 tAC SDRAM @ CLmax -0.5 [ns] 70 70 25 tCK @ CLmax -1 (Byte 18) [ns] 75 00 26 tAC SDRAM @ CLmax -1 [ns] 70 00 27 tRPmin [ns] 3C 48 28 tRRDmin [ns] 28 30 29 tRCDmin [ns] 3C 48 30 tRASmin [ns] 28 2A 31 Module Density per Rank 40 40 32 tAS, tCS [ns] 60 75 33 tAH, tCH [ns] 60 75 34 tDS [ns] 40 45 35 tDH [ns] 40 45 36 - 40 Not used 00 00 41 tRCmin [ns] 37 3C 42 tRFCmin [ns] 41 48 43 tCKmax [ns] 28 30 44 tDQSQmax [ns] 28 2D 45 tQHSmax [ns] 50 55 46 not used 00 00 47 DIMM PCB Height 01 01 48 - 61 Not used 00 00 62 SPD Revision 10 10 63 Checksum of Byte 0-62 76 1A 64 Manufacturer’s JEDEC ID Code (1) 7F 7F 65 Manufacturer’s JEDEC ID Code (2) 7F 7F 66 Manufacturer’s JEDEC ID Code (3) 7F 7F 67 Manufacturer’s JEDEC ID Code (4) 7F 7F 68 Manufacturer’s JEDEC ID Code (5) 7F 7F 69 Manufacturer’s JEDEC ID Code (6) 51 51 Rev. 1.21, 2006-09 03292006-RA8T-MSZL 30 Internet Data Sheet HYS[64/72]D[16/32/128]3xxHU–[5/6]–C Unbuffered DDR SDRAM Modules Product Type HYS64D32301HU–5–C HYS64D32301HU–6–C Organization 256MB 256MB ×64 ×64 1 Rank (×16) 1 Rank (×16) Label Code PC3200U–30331 PC2700U–25331 JEDEC SPD Revision Rev. 1.0 Rev. 1.0 Byte# Description HEX HEX 70 Manufacturer’s JEDEC ID Code (7) 00 00 71 Manufacturer’s JEDEC ID Code (8) 00 00 72 Module Manufacturer Location xx xx 73 Part Number, Char 1 36 36 74 Part Number, Char 2 34 34 75 Part Number, Char 3 44 44 76 Part Number, Char 4 33 33 77 Part Number, Char 5 32 32 78 Part Number, Char 6 33 33 79 Part Number, Char 7 30 30 80 Part Number, Char 8 31 31 81 Part Number, Char 9 48 48 82 Part Number, Char 10 55 55 83 Part Number, Char 11 35 36 84 Part Number, Char 12 43 43 85 Part Number, Char 13 20 20 86 Part Number, Char 14 20 20 87 Part Number, Char 15 20 20 88 Part Number, Char 16 20 20 89 Part Number, Char 17 20 20 90 Part Number, Char 18 20 20 91 Module Revision Code 1x 1x 92 Test Program Revision Code xx xx 93 Module Manufacturing Date Year xx xx 94 Module Manufacturing Date Week xx xx 95 - 98 Module Serial Number xx xx 00 00 99 - 127 Not used Rev. 1.21, 2006-09 03292006-RA8T-MSZL 31 Internet Data Sheet HYS[64/72]D[16/32/128]3xxHU–[5/6]–C Unbuffered DDR SDRAM Modules TABLE 19 Product Type HYS64D64300HU–5–C HYS64D64300HU–6–C HYS72D64300HU–5–C HYS72D64300HU–6–C SPD Codes for HYS[72/64]D64300HU–[5/6]–C Organization 512MB 512MB 512MB 512MB ×64 ×64 ×72 ×72 1 Rank (×8) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8) Label Code PC3200U– 30331 PC2700U– 25331 PC3200U– 30331 PC2700U– 25331 JEDEC SPD Revision Rev. 1.0 Rev. 1.0 Rev. 1.0 Rev. 1.0 HEX HEX HEX HEX 80 80 80 80 Byte# 0 Description 2 Programmed SPD Bytes in E PROM 1 2 Total number of Bytes in E PROM 08 08 08 08 2 Memory Type (DDR = 07h) 07 07 07 07 3 Number of Row Addresses 0D 0D 0D 0D 4 Number of Column Addresses 0B 0B 0B 0B 5 Number of DIMM Ranks 01 01 01 01 6 Data Width (LSB) 40 40 48 48 7 Data Width (MSB) 00 00 00 00 8 Interface Voltage Levels 04 04 04 04 9 tCK @ CLmax (Byte 18) [ns] 50 60 50 60 10 tAC SDRAM @ CLmax (Byte 18) [ns] 70 70 70 70 11 Error Correction Support 00 00 02 02 12 Refresh Rate 82 82 82 82 13 Primary SDRAM Width 08 08 08 08 14 Error Checking SDRAM Width 00 00 08 08 15 tCCD [cycles] 01 01 01 01 16 Burst Length Supported 0E 0E 0E 0E 17 Number of Banks on SDRAM Device 04 04 04 04 18 CAS Latency 1C 0C 1C 0C 19 CS Latency 01 01 01 01 20 Write Latency 02 02 02 02 21 DIMM Attributes 20 20 20 20 22 Component Attributes C1 C1 C1 C1 23 tCK @ CLmax -0.5 (Byte 18) [ns] 60 75 60 75 Rev. 1.21, 2006-09 03292006-RA8T-MSZL 32 Internet Data Sheet Product Type HYS64D64300HU–5–C HYS64D64300HU–6–C HYS72D64300HU–5–C HYS72D64300HU–6–C HYS[64/72]D[16/32/128]3xxHU–[5/6]–C Unbuffered DDR SDRAM Modules Organization 512MB 512MB 512MB 512MB ×64 ×64 ×72 ×72 1 Rank (×8) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8) Label Code PC3200U– 30331 PC2700U– 25331 PC3200U– 30331 PC2700U– 25331 JEDEC SPD Revision Rev. 1.0 Rev. 1.0 Rev. 1.0 Rev. 1.0 Byte# Description HEX HEX HEX HEX 24 tAC SDRAM @ CLmax -0.5 [ns] 70 70 70 70 25 tCK @ CLmax -1 (Byte 18) [ns] 75 00 75 00 26 tAC SDRAM @ CLmax -1 [ns] 70 00 70 00 27 tRPmin [ns] 3C 48 3C 48 28 tRRDmin [ns] 28 30 28 30 29 tRCDmin [ns] 3C 48 3C 48 30 tRASmin [ns] 28 2A 28 2A 31 Module Density per Rank 80 80 80 80 32 tAS, tCS [ns] 60 75 60 75 33 tAH, tCH [ns] 60 75 60 75 34 tDS [ns] 40 45 40 45 35 tDH [ns] 40 45 40 45 36 - 40 Not used 00 00 00 00 41 tRCmin [ns] 37 3C 37 3C 42 tRFCmin [ns] 41 48 41 48 43 tCKmax [ns] 28 30 28 30 44 tDQSQmax [ns] 28 2D 28 2D 45 tQHSmax [ns] 50 55 50 55 46 not used 00 00 00 00 47 DIMM PCB Height 01 01 01 01 48 - 61 Not used 00 00 00 00 62 SPD Revision 10 10 10 10 63 Checksum of Byte 0-62 AF 53 C1 65 64 Manufacturer’s JEDEC ID Code (1) 7F 7F 7F 7F 65 Manufacturer’s JEDEC ID Code (2) 7F 7F 7F 7F 66 Manufacturer’s JEDEC ID Code (3) 7F 7F 7F 7F Rev. 1.21, 2006-09 03292006-RA8T-MSZL 33 Internet Data Sheet Product Type HYS64D64300HU–5–C HYS64D64300HU–6–C HYS72D64300HU–5–C HYS72D64300HU–6–C HYS[64/72]D[16/32/128]3xxHU–[5/6]–C Unbuffered DDR SDRAM Modules Organization 512MB 512MB 512MB 512MB ×64 ×64 ×72 ×72 1 Rank (×8) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8) Label Code PC3200U– 30331 PC2700U– 25331 PC3200U– 30331 PC2700U– 25331 JEDEC SPD Revision Rev. 1.0 Rev. 1.0 Rev. 1.0 Rev. 1.0 Byte# Description HEX HEX HEX HEX 67 Manufacturer’s JEDEC ID Code (4) 7F 7F 7F 7F 68 Manufacturer’s JEDEC ID Code (5) 7F 7F 7F 7F 69 Manufacturer’s JEDEC ID Code (6) 51 51 51 51 70 Manufacturer’s JEDEC ID Code (7) 00 00 00 00 71 Manufacturer’s JEDEC ID Code (8) 00 00 00 00 72 Module Manufacturer Location xx xx xx xx 73 Part Number, Char 1 36 36 37 37 74 Part Number, Char 2 34 34 32 32 75 Part Number, Char 3 44 44 44 44 76 Part Number, Char 4 36 36 36 36 77 Part Number, Char 5 34 34 34 34 78 Part Number, Char 6 33 33 33 33 79 Part Number, Char 7 30 30 30 30 80 Part Number, Char 8 30 30 30 30 81 Part Number, Char 9 48 48 48 48 82 Part Number, Char 10 55 55 55 55 83 Part Number, Char 11 35 36 35 36 84 Part Number, Char 12 43 43 43 43 85 Part Number, Char 13 20 20 20 20 86 Part Number, Char 14 20 20 20 20 87 Part Number, Char 15 20 20 20 20 88 Part Number, Char 16 20 20 20 20 89 Part Number, Char 17 20 20 20 20 90 Part Number, Char 18 20 20 20 20 91 Module Revision Code 1x 1x 1x 1x 92 Test Program Revision Code xx xx xx xx Rev. 1.21, 2006-09 03292006-RA8T-MSZL 34 Internet Data Sheet Product Type HYS64D64300HU–5–C HYS64D64300HU–6–C HYS72D64300HU–5–C HYS72D64300HU–6–C HYS[64/72]D[16/32/128]3xxHU–[5/6]–C Unbuffered DDR SDRAM Modules Organization 512MB 512MB 512MB 512MB ×64 ×64 ×72 ×72 1 Rank (×8) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8) Label Code PC3200U– 30331 PC2700U– 25331 PC3200U– 30331 PC2700U– 25331 JEDEC SPD Revision Rev. 1.0 Rev. 1.0 Rev. 1.0 Rev. 1.0 Byte# Description HEX HEX HEX HEX 93 Module Manufacturing Date Year xx xx xx xx 94 Module Manufacturing Date Week xx xx xx xx 95 - 98 Module Serial Number xx xx xx xx 00 00 00 00 99 - 127 Not used Rev. 1.21, 2006-09 03292006-RA8T-MSZL 35 Internet Data Sheet HYS[64/72]D[16/32/128]3xxHU–[5/6]–C Unbuffered DDR SDRAM Modules TABLE 20 Product Type HYS64D128320HU–5–C HYS64D128320HU–6–C HYS72D128320HU–5–C HYS72D128320HU–6–C SPD Codes for HYS[64/72]D128320HU–[5/6]–C Organization 1 GByte 1 GByte 1 GByte 1 GByte ×64 ×64 ×72 ×72 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) Label Code PC3200U– 30331 PC2700U– 25331 PC3200U– 30331 PC2700U– 25331 JEDEC SPD Revision Rev. 1.0 Rev. 1.0 Rev. 1.0 Rev. 1.0 Byte# Description HEX HEX HEX HEX 0 Programmed SPD Bytes in E2PROM 80 80 80 80 2 Total number of Bytes in E PROM 08 08 08 08 2 Memory Type (DDR = 07h) 07 07 07 07 3 Number of Row Addresses 0D 0D 0D 0D 4 Number of Column Addresses 0B 0B 0B 0B 5 Number of DIMM Ranks 02 02 02 02 6 Data Width (LSB) 40 40 48 48 7 Data Width (MSB) 00 00 00 00 8 Interface Voltage Levels 04 04 04 04 9 tCK @ CLmax (Byte 18) [ns] 50 60 50 60 10 tAC SDRAM @ CLmax (Byte 18) [ns] 70 70 70 70 11 Error Correction Support 00 00 02 02 12 Refresh Rate 82 82 82 82 13 Primary SDRAM Width 08 08 08 08 14 Error Checking SDRAM Width 00 00 08 08 1 15 tCCD [cycles] 01 01 01 01 16 Burst Length Supported 0E 0E 0E 0E 17 Number of Banks on SDRAM Device 04 04 04 04 18 CAS Latency 1C 0C 1C 0C 19 CS Latency 01 01 01 01 20 Write Latency 02 02 02 02 21 DIMM Attributes 20 20 20 20 22 Component Attributes C1 C1 C1 C1 Rev. 1.21, 2006-09 03292006-RA8T-MSZL 36 Internet Data Sheet Product Type HYS64D128320HU–5–C HYS64D128320HU–6–C HYS72D128320HU–5–C HYS72D128320HU–6–C HYS[64/72]D[16/32/128]3xxHU–[5/6]–C Unbuffered DDR SDRAM Modules Organization 1 GByte 1 GByte 1 GByte 1 GByte ×64 ×64 ×72 ×72 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) Label Code PC3200U– 30331 PC2700U– 25331 PC3200U– 30331 PC2700U– 25331 JEDEC SPD Revision Rev. 1.0 Rev. 1.0 Rev. 1.0 Rev. 1.0 Byte# Description HEX HEX HEX HEX 23 tCK @ CLmax -0.5 (Byte 18) [ns] 60 75 60 75 24 tAC SDRAM @ CLmax -0.5 [ns] 70 70 70 70 25 tCK @ CLmax -1 (Byte 18) [ns] 75 00 75 00 26 tAC SDRAM @ CLmax -1 [ns] 70 00 70 00 27 tRPmin [ns] 3C 48 3C 48 28 tRRDmin [ns] 28 30 28 30 29 tRCDmin [ns] 3C 48 3C 48 30 tRASmin [ns] 28 2A 28 2A 31 Module Density per Rank 80 80 80 80 32 tAS, tCS [ns] 60 75 60 75 33 tAH, tCH [ns] 60 75 60 75 34 tDS [ns] 40 45 40 45 35 tDH [ns] 40 45 40 45 36 - 40 Not used 00 00 00 00 41 tRCmin [ns] 37 3C 37 3C 42 tRFCmin [ns] 41 48 41 48 43 tCKmax [ns] 28 30 28 30 44 tDQSQmax [ns] 28 2D 28 2D 45 tQHSmax [ns] 50 55 50 55 46 not used 00 00 00 00 47 DIMM PCB Height 01 01 01 01 48 - 61 Not used 00 00 00 00 62 SPD Revision 10 10 10 10 63 Checksum of Byte 0-62 B0 54 C2 66 64 Manufacturer’s JEDEC ID Code (1) 7F 7F 7F 7F 65 Manufacturer’s JEDEC ID Code (2) 7F 7F 7F 7F Rev. 1.21, 2006-09 03292006-RA8T-MSZL 37 Internet Data Sheet Product Type HYS64D128320HU–5–C HYS64D128320HU–6–C HYS72D128320HU–5–C HYS72D128320HU–6–C HYS[64/72]D[16/32/128]3xxHU–[5/6]–C Unbuffered DDR SDRAM Modules Organization 1 GByte 1 GByte 1 GByte 1 GByte ×64 ×64 ×72 ×72 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) Label Code PC3200U– 30331 PC2700U– 25331 PC3200U– 30331 PC2700U– 25331 JEDEC SPD Revision Rev. 1.0 Rev. 1.0 Rev. 1.0 Rev. 1.0 Byte# Description HEX HEX HEX HEX 66 Manufacturer’s JEDEC ID Code (3) 7F 7F 7F 7F 67 Manufacturer’s JEDEC ID Code (4) 7F 7F 7F 7F 68 Manufacturer’s JEDEC ID Code (5) 7F 7F 7F 7F 69 Manufacturer’s JEDEC ID Code (6) 51 51 51 51 70 Manufacturer’s JEDEC ID Code (7) 00 00 00 00 71 Manufacturer’s JEDEC ID Code (8) 00 00 00 00 72 Module Manufacturer Location xx xx xx xx 73 Part Number, Char 1 36 36 37 37 74 Part Number, Char 2 34 34 32 32 75 Part Number, Char 3 44 44 44 44 76 Part Number, Char 4 31 31 31 31 77 Part Number, Char 5 32 32 32 32 78 Part Number, Char 6 38 38 38 38 79 Part Number, Char 7 33 33 33 33 80 Part Number, Char 8 32 32 32 32 81 Part Number, Char 9 30 30 30 30 82 Part Number, Char 10 48 48 48 48 83 Part Number, Char 11 55 55 55 55 84 Part Number, Char 12 35 36 35 36 85 Part Number, Char 13 43 43 43 43 86 Part Number, Char 14 20 20 20 20 87 Part Number, Char 15 20 20 20 20 88 Part Number, Char 16 20 20 20 20 89 Part Number, Char 17 20 20 20 20 90 Part Number, Char 18 20 20 20 20 91 Module Revision Code 1x 1x 1x 1x Rev. 1.21, 2006-09 03292006-RA8T-MSZL 38 Internet Data Sheet Product Type HYS64D128320HU–5–C HYS64D128320HU–6–C HYS72D128320HU–5–C HYS72D128320HU–6–C HYS[64/72]D[16/32/128]3xxHU–[5/6]–C Unbuffered DDR SDRAM Modules Organization 1 GByte 1 GByte 1 GByte 1 GByte ×64 ×64 ×72 ×72 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) Label Code PC3200U– 30331 PC2700U– 25331 PC3200U– 30331 PC2700U– 25331 JEDEC SPD Revision Rev. 1.0 Rev. 1.0 Rev. 1.0 Rev. 1.0 Byte# Description HEX HEX HEX HEX 92 Test Program Revision Code xx xx xx xx 93 Module Manufacturing Date Year xx xx xx xx 94 Module Manufacturing Date Week xx xx xx xx 95 - 98 Module Serial Number xx xx xx xx 00 00 00 00 99 - 127 Not used Rev. 1.21, 2006-09 03292006-RA8T-MSZL 39 Internet Data Sheet HYS[64/72]D[16/32/128]3xxHU–[5/6]–C Unbuffered DDR SDRAM Modules 5 Package Outlines Package Outline for HYS64D32301HU–[5/6]–C FIGURE 8 Package Outline UDIMM Raw Card C (L-DIM-184-18) 0.1 A B C 133.35 0.15 A B C 128.95 2.7 MAX. A 31.75 ±0.13 4 ±0.1 1) 1 2.36 ±0.1 ø0.1 A B C 92 6.62 B 2.175 0.4 6.35 64.77 C 1.27 ±0.1 49.53 0.1 A B C 184 3 MIN. 0.2 2.5 ±0.2 Detail of contacts 1.27 1 ±0.05 0.1 A B C 1) On ECC modules only Burr max. 0.4 allowed Rev. 1.21, 2006-09 03292006-RA8T-MSZL 40 17.8 1.8 ±0.1 93 10 3.8 ±0.13 95 x 1.27 = 120.65 Internet Data Sheet HYS[64/72]D[16/32/128]3xxHU–[5/6]–C Unbuffered DDR SDRAM Modules Package Outline for HYS64D64300HU–[5/6]–C FIGURE 9 Package Outline UDIMM Raw Card A (L-DIM-184-32) 0.1 A B C 133.35 0.15 A B C 128.95 2.7 MAX. 31.75 ±0.13 4 ±0.1 A 1 2.36 ±0.1 ø0.1 A B C 92 6.62 B 2.175 0.4 6.35 64.77 C 1.27 ±0.1 49.53 0.1 A B C 93 184 3 MIN. 0.2 2.5 ±0.2 Detail of contacts 1.27 1 ±0.05 0.1 A B C Burr max. 0.4 allowed Rev. 1.21, 2006-09 03292006-RA8T-MSZL 41 17.8 1.8 ±0.1 10 3.8 ±0.13 95 x 1.27 = 120.65 Internet Data Sheet HYS[64/72]D[16/32/128]3xxHU–[5/6]–C Unbuffered DDR SDRAM Modules Package Outline for HYS72D64300HU–[5/6]–C FIGURE 10 Package Outline UDIMM Raw Card A (L-DIM-184-30) 0.1 A B C 133.35 0.15 A B C 128.95 2.7 MAX. A 31.75 ±0.13 4 ±0.1 1) 1 2.36 ±0.1 ø0.1 A B C 92 6.62 B 2.175 0.4 6.35 64.77 C 1.27 ±0.1 49.53 0.1 A B C 93 184 3 MIN. 0.2 2.5 ±0.2 Detail of contacts 1.27 1 ±0.05 0.1 A B C 1) On ECC modules only Burr max. 0.4 allowed Rev. 1.21, 2006-09 03292006-RA8T-MSZL 42 17.8 1.8 ±0.1 10 3.8 ±0.13 95 x 1.27 = 120.65 Internet Data Sheet HYS[64/72]D[16/32/128]3xxHU–[5/6]–C Unbuffered DDR SDRAM Modules Package Outline for HYS[64/72]D128320HU–[5/6]–C FIGURE 11 Package Outline UDIMM Raw Card B (L-DIM-184-31) 0.1 A B C 133.35 0.15 A B C 128.95 4 MAX. A 31.75 ±0.13 4 ±0.1 1) 1 2.36 ±0.1 ø0.1 A B C 92 6.62 B C 2.175 0.4 6.35 64.77 1.27 ±0.1 49.53 0.1 A B C 93 184 3 MIN. 0.2 2.5 ±0.2 Detail of contacts 1.27 1 ±0.05 0.1 A B C 1) On ECC modules only Burr max. 0.4 allowed Rev. 1.21, 2006-09 03292006-RA8T-MSZL 43 17.8 1.8 ±0.1 10 3.8 ±0.13 95 x 1.27 = 120.65 Internet Data Sheet HYS[64/72]D[16/32/128]3xxHU–[5/6]–C Unbuffered DDR SDRAM Modules Table of Contents 1 1.1 1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 3.1 3.2 3.3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDD Specification and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 16 16 18 21 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Rev. 1.21, 2006-09 03292006-RA8T-MSZL 39 Internet Data Sheet Edition 2006-09 Published by Qimonda AG Gustav-Heinemann-Ring 212 D-81739 München, Germany © Qimonda AG 2006. All Rights Reserved. Legal Disclaimer The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics (“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office. Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Qimonda Office. Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. www.qimonda.com