I90135 Product Data Sheet Version 1.2 (June 1999) I90135-ADSL Digital Chip Features ! ! ! ANSI T1.413 Issue 2 standard DMT modem with embedded, bypassable, ATM framer Byte interface or standard Utopia level 1 and level 2 ATM interfaces Main functions include: Receive Direction: - Rotor and adaptive frequency domain equalizing - Demapping of DMT carriers into a digital bitstream, including 4D trellis coding - Error and noise monitoring on individual carriers and pilot tones - Reed-Solomon decoding and deinterleaving - ADSL deframing - ATM cell-specific deframing (can be bypassed) - 144-pin PQFP package - Power consumption 1 watt at 3.3V General Description ITeX's I90135 is the DMT modem and ATM Framer of the Apollo series rate adaptive ADSL chipset. The I90135 is intended to be used in combination with I80134 analog front end. In addition, the control function of the chipset can be performed on a dedicated external controller (see figure 1.1) or on host/control software eliminating the need for a microcontroller (see figure 1.2). The I90135 may be used in both ATU-C (central office) and ATU-R (remote) applications. The chip provides both a cellbased UTOPIA level 1 and 2 ATM data interface to the host and a non-ATM synchronous bit stream. The I90135 performs the DMT modulation, demodulation, Reed-Solomon encoding, bit interleaving, and 4D trellis coding. The I90135 is in a 144-pin PQFP package. Transmit Direction: - ATM cell-specific framing - ADSL framing - Reed-Solomon encoding - Mapping of digital bitstream onto DMT carriers - Rotor and frequency domain gain correction Integrated Telecom Express, Inc. 1 I90135 Product Data Sheet Version 1.2 (June 1999) UTOPIA 1 & 2 interface I90135 DMT Modem and ATM Framer ATM I80134 Analog Front End Hybrid Line POTS Splitter A/B Microprocessor or dedicated controller STM bitstream FLASH RAM Figure 1.1: General Block Diagram AFE PCI ADSL Controller Software I90188 PCI Controller Utopia I90135 DMT Modem and ATM Framer I80134 Analog Front End Host Based POTS Splitter Line A/B Figure 1.2: General Block Diagram (Controllerless Configuration) Integrated Telecom Express, Inc. 2 I90135 Product Data Sheet Version 1.2 (June 1999) Block Diagram Test Signals Clock Test Module Data Symbol Timing Unit VCXO AFE Interface DSP Front-end FFT/ IFFT Rotor Trellis Coding Generic TC Mapper/ Demapper Reed/ Solomon Reset Reset Figure 2: I90135 Block Diagram Controller Bus The following essential describes the sequence of actions for the receive direction, corresponding functions for the transmit direction are readily derived. The DSP front end contains four parts in the receive direction: the input selector, the analog front end interface, the decimator and the time equalizer. The input selector Integrated Telecom Express, Inc. Utopia Controller Interface Introduction DSP Front End ATM Specific TC Interface Module SLAP General Purpose I/Os is used internally to enable test loopbacks inside the chip. The analog front end interface transfers 16-bit word, multiplexed on four input/output signals. As a result, four dock cycles are needed to transfer one word. The decimator receives the 16-bit samples at 8.8 MHz (as sent by the analog front end chip) and reduces this rate to 2.2 MHz. 3 I90135 Product Data Sheet Version 1.2 (June 1999) The Tme Equalizer (TEQ) module is an FIR filter with programmable coefficients. Its main purpose is to reduce the effect of Inter-Symbol Interferences (ISI) by shortening the channel impulse response. Both the decimator and TEQ can be bypassed. the FFT is followed by a Frequency Domain Equalizer (FEQ) and a rotor (phase shifter). Clipping is a statistical process limiting the amplitude of the output signal, optimizing the dynamic range of the AFE. The interpolator receives data at 2.2 MHz and generates samples at a rate of 8.8 MHz. In the TX path, the IFFT transforms the DMT symbol generated in the frequency domain by the mapper into a time domain representation. The IFFT block is proceed by a fne tune gain and a rotor stage, allowing for a compensation of the possible frequency mismatch between the master clock frequency and the transmitter clock frequency (which may be locked to another reference). The FFT module is a slave DSP engine controlled by the transceiver controller. It works off line and communicates with the other blocks via buffers controlled by the DSTU block. The DSP executes a program stored in a RAM area, a very flexible implementation open for future enhancements. DMT Modem DPLL In the transmit direction, the DSP front end includes: sidelobe filtering, clipping, delay equalization, and interpolation. The sidelobe filtering and delay equalization are implemented by IIR filters, reducing the effect of echo in FDM systems. This computational module is a programmable DSP unit. Its instruction set enables functions like FFT, IFFT, scaling, rotor, and Frequency Equalization (FEQ). This block implements the core of the DMT algorithm as specified in ANSI T1.413. In the RX path, the 51 2-point FFT transforms the time domain DMT symbol into a frequency domain representation, which can be further decoded by the subsequent demapping stages. After the first stage time domain equalization and FFT block an essentially ICI (InterCarrier Interferences)-free carrier information stream has been obtained. This stream is still affected by carrier-specific channel distortion resulting in an attenuation of the signal amplitude and a rotation of the signal phase. To compensate for these effects, Integrated Telecom Express, Inc. The Digital PLL module receives a metric for the phase error of the pilot tone. In general, the clock frequencies at the transmitter and receiver do not match exactly. The phase error is filtered and integrated by a low pass filter, yielding an estimation of the frequency offset. Various processes can use this estimate to deal with the frequency mismatch. In particular, small accumulated phase error can be compensated in the frequency domain by a rotation of the received code constellation (Rotor). Larger errors are compensated in the time domain by inserting or deleting clock cycles in the sample input sequence. 4 I90135 Product Data Sheet Version 1.2 (June 1999) Mapper/Demapper, Monitor, Trellis Coding, FEQ Update constellation point (in a complex x+jy representation) which is passed to the IFFT block. The Trellis Encoder generates redundant bits to improve the robustness of the transmission, using a 4-Dimensional Trellis Coded Modulation scheme. The Monitor computes error parameters for carriers specified in the Demapper process. Those parameters can be used for updates of adaptive filters coefficient, clock phase adjustments, error detection, etc. A series of values is constantly monitored, such as signal power, pilot phase deviations, symbol erasures generation, loss of frame, etc. The demapper converts the constellation points computed by the FFT to a block of bits. This essentially consists in identifying a point in a 2D QAM constellation plane. The demapper supports trellis coded demodulation and provides a Viterbi maximum likelihood estimator. When the trellis is active, the demapper receives an indication for the most likely constellation subset to be used. In the transmit direction, the mapper performs the inverse operation, mapping a block of bits into one Pin Diagram SLT_REQ_S VSS 110 109 113 SLT_FRAME_S 111 TDI 112 TDO 117 118 116 119 114 115 VSS TRSTB 120 121 TMS VDD TESTSE 122 123 TCK GP_OUT PDOWN 124 131 132 VDD AFRXD_0 133 AFRXD_1 VDD AFTXED_0 134 135 125 126 AFTXED_1 136 AFRXD_2 AFRXD_3 VSS AFTXED_2 137 138 127 AFTXED_3 139 VSS VDD IDDQ 140 141 130 AFTXD_0 142 128 129 AFTXD_1 VSS 143 144 CLWD MCLK AFTXD_2 CTRLDATA AFTXD_3 VDD VSS 1 108 AD_0 2 107 SLT_REQ_F AD_1 AD_2 3 4 106 105 SLT_DAT_S0 SLT_DAT_S1 AFE TEST VDD VDD 5 104 SLT_DAT_F0 AD_3 AD_4 6 7 103 102 SLT_DAT_F1 VSS VSS 8 101 SLT_FRAME_F AD_5 AD_6 9 10 VDD AD_7 11 12 98 97 AD_8 13 96 SLR_VAL_S AD_9 VSS 14 15 95 94 VDD SLR_DAT_S0 AD_10 16 93 SLR_DAT_S1 AD_11 VDD 17 18 92 SLR_FRAME_S 91 VSS AD_12 19 VSS PCLK 20 21 89 88 U_TX_ADDR_0 U_TX_ADDR_1 VDD 22 87 U_TX_ADDR_2 AD_13 AD_14 23 24 86 85 VDD U_TX_ADDR_3 AD_15 25 84 U_TX_ADDR_4 VSS BE1 26 27 83 82 U_TX_DATA_0 U_TX_DATA_1 ALE 28 VDD CSB 100 SLAP_CLOCK 99 SLR_VAL_F SLAP OBC SLR_DAT_F0 SLR_DAT_F1 90 SLR_FRAME_F UTOPIA 81 VDD 29 30 80 79 U_TX_DATA_2 U_TX_DATA_3 WR_RDB 31 78 U_TX_DATA_4 RDYB OBC_TYPE 32 33 77 76 U_TX_DATA_5 VDD INTB 34 75 U_TX_DATA_6 RESETB VSS 35 36 74 73 U_TX_DATA_7 VSS 71 72 U_TXENBB VDD VSS U_RXENBB U_TXCLK U_RX_CLAV U_TX_CLAV U_TXSOC 67 66 70 69 65 VDD U_RXSOC U_RXCLK 68 64 63 U_RX_REFB U_TX_REFB 62 61 60 VDD U_RXDATA_7 VSS GP_IN_1 U_RXDATA_6 VSS 59 58 48 U_RXDATA_5 57 47 46 U_RXDATA_4 VDD VSS 45 U_RXDATA_3 56 GP_IN_0 55 U_RX_ADDR_4 44 43 U_RXDATA_2 VSS 54 42 U_RXDATA_1 53 U_RX_ADDR_3 52 U_RX_ADDR_2 41 40 U_RXDATA_0 VDD 51 U_RX_ADDR_1 39 50 U_RX_ADDR_0 49 VDD 38 37 Figure 3: Pinout (Topside View) Integrated Telecom Express, Inc. 5 I90135 Product Data Sheet Version 1.2 (June 1999) Pin Assignment and Description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Mnemonic VSS AD_0 AD_1 AD_2 VDD AD_3 AD_4 VSS AD_5 AD_6 VDD AD_7 AD_8 AD_9 VSS AD_10 AD_11 VDD AD_12 VSS PCLK VDD AD_13 AD_14 AD_15 VSS BE1 ALE Type Supply Driver BS B B B VDD VDD VDD BD8SCR BD8SCR BD8SCR B B B B B VDD VDD BD8SCR BD8SCR B B B B VDD VDD BD8SCR BD8SCR B B B B B VDD VDD VDD BD8SCR BD8SCR BD8SCR B B B B B VDD VDD BD8SCR BD8SCR B B B VDD BD8SCR B VDD IBUF I B B B VDD VDD VDD BD8SCR BD8SCR BD8SCR B B B I I VDD VDD IBUF IBUF I C 29 30 VDD CSB I VDD IBUF I 31 WR_RDB I VDD IBUF I 32 33 34 35 36 37 38 39 RDYB OBC_TYPE INTB RESETB VSS VDD U_RxData_0 U_RxData_1 OZ I-PD O I VDD VDD VDD VDD BT4CR IBUF IBUF IBUF O I O I OZ OZ VDD VDD BD8SCR BD8SCR B B Description 0 Volt GROUND Micro processor interface Address / Data 1 Address / Data 2 +3.3 Volts power supply Address / Data 3 Address / Data 4 0 Volt GROUND +3.3 Volts power supply 0 Volt GROUND +3.3 Volts power supply Integrated Telecom Express, Inc. 0 Volt GROUND Processor clock +3.3 Volts power supply 0 Volt GROUND Address [1] input Used to latch the address of the internal register to be accessed +3.3 volts power supply Chip selected to respond to bus cycle Specifies the direction of the access cycle ATC Mode Selection Requests ATC interrupts service Hard reset 0 Volt GROUND +3.3 Volts power supply UTOPIA RX Data 0 UTOPIA RX Data 1 6 I90135 Product Data Sheet Version 1.2 (June 1999) Pin 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Mnemonic VSS U_RxData_2 U_RxData_3 VDD U_RxData_4 U_RxData_5 VSS U_RxData_6 U_RxData_7 VDD U_RxADDR_0 U_RxADDR_1 U_RxADDR_2 U_RxADDR_3 VSS U_RxADDR_4 GP_IN_0 VDD GP_IN_1 VSS U_RxRefB U_TxRefB VDD U_RxCLK U_RxSOC Type Supply Driver BS OZ OZ VDD VDD BD8SCR BD8SCR B B OZ OZ VDD VDD BD8SCR BD8SCR B B OZ OZ VDD VDD BD8SCR BD8SCR B B I I I I VDD VDD VDD VDD IBUF IBUF IBUF IBUF I I I I I I-PD VDD VDD IBUF IBUFDQ I I I-PD VDD IBUFDQ I O I VDD VDD IBUF BT4CR O I I O-Z VDD VDD IBUF BD8SCR 65 66 67 68 69 U_RxCLAV U_RxENBB VSS U_TxCLK U_TxSOC O-Z I VDD VDD BD8SCR IBUF I I VDD VDD IBUF IBUF 70 71 72 73 74 75 76 77 78 79 80 81 U_TxCLAV U_TxENBB VDD VSS U_TxData_7 U_TxData_6 VDD U_TxData_5 U_TxData_4 U_TxData_3 U_TxData_2 VDD O-Z I VDD VDD BD8SCR IBUF I I VDD VDD IBUF IBUF I I I I I I VDD VDD VDD VDD IBUF IBUF IBUF IBUF I I I I Integrated Telecom Express, Inc. Description 0 Volt GROUND UTOPIA RX Data 2 UTOPIA RX Data 3 +3.3 Volts power supply UTOPIA RX Data 4 UTOPIA RX Data 5 0 Volt GROUND UTOPIA RX Data 6 UTOPIA RX Data 7 +3.3 Volts power supply UTOPIA RX Address 0 UTOPIA RX Address 1 UTOPIA RX Address 2 UTOPIA RX Address 3 0 Volt GROUND UTOPIA RX Address 4 General purpose input +3.3 Volts power supply General purpose input 1 0 Volt GROUND 8 kHz clock to ATM device 8 kHz from network VSS +3.3 Volts power supply Receive interface Utopia clock Receive interface Start of Cell indication 0 Volt GROUND Transmit interface Utopia clock Transmit interface Start of Cell indication UTOPIA TX Enable +3.3 Volts power supply 0 Volt GROUND UTOPIA TX Data 7 UTOPIA TX Data 6 +3.3 Volts power supply UTOPIA TX Data 5 UTOPIA TX Data 4 UTOPIA TX Data 3 UTOPIA TX Data 2 +3.3 Volts power supply 7 I90135 Product Data Sheet Version 1.2 (June 1999) Pin 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 Mnemonic U_TxData_1 U_TxData_0 U_TxADDR_4 U_TxADDR_3 VDD U_TxADDR_2 U_TxADDR_1 U_TxADDR_0 SLR_FRAME_F VSS SLR_FRAME_S SLR_DATA_S_1 SLR_DATA_S_0 VDD SLR_VAL_S SLR_DATA_F_1 SLR_DATA_F_0 SLR_VAL_F SLAP_CLOCK SLT_FRAME_F VSS SLT_DATA_F_1 SLT_DATA_F_0 SLT_DATA_F_1 SLT_DATA_F_0 SLT_REQ_F VDD VSS SLT_REQ_S SLT_FRAME_S Type I I I I Supply VDD VDD VDD VDD Driver IBUF IBUF IBUF IBUF BS I I I I I I I O VDD VDD VDD VDD IBUF IBUF IBUF BT4CR I I I O O O VDD VDD VDD BT4CR BT4CR BT4CR O O O O O O VDD VDD VDD VDD VDD VDD BT4CR BT4CR BT4CR BT4CR BT4CR BT4CR I I I I O VDD VDD VDD VDD VDD IBUFDQ IBUFDQ IBUFDQ IBUFDQ BT4CR O O VDD VDD BT4CR BT4CR 112 113 114 115 116 117 118 119 120 121 122 123 124 TDI TDO TMS VDD TCK VSS TRSTB TESTSE GP_OUT PDOWN VDD AFRXD_0 AFRXD_1 I-PU OZ I-PU VDD VDD VDD IBUFDQ BT4CR IBUFDQ I-PD VDD IBUFDQ I-PD I O O VDD VDD VDD VDD IBUFDQ IBUF BD8SCR BT4CR I I VDD VDD IBUF IBUF Integrated Telecom Express, Inc. none O O I I Description UTOPIA TX Data 1 UTOPIA TX Data 0 UTOPIA TX Address 4 UTOPIA TX Address 3 +3.3 Volts power supply UTOPIA TX Address 2 UTOPIA TX Address 1 UTOPIA TX Address 0 Frame Identifier Fast 0 Volt GROUND Frame Identifier Interleaved Data Interleave 1 Data Interleave 0 +3.3 Volts power supply Data Valid Indicator Interleaved Data Fast 1 Data Fast 0 Data Valid Indicator Fast Clock for SLAP I/F Start of Frame Indicator Fast 0 Volt GROUND Fast Data 1 Fast Data 0 Data 1 Data 0 Byte Request Fast +3.3 Volts power supply 0 Volt GROUND Byte Request Interleaved Start of Frame Indication Interleaved JTAG I/P JTAG O/P JTAG Mode Select +3.3 Volts power supply JTAG Clock 0 Volt GROUND JTAG Reset Enables scan test mode General purpose analog output Power down analog front end +3.3 Volts power supply Receive data nibble Receive data nibble 8 I90135 Product Data Sheet Version 1.2 (June 1999) Pin 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Mnemonic AFRXD_2 AFRXD_3 VSS CLWD MCLK CTRLDATA VDD AFTXED_0 AFTXED_1 VSS AFTXED_2 AFTXED_3 VDD IDDq AFTXD_0 AFTXD_1 VSS AFTXD_2 AFTXD_3 VDD Type I I Supply VDD VDD Driver IBUF IBUF BS I I I I O VDD VDD VDD IBUF IBUF BT4CR I C O O O VDD VDD BT4CR BT4CR O O O O VDD VDD BT4CR BT4CR O O I O O VDD VDD VDD IBUF BT4CR BT4CR none O O VDD VDD BT4CR BT4CR O O O O Description Receive data nibble Receive data nibble 0 Volt GROUND Start of word indication Master clock Serial data transmit channel +3.3 Volts power supply Transmit echo nibble Transmit echo nibble 0 Volt GROUND Transmit echo nibble Transmit echo nibble +3.3 Volts power supply Test pin, active high Transmit data nibble Transmit data nibble 0 Volt GROUND Transmit data nibble Transmit data nibble +3.3 Volts power supply Package The I90135 is available in a 144-pin PQFP package. ©1998 ITeX and Alcatel Alsthom. ITeX is a trademark of Integrated Telecom Express, Inc. All other trademarks are the sole property of their respective owners. Windows is a trademark of Microsoft Corporation. ITeX's Standard Terms and Conditions, available upon request, apply to all sales. All specifications are subject to change without notice. Integrated Telecom Express, Inc. 9