ICHAUS IC-MD 48-bit quadrature counter Datasheet

preliminary
iC-MD 48-BIT QUADRATURE COUNTER
WITH RS422 RECEIVER AND SPI/BISS INTERFACE
Rev B1, Page 1/30
FEATURES
APPLICATIONS
• Configurable quadrature 3-channel binary counter of
• PLC interface to linear scales,
•
•
•
•
•
•
•
•
•
•
•
•
•
16, 24, 32 and 48 bit (TTL, RS422 or LVDS input)
Fast RS422 12 V receiver for differential A/B/Z encoder signal
Count frequency to 40 MHz
Monitoring of A/B phase logic with error message
Evaluation of distance-coded reference marks
Pin-triggered touch-probe function with
selectable hi/lo edge sensitivity
Error and warning signal generation
Operation from 3.3 V to 5 V
Configuration via bus capable SPI and BiSS C Interface
Two actuator output signals
Default operation mode permits plug & play
without programming
3 Channel 16 bit counting (TTL: A/B)
2 Channel 16, 24 or 16+32 bit counting
(TTL: AP/AN/BP, BN/CP/CN)
1 Channel 16, 24, 32 or 48 bit counting
(TTL: AP/AN/BP or
RS422, LVDS: AP,AN/BP,BN/CP,CN differential)
rotary encoders, digital gauges
• Motion control
PACKAGES
TSSOP 20
BLOCK DIAGRAM
VDD
RS-422/TTL RECEIVERS
AP
REFERENCE-TO-REFERENCE
COUNTER 24 Bit
MULTIPLEXER
DATA I/O
AND
STATUS
UPD Register
+
-
NERR
ERROR
REGISTERS
REFCNT
NWARN
REF Register
AN
WARNING
BP
+
A0
-
B0
BN
+
CN
COUNTERS
CNT 0
CNT 1
CNT 2
24 Bit
-
-
A1
24 Bit
24 Bit
-
B1
48 Bit
-
-
Z1
32 Bit
-
-
32 Bit
16 Bit
-
A2
16 Bit
-
-
B2
16 Bit
16 Bit
-
16 Bit
16 Bit
16 Bit
Z0
CP
CONFIGURABLE
ACTUATOR OUTPUT
ACT1
ACT0
SPI INTERFACE
SCK
NCS
MOSI
TOUCH PROBE
iC-MD
TPI
MISO
TP1
SERIAL INTERFACE
ENTP
+
TP2
BiSS C
SLO
SLI
SSI
MA
GND
Copyright © 2006, 2017 iC-Haus
http://www.ichaus.com
preliminary
iC-MD 48-BIT QUADRATURE COUNTER
WITH RS422 RECEIVER AND SPI/BISS INTERFACE
Rev B1, Page 2/30
DESCRIPTION
iC-MD evaluates incremental encoder signals with A,
B and index tracks from up to three encoders.
After power-on the iC-MD has all the RAM bits at 0 as
default configuration, that means one 24 bit counter
is configured with RS422 differential inputs. The encoder signals A+/A- are connected to AP,AN, B+/Bto BP,BN and Z+/Z- to CP,CN. The device can be
programmed via the SPI interface or BiSS Interface.
The 48 bit counter can be configured as up to three
counters with variable counter depths of 16, 24, 32
or 48 bits, but the sum of bits of all the configured
counters can not be higher than 48 bits. Some of the
possible configurations are 1x48 bit, 2x24 bit, 3x16 bit,
1x32 + 1x16 bit. Each edge of the synchronized encoder signal counts (fourfold edge evaluation).
An additional 24bit counter REF counter is used to
store the distance (number of pulses) between the
first two index pulses after power-on and the distance
between every last two index pulses in UPD register.
An event at the input pin TPI (configurable as rising,
falling or both edges) loads the register TP1 with the
actual value of the counter 0, and shift the old value
of TP1 in register TP2. This registers can also be
loads through the instruction bit TP, via SPI or BiSS
(Register communication).
Two bidirectional ports are used as error and warning
output (low active) and can be pulled down from outside to signals an external error or external warning.
This external error and warning are internally latched
in the status registers.
A set of status registers monitor the status of the
counter, TP1, TP2, REF, UPD, power on and external
error and warning pins.
The BiSS Interface uses the BiSS C protocol and
reads out the counter and registers TP1, TP2 and
UPD as Sensor data. REF register is read via BiSS C
register communication.
The device described here is a multifunctional iC that contains
integrated BiSS C interface components. The BiSS C process is
protected by patent DE 10310622 B4 owned by iC-Haus GmbH
and its application requires the conclusion of a license (free of
charge).
Download the license at
www.biss-interface.com/bua
preliminary
iC-MD 48-BIT QUADRATURE COUNTER
WITH RS422 RECEIVER AND SPI/BISS INTERFACE
Rev B1, Page 3/30
PACKAGING INFORMATION
PIN CONFIGURATION
TSSOP20 4.4 mm, lead pitch 0.65 mm
PIN FUNCTIONS
No. Name
Function
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
SLO
TPI
SLI
ACT1
MA
ACT0
AP
VDD
AN
NCS
BP
SCK
BN
MOSI
CP
MISO
CN
GND
nWARN
nERR
1
2
3
4
5
6
7
8
9
10
11
SLO
SLI
MA
AP
AN
BP
BN
CP
CN
GND
NERR
BiSS/SSI Interface, data output
BiSS/SSI Interface, data input
BiSS/SSI Interface, clock input
Signal Input (CNT0)
Signal Input (CNT0)
Signal Input (CNT0/CNT1)
Signal Input (CNT0/CNT1)
Signal Input (CNT0/CNT1/CNT2)
Signal Input (CNT0/CNT1/CNT2)
Ground
Error Message Output (low active)
/ System Error Message Input
12 NWARN Warning Message Output (low active)
/ System Warning Message Input
13 MISO
SPI Interface, data output
14 MOSI
SPI Interface, data input
15 SCK
SPI Interface, clock input
16 NCS
SPI Interface, chip select (low active)
17 VDD
3.0 . . . 5.5 V Supply Voltage
18 ACT0
Actuator Output 0
19 ACT1
Actuator Output 1
20 TPI
Touch Probe Input
preliminary
iC-MD 48-BIT QUADRATURE COUNTER
WITH RS422 RECEIVER AND SPI/BISS INTERFACE
Rev B1, Page 4/30
ABSOLUTE MAXIMUM RATINGS
These ratings do not imply operating conditions; functional operation is not guaranteed. Beyond these ratings device damage may occur.
Item
No.
Symbol
Parameter
Conditions
Unit
Min.
Max.
G001 V()
Voltage at VDD
-0.3
7
V
G002 V()
Voltage at MA, SLI, NERR, NWARN,
NCS, SCK, MOSI, TPI
-0.3
7
V
G003 I()
Current in MA, SLI, NERR, NWARN,
NCS, SCK, MOSI, TPI
-4
4
mA
G004 V()
Voltage at AP, AN, BP, BN, CP, CN
-7
7
V
G005 I()
Current in AP, AN, BP, BN, CP, CN
-20
20
mA
G006 Vd()
ESD Susceptibility at all pins
2
kV
G007 Tj
Junction Temperature
-40
150
°C
G008 Ts
Storage Temperature Range
-40
150
°C
HBM 100 pF discharged through 1.5 kΩ
THERMAL DATA
Item
No.
T01
Symbol
Parameter
Conditions
Unit
Min.
Ta
Operating Ambient Temperature Range
All voltages are referenced to ground unless otherwise stated.
All currents flowing into the device pins are positive; all currents flowing out of the device pins are negative.
-40
Typ.
Max.
125
ºC
preliminary
iC-MD 48-BIT QUADRATURE COUNTER
WITH RS422 RECEIVER AND SPI/BISS INTERFACE
Rev B1, Page 5/30
ELECTRICAL CHARACTERISTICS
Operating Conditions: VDD = 3 . . . 5.5 V, Tj = -40 . . . 125 °C, unless otherwise noted.
Item
No.
Symbol
Parameter
Conditions
Unit
Min.
Typ.
Max.
General
001
002
VDD
Voltage Supply VDD
I(VDD)
Supply Current in VDD
TTL input configuration, 48 bits counter
10 MHz signal in AP (0º phase) and AN
(90º phase), BP, BN, CP and CN to GND
3
5.5
V
15
mA
003
Vc()hi
Clamp Voltage hi
Vc()hi = V() - VDD, I() = 1 mA, all pins
004
Vc()lo
Clamp Voltage lo
Vc()hi = V() - VDD, I() = 1 mA, all pins
0.4
1.5
V
-1.5
-0.25
V
VDD = 4.5 . . . 5.5 V
VDD = 3 . . . 5.5 V
0.8
0.75
2
V
Digital Inputs: MA, SLI, SCK, MOSI, NCS, TPI
101
102
Vt()hi
Input Threshold Voltage hi
Vt()lo
Input Threshold Voltage lo
103
Vt()hys
Input Hysteresis
104
Ipd()
Input Pull-down Current at
SCK, MOSI, TPI
V() = 1 V . . . VDD
105
Ipu()
Input Pull-Up Current at
NCS, MA
V() = 0 V . . . VDD - 1 V
106
fclk(MA)
Permissible Clock Frequency at
MA
ENSSI = 1 (SSI protocol)
ENSSI = 0 (BiSS protocol)
107
108
Voc()
Pin Open Voltage at SLI
Ri()
Internal Resistance at SLI
Referenced to VDD
Referenced to GND
109
to(SLI)
Digital Filter at SLI
SLI = open
110
fclk(SCK)
Permissible Clock Frequency at
SCK
V
V
150
250
2
30
75
µA
-75
-30
-2
µA
4
10
MHz
MHz
51
%VDD
70
40
170
110
kΩ
kΩ
5
25
µs
10
MHz
-10
µA
2
V
42
46.5
mV
Bidirectional Pins: NWARN, NERR
201
Ipu()
Pull-Up Current
202
203
Vt()hi
Input Threshold Voltage hi
V() = 0 V . . . VDD - 1 V
Vt()lo
Input Threshold Voltage lo
204
Vt()hys
Input Hysteresis
205
Vs()lo
Saturation Voltage lo
I() = 4 mA
206
Isc()lo
Short-Circuit Current lo
V() = 0 V . . . VDD
VDD = 4.5 . . . 5.5 V
VDD = 3 . . . 5.5 V
-850
-100
0.8
0.75
150
V
V
250
4
mV
450
mV
100
mA
ABZ Counter
301
R()
Counter Resolution
48
bit
302
303
fcnt()
Permissible Count Frequency
40
MHz
PHab2
Permissible A/B Phase Distance edge A vs. edge B and vice versa
TTL=1
TTL=0, LVDS=X
5
13
ns
ns
Power-Down Reset and Oscillator
601
VDDon
Power-On Supply Voltage
602
VDDoff
Power-Down Voltage
2.9
603
604
VDDhys
Power-On Hysteresis
VDDon - VDDoff
35
f(CLK)
Internal Oscillator Frequency
VDD = 3.5 . . . 5.5 V
VDD = 3 . . . 3.5 V
1.4
1.6
2.1
V
V
100
mV
5.6
6.7
MHz
MHz
Digital Outputs: SLO, MISO, ACT0, ACT1
701
Vs()hi
Saturation Voltage hi
Vs()hi = VDD - V(), I() = -4 mA
450
mV
702
Vs()lo
Saturation Voltage lo
I() = 4 mA
450
mV
703
Isc()hi
Short-Circuit Current hi
V() = 0 . . . VDD
704
Isc()lo
Short-Circuit Current lo
V() = 0 . . . VDD
-115
mA
100
mA
preliminary
iC-MD 48-BIT QUADRATURE COUNTER
WITH RS422 RECEIVER AND SPI/BISS INTERFACE
Rev B1, Page 6/30
ELECTRICAL CHARACTERISTICS
Operating Conditions: VDD = 3 . . . 5.5 V, Tj = -40 . . . 125 °C, unless otherwise noted.
Item
No.
Symbol
Parameter
Conditions
RS-422 Configuration: Differential Inputs AP, AN, BP, BN, CP, CN
A01 Vcm()
Common Mode Voltage Range
TTL = 0, LVDS = 0
VDD = 4.5 . . . 5.5 V
VDD = 3 . . . 5.5 V
A02 Vd()
Differential Input Threshold
TTL = 0, LVDS = 0,
V() = V(AP) - V(AN)
Voltage
V() = V(BP) - V(BN)
V() = V(CP) - V(CN)
A03
Unit
Min.
Vhys()
Differential Input Hysteresis
TTL = 0, LVDS = 0,
Vhys() = Vth()hi-Vth()lo
(guaranteed by design)
TTL Configuration: Input AP, AN, BP, BN, CP, CN
B01 Vt()hi
Input Threshold Voltage hi at
TTL = 1, LVDS = 0
AP, AN, BP, BN, CP, CN
B02 Vt()lo
Input Threshold Voltage lo at
TTL = 1, LVDS = 0
AP, AN, BP, BN, CP, CN
Typ.
0
0
3
1.5
V
V
-300
300
mV
2.5
10
mV
2
V
0.8
V
B03
Vt()hys
Input Hysteresis at
AP, AN, BP, BN, CP, CN
TTL = 1, LVDS = 0
150
300
B04
Rpd()
Pull-Down Resistor
TTL = 1, LVDS = 0
35
50
LVDS Configuration: Differential Inputs AP, AN, BP, BN, CP, CN
C01 Vin()
Input Voltage Range
TTL = 0, LVDS = 1
VDD = 4.5 . . . 5.5 V
VDD = 3 . . . 5.5 V
C02 Vd()
Differential Input Threshold
TTL = 0, LVDS = 1
V() = V(AP)-V(AN)
Voltage
V() = V(BP)-V(BN)
V() = V(CP)-V(CN)
C03 Vhys()
Differential Input Hysteresis
TTL = 0, LVDS = 1
Vhys() = Vth()hi-Vth()lo
(guaranteed by design)
Max.
mV
65
kΩ
0.8
0.8
3
1.5
V
V
-200
200
mV
1.2
12
mV
preliminary
iC-MD 48-BIT QUADRATURE COUNTER
WITH RS422 RECEIVER AND SPI/BISS INTERFACE
Rev B1, Page 7/30
OPERATING REQUIREMENTS: SPI Interface
Operating Conditions: VDD = 3 . . . 5.5 V, Tj = -40 . . . 125 °C, unless otherwise noted.
Item
No.
Symbol
Parameter
Conditions
Unit
Min.
Max.
SPI Interface
I001 tsCCL
Setup Time:
NCS hi → lo before SCK lo → hi
15
ns
I002 tsDCL
Setup Time:
MOSI stable before SCK lo → hi
20
ns
I003 thDCL
Hold Time:
MOSI stable after SCK lo → hi
0
ns
I004 tCLh
Signal Duration SCK hi
25
ns
I005 tCLI
Signal Duration SCK lo
25
ns
I006 thCLC
Hold Time: NCS lo after SCK lo → hi
25
ns
I007 tCSh
Signal Duration NCS hi
0
I008 tpCLD
Propagation Delay:
MISO stable after SCK hi → lo
40
ns
I009 tpCSD
Propagation Delay:
MISO high impedance after
NCS lo → hi
25
ns
I010 f(SCK)
Clock Frequency
10
MHz
tCSh
NCS
tsCCL
tCLh
thCLC
tpCLl
SCK
tsDCL thDCL
MOSI
MISO
MSB in
LSB in
tristate
tCSh
NCS
tpCLh tpCLl
thCLC
SCK
MOSI
don’t care
tpCLD
MISO
tpCLD
MSB out
tpCSD
LSB out
Figure 1: SPI write cycle (top) and read cycle (bottom)
ns
preliminary
iC-MD 48-BIT QUADRATURE COUNTER
WITH RS422 RECEIVER AND SPI/BISS INTERFACE
Rev B1, Page 8/30
OPERATING REQUIREMENTS: BiSS and SSI Interface
Operating Conditions: VDD = 3 . . . 5.5 V, Tj = -40 . . . 125 °C, unless otherwise noted; input levels lo = 0 ... 0.45 V, hi = 2.4 V ... VDD
Item
No.
Symbol
Parameter
Conditions
SSI Output (ENSSI = 1)
I101 TMAS
Permissible Clock Period
ENSSI = 1
SLI = open
Unit
Min.
Max.
250
2x ttos
ns
I102 tMASh
Clock Signal Hi Level Duration
25
ttos
ns
I103 tMASl
Clock Signal Lo Level Duration
25
ttos
ns
BiSS C Single Cycle Data
I104 TMAS
Permissible Clock Period
I105 tMASh
Clock Signal Hi Level Duration
ENSSI = 0
100
25
I106 tMASl
Clock Signal Lo Level Duration
25
Figure 2: Timing diagram of SSI output.
Figure 3: Timing diagram of BiSS C DATA (here: CDS, counter data, status, CRC)
ns
ttos
ns
ns
preliminary
iC-MD 48-BIT QUADRATURE COUNTER
WITH RS422 RECEIVER AND SPI/BISS INTERFACE
Rev B1, Page 9/30
CONFIGURATION PARAMETERS
Read/Write Registers
Configuration
INVZ0
Invert Z On CNT0 (P. 13)
INVZ1
Invert Z On CNT1 (P. 13)
EXCH0
Exchange AB On CNT0 (P. 13)
EXCH1
Exchange AB On CNT1 (P. 13)
EXCH2
Exchange AB On CNT2 (P. 13)
CNTCFG(2:0) Counter Length Configuration (P. 12)
TTL
TTL Inputs (P. 13)
CBZ0
CNT0 Cleared By Z0 Signal (P. 12)
CBZ1
CNT1 Cleared By Z1 Signal (P. 12)
CFGZ(1:0)
Index Signal Configuration (P. 12)
TPCFG(1:0)
PRIOR
MASK(9:0)
NMASK(1:0)
LVDS
CH0SEL
CH1SEL
CH2SEL
NENCH0
ENCH1
ENCH2
TPI Pin Configuration (P. 16)
SPI Interface Priority (P. 26)
Error/Warning Event Mask (P. 21)
Error/Warning Event Not Mask (P. 21)
LVDS/RS-422 Inputs (P. 13)
BiSS Channel Selection CH0 (P. 25)
BiSS Channel Selection CH1 (P. 25)
BiSS Channel Selection CH2 (P. 25)
Disable BiSS Channel 0 (P. 25)
Enable BiSS Channel 1 (P. 25)
Enable BiSS Channel 2 (P. 25)
Table 6: Register Description
Write Only Registers
Instructions
ACT0
Control Actuator Pin ACT0 (P. 17)
ACT1
Control Actuator Pin ACT1 (P. 17)
TP
Touch Probe Instruction (P. 17)
ZCEN
Enable Zero Codification (P. 17)
ABRES0 Reset Counter CNT0 (P. 17)
ABRES1 Reset Counter CNT1 (P. 17)
ABRES2 Reset Counter CNT2 (P. 17)
Table 7: Instruction Byte
Read Only Registers
Measurement Data and Status
AB
AB Counter Values (P. 16)
NWARN
No Warning (P. 16)
NERR
No Error (P. 16)
TP1
Touch Probe Register 1 (P. 16)
TP2
Touch Probe Register 2 (P. 16)
NTPVAL
Touch Probe Register Not Valid (P. 16)
NABERR No AB Counter Error (P. 16)
REF
Reference Counter Value (P. 14)
UPD
Update Register (P. 15)
NUPDVAL Update Register Not Valid (P. 15)
Table 8: Counter Registers
Errors
ABERRx AB Decodification Error
Counter CNTx (P. 18)
EXTERR External Error (P. 19)
Table 9: Error Registers
Warnings
OVFx
Counter Overflow Warning
Counter CNTx (P. 18)
ZEROx
Zero Value In Counter CNTx (P. 18)
PDWN
Undervoltage Reset (P. 18)
RVAL
REF Register Value Valid (P. 18)
UPDVAL
UPD Update Register Valid (P. 18)
OVFREF
Reference Counter Overflow (P. 19)
TPVAL
Touch Probe Values Valid (P. 19)
EXTWARN External Warning (P. 19)
COMCOL Communication Collision (P. 19)
TPS
Touch Probe Pin Status (P. 19)
ENSSI
SSI Enabled (P. 19)
Table 10: Warning Registers
BiSS Identifier
BiSS Device ID
(P. 26)
BiSS Device Revision
(P. 26)
BiSS Device Manufacturer ID (P. 26)
Table 11: Warning Registers
preliminary
iC-MD 48-BIT QUADRATURE COUNTER
WITH RS422 RECEIVER AND SPI/BISS INTERFACE
Rev B1, Page 10/30
REGISTER MAP
PROGRAMMING
Adr
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
EXCH1
EXCH0
Bit 2
Bit 1
Bit 0
Configuration
0x00
INVZ1
INVZ0
EXCH2
0x01
TTL
CBZ1
CBZ0
CFGZ(1:0)
0x02
TPCFG(1:0)
PRIOR
MASK(7:0)
0x03
LVDS
0x04
CH2SEL
Reserved
ENCH2
CH1SEL
NMASK(1:0)
ENCH1
0x05
CH0SEL
MASK(9:8)
NENCH0
Reserved
Reserved
0x06
0x07
CNTCFG(2:0)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
ABRES2
ABRES1
ABRES0
TPVAL
Measurement Data (SPI read only)
0x08
AB/SPICH(47:0) + NERR + NWARN
0x09
Reserved
0x0A
UPD(23:0) + NABERR + NUPDVAL
0x0B
Reserved
0x0C
TP1(23:0) + NABERR + NTPVAL
0x0D
Reserved
0x0E
TP2(23:0) + NABERR + NTPVAL
Measurement Data (SPI and BiSS read only)
0x10
REF(23:16)
0x11
REF(15:8)
0x12
REF(7:0)
SPI write only data. (read via AB)
0x20
SPICH(47:40)
0x21
SPICH(39:32)
0x22
SPICH(31:24)
0x23
SPICH(23:16)
0x24
SPICH(15:8)
0x25
SPICH(7:0)
Instruction Byte (write only)
0x30
Reserved
ACT1
ACT0
TP
ZCEN
BiSS Profile ID (SPI and BiSS read only)
0x42
BiSS Profile ID: 0x33
0x43
BiSS Profile ID: 0x18
Status
0x48
ABERR0
OVF0
ZERO0
PDWN
RVAL
UPDVAL
OVFREF
0x49
ABERR1
OVF1
ZERO1
PDWN
EXTERR
EXTWARN
COMCOL
TPS
0x4A
ABERR2
OVF2
ZERO2
PDWN
EXTERR
EXTWARN
COMCOL
ENSSI
preliminary
iC-MD 48-BIT QUADRATURE COUNTER
WITH RS422 RECEIVER AND SPI/BISS INTERFACE
Rev B1, Page 11/30
PROGRAMMING
Adr
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
BiSS Device and Manufacturer ID (SPI and BiSS read only)
0x78
BiSS Device ID - 0x4D (’M’)
0x79
BiSS Device ID - 0x44 (’D’)
0x7A
BiSS Device Revision - 0x58 (’X’)
0x7B
BiSS Device Revision - 0x00 (’0’)
0x7C
BiSS Device Revision - 0x00 (”)
0x7D
BiSS Device Revision - 0x00 (”)
0x7E
BiSS Device Manufacturer ID (default 0x69)
0x7F
BiSS Device Manufacturer ID (default 0x43)
Table 12: Register layout
Bit 1
Bit 0
preliminary
iC-MD 48-BIT QUADRATURE COUNTER
WITH RS422 RECEIVER AND SPI/BISS INTERFACE
Rev B1, Page 12/30
COUNTER CONFIGURATION
iC-MD has a 48 bit counter configurable from single to
up to three counters with bit lengths from 16 to 48 bit.
Table 13 show all the possible counters configuration
considering table 18 and table 20.
The ”count of counter” configuration is given by the
registers CNTCFG as shown in table 13.
If it is configured with more than one counter, the
input stage must be set to TTL (table 17).
CNTCFG
Code
Addr. 0x00; bit (2:0)
Counter Configuration
Default = 0b000
000
001
010
011
CNT0 = 24 bit: 1 counter: TTL, RS422 or LVDS
CNT0 = 24 bit + CNT1 = 24 bit:2 counter: TTL only
CNT0 = 48 bit: 1 counter: TTL, RS422 or LVDS
CNT0 = 16 bit: 1 counter: TTL, RS422 or LVDS
100
101
110
111
CNT0 = 32 bit: 1 counter: TTL, RS422 or LVDS
CNT0 = 32 bit + CNT1 = 16 bit: 2 counter: TTL only
CNT0 = 16 bit + CNT1 = 16 bit: 2 counter: TTL only
CNT0 = 16 bit + CNT1 = 16 bit + CNT2 = 16 bit:
3 counter: TTL only
Table 13: Count of Counter and Counter Length Configuration
Note that the three counter configuration does not
implement any Zero signal input, only A and B input signals.
The 48 bit register of the AB counter is also used as
"SPI data channel" for data exchanging between SPI
and BiSS interface, for that purpose the bit CH0SEL
(table 65) must be set to 1. When CH0SEL = 1, the
counting function for all the counters is deactivated.
Index Signal Z
In default operation configuration, the index signal Z
is active when A = B = 1, as shown in table 14 with
EXCH = 0 and INVZ = 0. All other configurations are
also possible.
CFGZ
Code
Addr. 0x01; bit (4:3)
Function:
00
01
10
11
Z active:
Z active:
Z active:
Z active:
Default = 0b00
when A = 1 B = 1
when A = 1 B = 0
when A = 0 B = 1
when A = 0 B = 0
Table 14: Index Signal Configuration
It can also be deactivated the clearing of counter by the
index signal with the configuration bit CBZ ( table 15
and table 16 ).
The CBZ configuration is only applicable after the second index pulse after power-on or the activation of
ZCEN (table 40), because after it, the iC-MD will reset
the counter value by the firsts two index pulse, independently of the CBZ configuration, in order to have the AB
Counter value referenced to the second index pulse.
By default, CBZ is set to 0, also the counters are not
reset to 0 by the index signal. But the firsts two Index
pulse always reset the counters.
CBZ0
Addr. 0x01; bit (5)
Code
Function
0
1
CNT0 not cleared by Z0 signal
CNT0 cleared by Z0 signal
Default = 0b0
Table 15: CNT0 Cleared By Z0 Signal
CBZ1
Code
Addr. 0x01; bit (6)
Function
0
CNT1 not cleared by Z1 signal
1
CNT1 cleared by Z1 signal
Default = 0b0
Table 16: CNT0 Cleared By Z1 Signal
preliminary
iC-MD 48-BIT QUADRATURE COUNTER
WITH RS422 RECEIVER AND SPI/BISS INTERFACE
Rev B1, Page 13/30
INPUT CONFIGURATION
The input stage for the incremental signals ABZ is configurable as single-ended TTL and differential (RS-422
or LVDS). Differential inputs are possible only for a single counter configuration and the input configuration
shown in table 18.
TTL
Code
Addr. 0x01; bit (7)
Function
0
1
Differential inputs
TTL inputs
Default = 0b0
Table 17: TTL Inputs
Counter
A0
B0
Z0
1xDifferential AP AN BP BN CP CN
Table 18: RS422 or LVDS Input Counters Configuration
If two or more counter are configured, the TTL input configuration shown in table 20 must be used
and table 13 shows all the possible counter configuration.
It is possible to configure the differential input stage of
iC-MD in two different modes; differential RS-422 and
differential LVDS. See table 19.
LVDS
Code
Addr. 0x03; bit (7)
Function
0
1
Differential RS-422 inputs
Differential LVDS inputs
Notes
condition: TTL=0
The configuration bit EXCH exchanges the input A and
the input B of the counters. The default counting direction is positive in clockwise (CW) direction (A edge take
place before B edge). But it is also possible to change
the counting direction with the register EXCH. See table
21, table 22 and table 23.
EXCH0
Code
Addr. 0x00; bit (3)
Function
0
Exchange AB CNT0 (CW positive)
1
Exchange AB CNT0 (CCW positive)
Default = 0b0
Table 21: Exchange AB Inputs Channel on Counter
CNT0
EXCH1
Code
Addr. 0x00; bit (4)
Function
0
1
Exchange AB CNT1 (CW positive)
Exchange AB CNT1 (CCW positive)
Default = 0b0
Table 22: Exchange AB Inputs on Counter CNT1
EXCH2
Addr. 0x00; bit (5)
Code
Function
0
1
Exchange AB CNT2 (CW positive)
Exchange AB CNT2 (CCW positive)
Default = 0b0
Default = 0b0
Table 23: Exchange AB Inputs on Counter CNT2
The index (Z) signal can be inverted as shown in table
24 and table 25 with the register bits INVZ(1:0).
Table 19: LVDS/RS-422 Inputs
Counters
1xTTL
2xTTL
3xTTL
A0
AP
AP
AP
B0 Z0 A1 B1 Z1 A2 B2
AN BP AN BP BN CP CN AN - BP BN - CP CN
INVZ0
Code
Addr. 0x00; bit (6)
Function
0
1
Non inverted Z on CNT0
Inverted Z on CNT0(Z=0 active)
Default = 0b0
Table 24: Invert Z Signal Counter CNT0
Table 20: TTL Input Counters Configuration
Note that the three counters configuration don’t implement any Zero signal. It has only A and B input signals.
Register bits TTL and LVDS set the configuration of the
quadrature input signals.
INVZ1
Code
Addr. 0x00; bit (7)
Function
0
Non inverted Z on CNT1
1
Inverted Z on CNT1(Z=0 active)
Default = 0b0
Table 25: Invert Z Signal Counter CNT1
preliminary
iC-MD 48-BIT QUADRATURE COUNTER
WITH RS422 RECEIVER AND SPI/BISS INTERFACE
Rev B1, Page 14/30
24 BIT REFERENCE COUNTER
An additional 24 bit counter is integrated in order to load
the REF and UPD registers. The value of this internal
counter can not be read, it can only be read the values
of REF and UPD registers. The reference counter is
activated by default after power-on and reset with every
index signal (it is not affected by the configuration bit
CFGZ, table 14).
Since the internal counter for REF and UPD is 24 bit
long, the maximum number of edges that can be evaluated (loaded in UPD and REF) between two index
signal goes from -223 (negative counting direction) to
223 -1 (positive counting direction).
REF REGISTER
After the start up (Power on), the iC-MD counts the
number of edges between the first two different index
signals (Z) in the register REF. This function is always
activated by the following situations:
of edges between the first two index signals stored in
REF.
REF(23:0)
Addr. 0x10 to 0x12;
R
REF register value
- after power-on.
- by activating the zero codification function via instruction byte (table 40).
The process runs as following: the "reference counter"
is set to zero with the first index signal, and the second
index signal (must be different of the first one) loads the
register REF with the value of "reference counter". It
is the distance between the first and the second index
signals. The AB counter is then set to 0 with the second
index signal. The counter value is then referenced to
the position of the second Z signal, and the number
0xXXXXXX
Table 26: Reference Counter Value
After the second index signal, the status bit RVAL (table
48) is set and remains at this value until the next power
on, the activation of the zero codification function or
until the resetting of the counter 0.
The following diagrams show the reference position acquisition process also called as zero codification function.
Figure 4: Zero-Codification: REF and UPD registers after activation of Zero Codification function
preliminary
iC-MD 48-BIT QUADRATURE COUNTER
WITH RS422 RECEIVER AND SPI/BISS INTERFACE
Rev B1, Page 15/30
Figure 5: Zero-Codification: reference position acquisition
UPD REGISTER
The register UPD is load at every index pulse with the
value of the "reference counter", it is the number of
AB edges between the last two index pulses (value of
the reference counter). It is used to check that any AB
pulse was lost.
The status bit UPDVAL (table 49) signals that a new
UPD value is available (UPD register was loaded and
still not read).
UPD(23:0)
Addr. 0x0A;
NUPDVAL
0
1
Addr. 0x0A;
R
UPD value valid
UPD value not valid
Table 28: Update Register Not Valid
The following diagram shows the value of REF and
UPD after activating the zero codification function when
counting in negative direction.
R
UPD register value
0xXXXXXX
Table 27: Update Register Value
5000
5000
5000
5005
Z
2510
Z
2490
Z
5005
2515
Bit ZCEN=1
Z
2485
Z
Negative counting direction
5005
2520
Z
2480
Z
2525
REF
0
-2510
-2510
-2510
-2510
-2510
-2510
UPD
X
-2510
-2490
-2515
-2485
-2520
-2480
CNT
X
0+n
-2490+n
-2515+n
-5000+n
-5520+n
Figure 6: REF and UPD registers in negative direction
-10000+n
Z
preliminary
iC-MD 48-BIT QUADRATURE COUNTER
WITH RS422 RECEIVER AND SPI/BISS INTERFACE
Rev B1, Page 16/30
TP1, TP2 and AB REGISTERS
TP1, TP2 Registers
The touch probe registers consist of two 24 bit registers
which are load with a TPI pin event (see table 29) or
writing the instruction bit TP (table 41) via SPI/BiSS. At
every TPI pin or TP instruction event, the register TP2
is load with the value of TP1 and TP1 is load with the
actual value of counter 0. For using TP registers, AB
counter must be configured to 24 bit, but if 2x24 bit counters are configured, only the counter 0 will be latched
into TP1/TP2 registers. The TPI pin events can be
configured as falling, rising or both edges, as shown in
table 29.
TP1(23:0)
Addr. 0x01; bit (2:1)
Code
Function
00
01
both edges active
rising edge active
10
11
falling edge active
pin TPI disabled
Default = 0b00
R
TP1 value
0xXXXXXX
Table 30: Touch Probe 1
TP2(23:0)
Addr. 0x0E;
R
TP2 value
0xXXXXXX
Table 31: Touch Probe 2
NTPVAL
TPCFG
Addr. 0x0C;
0
1
Addr. 0x0C or 0x0E;
R
TP valid
TP not valid
Table 32: Touch Probe Register Not Valid
The following diagram (figure 7) shows the function of
the pin TPI when configured for both rising and falling
edge.
Table 29: TPI Pin Configuration
Figure 7: Function of TPI pin when TPCFG=11
AB Register
A 48 bit register (AB) is used to store and shift out the
ABCNT Registers (Counters), and also the "SPI Channel Data" (SPICH). The register AB is read via BiSS
(sensor data, channel 0) or via SPI (Adr 0x08), and the
bit length is set by the configuration bits CNTCFG (table
13)
AB(47:0)
0xXX..XX
Addr. 0x08;
R
AB counter value
0
1
Addr. 0x08;
Warning active
No warning active
Table 34: No Warning
0
1
Addr. 0x08;
R
Error active
No Error active
Table 35: No Error
NABERR
0
1
Addr. 0x0A or 0x0C or
0x0E;
R
AB counter value error
AB counter correct value
Table 36: No AB Counter Error
Table 33: AB Counter Values
NWARN
NERR
R
The bit CH0SEL (table 65) selects the data to be load
in the AB register when reading the channel 0 via BiSS
or the address 0x08 via SPI.
preliminary
iC-MD 48-BIT QUADRATURE COUNTER
WITH RS422 RECEIVER AND SPI/BISS INTERFACE
Rev B1, Page 17/30
COMMUNICATION CONTROL
iC-MD can communicate simultaneously via SPI and
BiSS in order to exchange data between SPI and BiSS.
For this purpose, SPI writes the data to be read by BiSS
in the AB register, and BiSS reads the SPICH (BiSS
channel 0 configured as SPICH, see table 65).
If both interfaces attempt to read or write at the same
time a different RAM address than the SPICH (Adr.
0x20 to 0x25), then the bit error COMCOL (table 54)
is set and the communication of the interface without
priority (see table 71) is not valid.
Instruction Byte
Register address 0x30 contains the write only instruction byte. When one of these bits is set to 1, then the
corresponding operation is executed and then set back
to 0, excepts the bits ACT0 and ACT1 which remain to
the written value.
ABRES0
Addr. 0x30; bit 0
Code
Function
1
Reset of counter 0
Default = 0b0
ABRES2
Code
Addr. 0x30; bit 2
Function
1
Reset of counter 2
Table 39: Reset Counter 2
ZCEN
Code
Addr. 0x30; bit 3
Function
1
Enable zero codification
Addr. 0x30; bit 1
Function
1
Reset of counter 1
Table 38: Reset Counter 1
Default = 0b0
Table 40: Enable Zero Codification
TP
Code
Addr. 0x30; bit 4
Function
1
Load TP2 with TP1 value
and TP1 with ABCNT value
Notes
Counter must be configured to 24 bit length
Default = 0b0
Table 41: Touch Probe Instruction
The instruction bits ACT0 and ACT1 set the actuator
pins ACT0 and ACT1 to high or low voltage.
ACT0
Code
Addr. 0x30; bit 5
Function
0
1
Set actuator pin 0 to GND
Set actuator pin 0 to VDD
Default = 0b0
Table 42: Control Actuator Pin 0
Table 37: Reset Counter 0
ABRES1
Code
Default = 0b0
Default = 0b0
ACT1
Code
Addr. 0x30; bit 6
Function
0
1
Set actuator pin 1 set to GND
Set actuator pin 1 set to VDD
Default = 0b0
Table 43: Control Actuator Pin 1
preliminary
iC-MD 48-BIT QUADRATURE COUNTER
WITH RS422 RECEIVER AND SPI/BISS INTERFACE
Rev B1, Page 18/30
STATUS REGISTER and ERROR/WARNING INDICATION
The three bytes status registers (Adr. 0x48 to 0x4A)
indicate the state of the iC-MD. All the status bits are
latched (except TPS) when an error/warning occurs
and are reset when reading the error/warning via SPI
or BiSS excepts RVAL. The status bits TPVAL and UPDVAL are also reset by reading the register TP1 and
UPD respectively.
ZEROx
Code
Addr. 0x48, 0x49, 0x4A;
bit 5
Description
R
0
no zero of counter x
1
zero of counter x
Notes
x = 0, 1, 2
reset by reading Adr. 0x48 (ZERO0), 0x49 (ZERO1)
and 0x4A (ZERO2)
The status bit TPS (table 55) is not latched, it signals
the actual state of the input pin TPI.
Table 46: Zero Value in Counter CNTx
Two of this status bits are error bits; ABERR (AB decodification error, table 44) and EXTERR (external error,
table 52), all others status bits signal warnings.
If VDD reaches the power off supply level (VDDoff,
Spec. Item No. 602), the iC-MD is reset and the RAM
initialized to the default value. Status bit PDWN indicates that this initialization has taken place.
Status bits ABERRx indicate a decodification error of
the AB inputs, it occurs if the counting frequency is too
high or if two incremental edges are too close (PHab2,
Spec. Item No.303).
ABERRx
Code
Addr. 0x48, 0x49, 0x4A;
bit 7
Description
R
0
1
No decodification error in counter x
Decodification error in counter x
Notes
x = 0, 1, 2
Reset by reading Adr. 0x48 (ABERR0),
0x49 (ABERR1) and
0x4A (ABERR2)
The corresponding counter must be reset (ABRES)
after an error
The maximum counting range of the counters depends
on the counter configuration (see table 13). A counter
with the bit length "n" has the maximum counting range
will be from -2n-1 up to 2n-1 -1. The corresponding bit
OVFx is set to 1 if the counter exceeds these values.
Addr. 0x48, 0x49, 0x4A;
bit 6
Code
Description
0
1
no overflow in counter x
overflow in counter x
Notes
x = 0, 1, 2
reset by reading Adr. 0x48 (OVF0), 0x49 (OVF1)
and 0x4A (OVF2)
Addr. 0x48, 0x49, 0x4A;
bit 4
Code
Description
0
1
No undervoltage
Undervoltage(RAM was reset)
Notes
Reset by reading Adr. 0x48, 0x49 or 0x4A
R
Table 47: Undervoltage Reset
Table 44: AB Decodification Error of Counter CNTx
OVFx
PDWN
R
RVAL status bit indicates that the reference value was
load in the REF register, after the "Zero Codification"
process. After power-on, this bit remains at 0 until the
second different Index pulse.
RVAL
Code
Addr. 0x48; bit 3
Description
0
1
REF Reg. not valid
REF Reg. valid
Notes
Reset by the instruction ZCEN(see table 40)
R
Table 48: REF Register Values Valid
Every time that the UPD register is loaded, the status
bit UPDVAL (UPD valid) is set to 1 until the status bit
UPD or the register UPD is read via SPI or BiSS.
UPDVAL
Code
Addr. 0x48; bit 2
Description
R
0
1
UPD Reg. not valid
UPD Reg. valid
Notes
Reset by reading Adr. 0x48 or the register UPD via
SPI (Adr. 0x0A) or BiSS (Channel 1)
Table 45: Counter Overflow Warning of Counter CNTx
Table 49: UPD Register Values Valid
ZEROx bits indicate that the counter value has reached
the zero value.
If the number of AB edges between two index signals is greater than 223 -1=8388607 or lower than
preliminary
iC-MD 48-BIT QUADRATURE COUNTER
WITH RS422 RECEIVER AND SPI/BISS INTERFACE
Rev B1, Page 19/30
-223 =-8388608 the status bit OVFREF is set to 1 and
indicates that the value of the UPD and REF registers
are not valid.
OVFREF
Code
Addr. 0x48; bit 1
Description
0
1
No Overflow in reference counter
Overflow in reference counter
Notes
Reset by reading Adr. 0x48
After loading TP1/TP2 register, either via pin TPI or
instruction TP (see table 41), the bit TPVAL is set to
1 and remains at 1 until the reading of TPVAL, TP1 or
TP2 via SPI or BiSS.
Addr. 0x48; bit 0
Description
0
TPx registers not loaded
TP1 and TP2 registers have not been updated
New values loaded in TP1 and TP2
1
Notes
R
Reset by reading Adr. 0x48, register TP1 or register
TP2 via SPI (Adr. 0x0C and 0x0E) or BiSS (channel
1 and channel 2, see table 65)
Table 51: Touch Probe Values Valid
Addr. 0x49, 0x4A; bit 3
Description
0
1
no external error
external error
Notes
Reset by reading Adr. 0x49 or 0x4A
no external warning
external warning
Notes
reset by reading Adr. 0x49 or 0x4A
R
Table 53: External Warning
If BiSS/SSI and SPI try to access at the same time
to the internal data bus (BiSS register communication
and SPI communication) the bit COMCOL will be set
indicating that a collision has taken place. If SPICH is
activated (table 65), the writing process of AB via SPI
and reading of channel 0 via BiSS at the same time will
generate no COMCOL warning.
If a communication collision take place, only the interface with priority (See table 71) executes the write/read
process correctly, but the other interface doe not write
any data, the other interface does read a false value.
COMCOL
Code
Addr. 0x49, 0x4A; bit 1
Description
0
1
no communication collision
communications collided
Notes
reset by reading Adr. 0x49 or 0x4A
R
Table 54: Communication Collision
Bit TPS signals the actual state of the input pin TPI. If
the pin TPI is high, the bit TPS remains at 1, and if TPI
is set to low, TPS status bit is 0.
The status bit (EXTERR: external error) indicates if the
pin NERR was either pulled-down from outside or set to
0 from inside (an internal masked error has occurred).
EXTERR
Code
0
1
R
Table 50: Reference Counter Overflow
TPVAL
Code
EXTWARN
Addr. 0x49, 0x4A; bit 2
Code
Description
TPS
Description
0
1
TPI pin at low
TPI pin at high
Status bit ENSSI signals if the SSI interface instead of
BiSS is configured. This is configured by the SLI pin, if
the pin is open, the SSI interface is selected. ENSSI
has an internal digital filter of 25 µs maximum.
ENSSI
The status bit (EXTWARN: external warning) bit indicates if the pin NWARN was either pulled-down from
outside or set to 0 from inside (an internal masked
warning has occurred).
R
Table 55: Touch-Probe Pin Status
R
Table 52: External Error
Addr. 0x49; bit 0
Code
Addr. 0x4A; bit 0
Code
Description
0
1
SSI not enabled
SSI enabled (pin SLI open)
Table 56: SSI Enabled
R
preliminary
iC-MD 48-BIT QUADRATURE COUNTER
WITH RS422 RECEIVER AND SPI/BISS INTERFACE
Rev B1, Page 20/30
Error and warning mask
The masks (MASK) and not masks (NMASK) bits, stipulate whether error and warning events are signaled as an
alarm via the open drain I/O pins NERR and NWARN.
STATUS1 (Addr. 0x49)
0
1
NERR pin forced
READ
NS
Q
C
D
NQ
4
5
6
7
TPS
COMCOL
EXTWARN
EXTERR
PDWN
ZERO1
OVF1
ABERR1
&
Other
mask bits
1
NERR
Pin and
NERR in measurement data
STATUS2 (Addr. 0x4A)
0
NWARN pin forced
READ
NS
Q
C
D
NQ
1
4
5
6
7
ENSSI
COMCOL
EXTWARN
EXTERR
PDWN
ZERO2
OVF2
ABERR2
&
Other
mask bits
1
NWARN
Pin and
NWARN in measurement data
Configuration (Addr. 0x02)
0
1
2
3
4
5
6
7
MASK(0)
MASK(1)
MASK(2)
MASK(3)
MASK(4)
MASK(5)
MASK(6)
MASK(7)
Configuration (Addr. 0x03)
0
1
2
3
4
5
6
7
MASK(8)
MASK(9)
NMASK(0)
NMASK(1)
LVDS
Figure 8: MASK gating
The latched events are reset with reading the STATUS addresses 0x48, 0x49 or 0x4A unless the event signals do
not persist. The read access is indicated by the latch reset signal ”READ”.
preliminary
iC-MD 48-BIT QUADRATURE COUNTER
WITH RS422 RECEIVER AND SPI/BISS INTERFACE
Rev B1, Page 21/30
STATUS0 (Addr. 0x48)
0
1
Update Register Valid
READ
NS
Q
C
D
NQ
3
4
5
6
AB CNT0 decodification error
READ
NS
Q
C
D
NQ
STATUS1 (Addr. 0x49)
0
1
2
3
4
5
6
AB CNT1 decodification error
READ
NS
Q
C
D
NQ
NS
Q
C
D
NQ
TPS
COMCOL
EXTWARN
EXTERR
PDWN
ZERO1
OVF1
ABERR1
STATUS2 (Addr. 0x4A)
0
1
2
3
4
5
6
AB CNT2 decodification error
READ
TPVAL
OVFREF
UPDVAL
RVAL
PDWN
ZERO0
OVF0
ABERR0
&
ENSSI
COMCOL
EXTWARN
EXTERR
PDWN
ZERO2
OVF2
ABERR2
Other
mask bits
1
Configuration (Addr. 0x03)
0
1
2
3
4
5
6
7
NWARN
Pin and
NWARN in measurement data
&
Other
mask bits
MASK(8)
MASK(9)
1
1
NERR
Pin and
NERR in measurement data
NMASK(0)
NMASK(1)
LVDS
Figure 9: NMASK gating
The latched events are reset with reading the STATUS addresses 0x48, 0x49 or 0x4A unless the event signals do
not persist. The read access is indicated by the latch reset signal ”READ”.
MASK
Bit
Adr 0x02, bit 7:0; Adr 0x03, bit 1:0 Default = 0x000
Error/Warning Event
NMASK
Bit
Adr 0x03, bit 3:2 Default = 0b00
error/warning event
9
8
7
6
enable SSI (warning)
external error (error)
zero value of active counter 0, 1 or 2 (warning)
touch-probe valid (warning)
1
AB decodification error. e.g. too high
frequency(error)
0
UPD reg. valid (warning)
Notes
5*
4
3
2
1
0
power down (RAM was initialized) (warning)
overflow of reference counter (warning)
overflow of counter 0, 1 or 2 (warning)
REF reg. valid (warning)
external warning (warning)
register communication collision (warning)
encoding of bit 1...0:
0 = message enabled, 1 = message disabled
Notes
encoding of bit 9 . . . 0:
0 = message disabled, 1 = message enabled
Table 57: Error/Warning Event Masks
Table 58: Error/Warning Event Not Masks
preliminary
iC-MD 48-BIT QUADRATURE COUNTER
WITH RS422 RECEIVER AND SPI/BISS INTERFACE
Rev B1, Page 22/30
SPI INTERFACE
The Serial Peripheral Interface (SPI) of iC-MD consists
of a SPI slave interface with polarity 0 and phase 0.
mand defines the operations to be performed
(Write/Read) and the address.
Each transmission starts with a falling edge of NCS
and ends with the rising edge. During transmission,
commands and data are controlled by SCK and NCS
according to the following rules:
• The rising edge of NCS ends all data transfer and
resets internal counter and command register
• Data transfer out from MISO starts with the falling
edge of SCK immediately after the last bit of the
SPI command is sampled in on the rising edge of
SCK
• Commands and data are shifted; MSB first, LSB
last
• Each output data/status bits are shifted out on the
falling edge of SCK (MISO line) and each bit is
sampled on the rising edge of SCK (Polarity 0,
Phase 0).
• Data transfer to MOSI continues immediately after
receiving the command in all cases where data is
to be written to iC-MD internal registers
• After the device is selected with the falling edge
of NCS, an 8-bit command is received. The com-
• The SPI interface can not be used for daisy chain
setups.
SPI Communication
The first byte to be transmitted to the iC-MD via SPI is the instruction (or command) which determine the
communication direction (read or write), and has the following structure:
Bit 7
R/W
Bit 6
Bit 5
SPI Commands
Bit 4
Bit 3
Bit 2
ADDRESS(6:0)
Bit 1
Bit 0
Table 59: SPI command structure
The following diagrams show the SPI write and read
processes.
Polarity 0, Phase 0
NCS
SCLK
MOSI
0
ADR(6:0)
7
6
5
4
3
2
1
0
7
6
5
Byte to write in ADR
MISO
4
3
2
1
0
2
1
0
X
Byte to write in ADR+1
High Impedance
Figure 10: SPI Write Data
Polarity 0, Phase 0
NCS
SCLK
MOSI
MISO
1
don't care
ADDRESS(6:0)
High Impedance
n
n-1
n-2
n-3
n-4
n-5
Figure 11: SPI Read Data
5
4
3
X
High Impedance
preliminary
iC-MD 48-BIT QUADRATURE COUNTER
WITH RS422 RECEIVER AND SPI/BISS INTERFACE
Rev B1, Page 23/30
The data length to be written is always 8 bit, but it is possible to transmit several bytes of data consecutively if the
NCS signal is not reset and SCLK continues being clocked. The address transmitted is then the start address
which is internally increased by 1 following each transmitted byte.
The data length to be read after the read instruction is variable:
Address 0x0A, 0x0C, 0x0E: 24 bit + 2 bit data length
For TP1, TP2 and UPD registers the single SPI read requires a transfer of 26 bit in one sequence.
Example: UPD = 24 bit + NERR + NWARN SPI data access
SPI READ DATA UPD(23:0) + NERR + NWARN
Adr
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Measurement Data (SPI read only)
0x0A
UDP(23:16)
UDP(15:8)
UDP(7:0)
NERR
NWARN
0b00.0000
Table 60: Register layout
Address 0x08: variable data length
For counter data, it depends on the counter configuration CNTCFG (Adr. 0x00 bit (2:0)) how many bits this single
transfer needs to clock out. See the table 61. The total length is CNT length + 2 bit (NERR, NWARN). Additional
bits may be clocked out as a full byte.
CNTCFG
0b000
0b001
0b010
0b011
0b100
0b101
0b110
0b111
Counter Configuration
CNT0 = 24 bit
CNT1 = 24 bit
CNT0 = 24 bit
CNT0 = 48 bit
CNT0 = 16 bit
CNT0 = 32 bit
CNT1 = 32 bit
CNT0 = 16 bit
CNT1 = 16 bit CNT0 = 16 bit
CNT2 = 16 bit CNT1 = 16 bit CNT0 = 16 bit
Table 61: SPI Counter Data Position
Total CNT length
24 bit
48 bit
48 bit
16 bit
32 bit
48 bit
32 bit
48 bit
preliminary
iC-MD 48-BIT QUADRATURE COUNTER
WITH RS422 RECEIVER AND SPI/BISS INTERFACE
Rev B1, Page 24/30
Example: CNT0 = 48 bit + NERR + NWARN SPI data access
SPI READ DATA AB/SPICH(47:0) + NERR + NWARN
Adr
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 1
Bit 0
Measurement Data (SPI read only)
0x08
AB/SPICH(47:40) = CNT0(47:40)
AB/SPICH(39:32) = CNT0(39:32)
AB/SPICH(31:24) = CNT0(31:24)
AB/SPICH(23:16) = CNT0(23:16)
AB/SPICH(15:8) = CNT0(15:8)
AB/SPICH(7:0) = CNT0(7:0)
NERR
NWARN
0b00.0000
Table 62: Register layout
Example: CNT1 = 24 bit + CNT0 = 16 bit + NERR + NWARN SPI data access
SPI READ DATA AB/SPICH(39:0) + NERR + NWARN
Adr
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Measurement Data (SPI read only)
0x08
AB/SPICH(39:32) = CNT1(23:16)
AB/SPICH(31:24) = CNT1(15:8)
AB/SPICH(23:16) = CNT1(7:0)
AB/SPICH(15:8) = CNT0(15:8)
AB/SPICH(7:0) = CNT0(7:0)
NERR
NWARN
0b00.0000
Table 63: Register layout
Default 8 bit data length on remaining addresses
For configuration data (Adr.- 0x00 to 0x07), REF and
SPICH (Adr.- 0x10 to 0x25), ROM (Adr.- 0x42, 0x43)
and Status Bit (Adr.- 0x48 to 0x4A). But it is possible
to read several bytes of data consecutively if the NCS
signal is not reset and SCLK continues being clocked.
The address transmitted is then the start address which
is internally increased by 1 following each transmitted
byte.
preliminary
iC-MD 48-BIT QUADRATURE COUNTER
WITH RS422 RECEIVER AND SPI/BISS INTERFACE
Rev B1, Page 25/30
BiSS and SSI INTERFACE
The BiSS interface is a bidirectional serial interface,
which is used to read out the sensor data values and to
write and read the internal configuration registers. For
a detailed description of the protocol, see the BiSS C
specification.
It consist of 3 configurable channels:
Channel
CH0
CH1
CH2
Data
AB counter
Error
NERR
SPI Channel
NERR
UPD
TP1
TP1
TP2
NABERR
NABERR
NABERR
NABERR
Notes
Warning
NWARN
Data length
CRC polynomial CRC mode
16 + 2 bit
1000011
inverted
24 + 2 bit (default)
32 + 2 bit
48 + 2 bit
NSPICHVAL
16 + 2 bit
1000011
inverted
24 + 2 bit
32 + 2 bit
48 + 2 bit
NUPDVAL
24 + 2 bit
100101
inverted
NTPVAL
24 + 2 bit
100101
inverted
NTPVAL
24 + 2 bit
100101
inverted
NTPVAL
24 + 2 bit
100101
inverted
channel 0 data length configurable via:
CNTCFG (Adr.0x00, bit 3:0)
Table 64: BiSS Channels
The error (NERR) and warning (NWARN) bit of the
channel 0 signal the same data to be output at the pins
NERR and NWARN, it’s by default:
All three channels are enabled supply data by default
configuration, but all of them can be disable with the
registers NENCH0 (table 66) and ENCHx (table 67)
NERR: ABERR (AB signal error)
NWARN: UPDVAL (UPD Reg. up to date)
This bits can also be configured like the NERR and
NWARN outputs, with the registers MASK (table 57)
and NMASK(table 58)
Two different data can be selected for each channel,
register CHxSEL (table 65) selects the data to be transmitted by the channels.
CHxSEL
Code
Addr. 0x04; bit (7,5,3)
Function
XX0
XX1
X0X
X1X
channel 0:
channel 0:
channel 1:
channel 1:
0XX
1XX
channel 2: TP1 data
channel 2: TP2 data
Default = 0b000
AB counter data
SPI data channel
UPD data
TP1 data
Table 65: BiSS Channel Selection
NENCH0
Code
Addr. 0x04; bit (2)
Function
0
1
BiSS channel 0 enabled
BiSS channel 0 disabled
Default = 0b0
Table 66: Disable BiSS Channel 0
ENCHx
Code
Addr. 0x04; bit (6,4)
Function
X0
BiSS channel 1 disabled
0X
BiSS channel 2 disabled
Default = 0b00
Table 67: Enable BiSS Channel 1 and 2
N.B. With using BiSS protocol the device provides a
BiSS Profile ID 0x33 0x18 (0x33 in address 0x42 and
0x18 in address 0x43) that is a void "BiSS Profile ID".
preliminary
iC-MD 48-BIT QUADRATURE COUNTER
WITH RS422 RECEIVER AND SPI/BISS INTERFACE
Rev B1, Page 26/30
BiSS Device ID
0x78
Addr. 0x78 0x79; bit
(7,0)
0x4D = ASCII "M"
0x79
0x44 = ASCII "D"
R
0x7F
Table 68: BiSS Device ID
R
0x43 = ASCII "C"
Table 70: BiSS Device Manufacturer ID
BiSS Device ID
0x7A
0x7B
. . . 0x7D
BiSS Device
Addr. 0x7E 0x7F; bit
Manufacturer ID (7,0)
0x7E
0x69 = ASCII "i"
Addr. 0x7A. . . 0x7D; bit
(7,0)
0x5A = ASCII "Z" iC-MD Redesign Z
0x00 = ASCII n.a. (first redesign)
R
0x7A
0x7B
0x7C
. . . 0x7D
0x5A = ASCII "Z" iC-MD Redesign Z1
0x31 = ASCII "1"
0x00 = ASCII n.a.
0x7A
0x7B
. . . 0x7D
0x59 = ASCII "Y" iC-MD Redesign Y
0x00 = ASCII n.a.
0x7A
0x58 = ASCII "X" iC-MD Redesign X
0x7B
. . . 0x7D
0x00 = ASCII n.a. (latest redesign)
Table 69: BiSS Device ID, BiSS Device Revision
SSI Protocol
An SSI protocol is selected if the input pin SLI is open.
This enable signal has an internal digital filter of 25 µs
maximum.
A clock pulse train from a controller is used to gate out
sensor data. Between each clock pulse train there is a
SSI timeout during which fresh data is moved into the
register. Data is shifted out when the iC-MD receives
a pulse train from the controller. When the least significant bit (LSB) goes high after the SSI timeout, new
data is available to read.
The AB counter data transmitted is in the form of a
binary code (24 bit + NERR + NWARN). If the input MA
continues being clocked without SSI timeout, it will be
output a total of 94 bit with the following scheme:
Figure 12: Output data with SSI protocol
INTERFACE PRIORITY
The Configuration bit PRIOR (Adr. 0x03, bit 1), set
which interface has priority when taking place a Read/Write interface collision. It means that if BiSS and SPI
try to access to the configuration register at the same
time, then only the one with the priority will write/read
successfully the register. The error in the interface without priority will be signalized by the collision Status bit:
SPICOL or BISSCOL, Adr.0x4A, bit(1:0).
PRIOR
Code
Addr. 0x03; bit 0
Function
0
1
BiSS priority
SPI priority
Default = 0b0
Table 71: SPI Interface Priority
SPI Channel: SPI to BiSS communication
The counter register is also used for the transmission of
data from SPI to BiSS. The data exchanging take place
as following:
1. SPI writes the data to be transmitted in address
0x20 to 0x25, this data is written in the counter
registers. The data length to be transmitted is
selected by CNTCFG (Table 13) and can be configured as 16, 24, 32 or 48-bit
2. After the writing process, the bit SPICHVAL is set
to 1 and read via BiSS as Warning bit of channel
0.
3. BiSS reads out the channel 0, the data written
via SPI and two status bits, NERR and NWARN
which indicates if the read data is valid.
preliminary
iC-MD 48-BIT QUADRATURE COUNTER
WITH RS422 RECEIVER AND SPI/BISS INTERFACE
Rev B1, Page 27/30
ACTUATOR OUTPUTS, ERROR and WARNING I/O PINS
The pins NERR and NWARN are low active bidirectional ports (open collector outputs and digital inputs).
error/warning will be read by the controller via SPI or
BiSS as status bits.
The inputs are used to latch an external error/warning (tables 52 and 53) and makes possible that this
The instruction bits ACT0 and ACT1 (tables 42 and 43)
set the value of the output pins ACT0 and ACT1.
APPLICATIONS NOTES
RS422 12 V capable inputs setup
The following figure 13 shows the resistors configuration used for a 12 V capable RS422 inputs. (see Fig. 13).
VDD
0..5.5V
VDD
AP
1kΩ
+
R
1kΩ
R
1kΩ
1kΩ
R
4.7kΩ
R
1kΩ
AN
AN
BP
BP
BP
+
1kΩ
1kΩ
Z0
24-bit REF Counter
REFCNT(23:0)
Z Signal
COUNT
Reset
RESAB
1x48bit Counter
1x32bit Counter
1,2x24bit Counters
1,2,3x16bit Counters
BD
-
R
4.7kΩ
R
-12..12V
AD
AN
R
R
-12..12V
A0
-
R
4.7kΩ
BPR
AP
B0
R
-12..12V
-12..12V
BNR
AP
4.7kΩ
APR
ANR
R
R
RS-422 Receivers
1kΩ
BN
BN
BN
CP
CP
CP
1kΩ
B1
4.7kΩ
-12..12V
+
R
4.7kΩ
1kΩ
1kΩ
CN
CN
Z
CBZ
&
Z1
1
CD
-
R
R
-12..12V
R
CPR
CNR
R
R
A1
1kΩ
AB(47:0)
D Q
A2
B2
CN
CNTFLG
TPI
Figure 13: RS422 12 V capable configuration
preliminary
iC-MD 48-BIT QUADRATURE COUNTER
WITH RS422 RECEIVER AND SPI/BISS INTERFACE
Rev B1, Page 28/30
VDD
VDD
RS-422/TTL RECEIVERS
AP
AP
REFERENCE-TO-REFERENCE
COUNTER 24 Bit
MULTIPLEXER
AND
STATUS
UPD Register
+
-
NERR
ERROR
REGISTERS
REFCNT
NWARN
REF Register
AN
AN
DATA I/O
WARNING
BP
BP
+
A0
-
B0
BN
BN
CNT 1
CNT 2
24 Bit
-
-
A1
24 Bit
24 Bit
-
B1
48 Bit
-
-
Z1
32 Bit
-
-
32 Bit
16 Bit
-
A2
16 Bit
-
-
B2
16 Bit
16 Bit
-
16 Bit
16 Bit
16 Bit
R
R
R
+
CN
COUNTERS
CNT 0
Z0
CP
CONFIGURABLE
ACTUATOR OUTPUT
ACT1
ACT0
SPI INTERFACE
SCK
SCK
NCS
NCS
MOSI
MOSI
MISO
MISO
TOUCH PROBE
SERIAL INTERFACE
ENTP
TP2
BiSS C
SLO
SLI
SSI
R
&
R
iC-MD
TPI
TP1
MA
GND
GND
Figure 14: SPI only operation with unused constant pulled index input
Optional ”SPI only” operation setup
Figure 14 shows an SPI only configuration. All trigger events or status requests need to be accessed over the SPI
interface.
• Default State of the BiSS Interface
– Pull up resistor on input pin MA
– Pull down resistor on input pin SLI
• On unused pin TPI:
– Pull up resistor on input pin TPI
Optional unused index setup
Figure 14 shows a deactivated index input pins biasing for CP CN on differential input signals. The logic state of
the index input is then 0.
• On unused counter pins CP CN with RS-422 receiver setup:
– Pull down resistor on the positive input pin CP
– Pull up resistor on the positive input pin CN
– Consider INVZ0 = 0 signal configuration
– Consider CFGZ = 0 signal configuration
• On unused counter pins with TTL/CMOS receiver setup:
– Pull down resistor on input pin BP and CN
– Consider INVZx = 0 signal configuration
– Consider CFGZ = 0 signal configuration
preliminary
iC-MD 48-BIT QUADRATURE COUNTER
WITH RS422 RECEIVER AND SPI/BISS INTERFACE
Rev B1, Page 29/30
DESIGN REVIEW: Notes On Chip Functions
iC-MD X
No. Function,
Parameter/Code
Description and Application Hints
1
No further notes at time of printing.
Table 72: Notes on chip functions regarding iC-MD chip
release X.
REVISION HISTORY
Rel.
Rel. Date∗
A1
2010-11-02
Rel.
Rel. Date∗
A2
2012-02-22
Rel.
Rel. Date∗
A3
2013-03-04
Chapter
Modification
Page
Initial release
all
Modification
Page
Tables added, more detailed explanations
n.a.
Modification
Page
New title: 48-BIT QUADRATURE COUNTER
1
DESCRIPTION
BUA info added
2
REVISION HISTORY
REVISION HISTORY added
26
Chapter
Chapter
Chapter
Rel.
Rel. Date∗
Modification
Page
A4
2015-02-18 STATUS REGISTER and
ERROR/WARNING INDICATION
MASK and NMASK figures added
20, 21
Rel.
Rel. Date∗
Chapter
Modification
Page
B1
2017-3-30
ELECTRICAL
CHARACTERISTICS
item 004, 201, 604 and C01 updated
5, 6
ELECTRICAL
CHARACTERISTICS
ENSSI replaces ENBISS, item i107 -113 removed, figure 4 removed,
operating conditions updated,
8
REGISTER MAP
Added ”SPI and BiSS read only”
10
COUNTER CONFIGURATION
Table 13 address bits (2:0) updated
12
BiSS and SSI INTERFACE
BiSS identifier details added
26
BiSS and SSI INTERFACE
Table 70 updated 0x7E 0x7F for BiSS Device Manufacturer
26
INTERFACE PRIORITY
Table 71 address bit (0) updated
26
REVISION HISTORY
REVISION HISTORY updated
29
iC-Haus expressly reserves the right to change its products and/or specifications. An Infoletter gives details as to any amendments and additions made to the
relevant current specifications on our internet website www.ichaus.com/infoletter and is automatically generated and shall be sent to registered users by email.
Copying – even as an excerpt – is only permitted with iC-Haus’ approval in writing and precise reference to source.
The data specified is intended solely for the purpose of product description and shall represent the usual quality of the product. In case the specifications contain
obvious mistakes e.g. in writing or calculation, iC-Haus reserves the right to correct the specification and no liability arises insofar that the specification was from
a third party view obviously not reliable. There shall be no claims based on defects as to quality in cases of insignificant deviations from the specifications or in
case of only minor impairment of usability.
No representations or warranties, either expressed or implied, of merchantability, fitness for a particular purpose or of any other nature are made hereunder
with respect to information/specification or the products to which information refers and no guarantee with respect to compliance to the intended use is given. In
particular, this also applies to the stated possible applications or areas of applications of the product.
iC-Haus products are not designed for and must not be used in connection with any applications where the failure of such products would reasonably be
expected to result in significant personal injury or death (Safety-Critical Applications) without iC-Haus’ specific written consent. Safety-Critical Applications
include, without limitation, life support devices and systems. iC-Haus products are not designed nor intended for use in military or aerospace applications or
environments or in automotive applications unless specifically designated for such use by iC-Haus.
iC-Haus conveys no patent, copyright, mask work right or other trade mark right to this product. iC-Haus assumes no liability for any patent and/or other trade
mark rights of a third party resulting from processing or handling of the product and/or any other use of the product.
Software and its documentation is provided by iC-Haus GmbH or contributors "AS IS" and is subject to the ZVEI General Conditions for the Supply of Products
and Services with iC-Haus amendments and the ZVEI Software clause with iC-Haus amendments (www.ichaus.com/EULA).
∗
Release Date format: YYYY-MM-DD
preliminary
iC-MD 48-BIT QUADRATURE COUNTER
WITH RS422 RECEIVER AND SPI/BISS INTERFACE
Rev B1, Page 30/30
ORDERING INFORMATION
Type
Package
Options
Order Designation
iC-MD
TSSOP20
iC-MD TSSOP20
Evaluation
Board iC-MD
100 mm x 80 mm PCB
iC-MD EVAL MD1D
Please send your purchase orders to our order handling team:
Fax: +49 (0) 61 35 - 92 92 - 692
E-Mail: [email protected]
For technical support, information about prices and terms of delivery please contact:
iC-Haus GmbH
Am Kuemmerling 18
D-55294 Bodenheim
GERMANY
Tel.: +49 (0) 61 35 - 92 92 - 0
Fax: +49 (0) 61 35 - 92 92 - 192
Web: http://www.ichaus.com
E-Mail: [email protected]
Appointed local distributors: http://www.ichaus.com/sales_partners