ICSI IC41LV16257S-50TI 256k x 16 (4-mbit) dynamic ram with fast page mode Datasheet

IC41C16257/IC41C16257S
IC41LV16257/IC41LV16257S
Document Title
256Kx16 bit Dynamic RAM with Fast Page Mode
Revision History
Revision No
History
Draft Date
0A
Initial Draft
August 11,2001
Remark
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc.
DR021-0A 08/11/2001
1
IC41C16257/IC41C16257S
IC41LV16257/IC41LV16257S
256K x 16 (4-MBIT) DYNAMIC RAM
WITH FAST PAGE MODE
FEATURES
•
•
•
•
•
•
•
•
•
DESCRIPTION
The ICSI IC41C16257 and the IC41LV16257 are 262,144
Fast access and cycle time
x 16-bit high-performance CMOS Dynamic Random Access
TTL compatible inputs and outputs
Memory. Fast Page Mode allows 512 random accesses
Refresh Interval: 512 cycles/8 ms
within a single row with access cycle time as short as 12 ns
per 16-bit word. The Byte Write control, of upper and lower
Refresh Mode: RAS-Only, CAS-before-RAS
byte, makes these devices ideal for use in 16-, 32-bit wide
(CBR), Hidden
data bus systems.
Self Refresh Mode: 512 cycles/64 ms (S version
These features make the IC41C16257 and the IC41LV16257
only)
ideally suited for high band-width graphics, digital signal
JEDEC standard pinout
processing, high-performance computing systems, and
peripheral applications.
Single power supply:
— 5V ± 10% (IC41C16257)
The IC41C16257 and the IC41LV16257 are packaged in a
40-pin, 400mil SOJ and TSOP-2.
— 3.3V ± 10% (IC41LV16257)
Byte Write and Byte Read operation via
KEY TIMING PARAMETERS
two CAS
Parameter
-35
-50
-60 Unit
Available in 40-pin SOJ and TSOP-2
PIN CONFIGURATIONS
40-Pin TSOP-2
Max. RAS Access Time (tRAC)
Max. CAS Access Time (tCAC)
Max. Column Address Access Time (tAA)
Min. Fast Page Mode Cycle Time (tPC)
35
10
18
12
50
14
25
20
60
15
30
25
ns
ns
ns
ns
Min. Read/Write Cycle Time (tRC)
60
90
110
ns
40-Pin SOJ
PIN DESCRIPTIONS
A0-A8
Address Inputs
I/O0-I/O15
Data Inputs/Outputs
WE
Write Enable
OE
Output Enable
RAS
Row Address Strobe
UCAS
Upper Column Address
Strobe
LCAS
Lower Column Address
Strobe
Vcc
Power
GND
Ground
NC
No Connection
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
2
Integrated Circuit Solution Inc.
DR021-0A 08/11/2001
IC41C16257/IC41C16257S
IC41LV16257/IC41LV16257S
FUNCTIONAL BLOCK DIAGRAM
Integrated Circuit Solution Inc.
DR021-0A 08/11/2001
3
IC41C16257/IC41C16257S
IC41LV16257/IC41LV16257S
TRUTH TABLE
Function
Standby
Read: Word
Read: Lower Byte
RAS
H
L
L
Read: Upper Byte
L
H
Write: Word (Early Write)
Write: Lower Byte (Early Write)
L
L
Write: Upper Byte (Early Write)
L
Read-Write(1,2)
Hidden Refresh2)
RAS-Only Refresh
CBR Refresh(3)
L
Read L→H→L
Write L→H→L
L
H→L
LCAS UCAS
H
H
L
L
L
H
WE
X
H
H
OE
X
L
L
Address tR/tC
X
ROW/COL
ROW/COL
L
H
L
ROW/COL
L
L
L
H
L
L
X
X
ROW/COL
ROW/COL
H
L
L
X
ROW/COL
L
L
L
H
L
L
L
L
H
L
H→L
H
L
X
X
L→H
L
X
X
X
ROW/COL
ROW/COL
ROW/COL
ROW/NA
X
I/O
High-Z
DOUT
Lower Byte, DOUT
Upper Byte, High-Z
Lower Byte, High-Z
Upper Byte, DOUT
DIN
Lower Byte, DIN
Upper Byte, High-Z
Lower Byte, High-Z
Upper Byte, DIN
DOUT, DIN
DOUT
DOUT
High-Z
High-Z
Notes:
1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active).
2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active).
3. At least one of the two CAS signals must be active (LCAS or UCAS).
4
Integrated Circuit Solution Inc.
DR021-0A 08/11/2001
IC41C16257/IC41C16257S
IC41LV16257/IC41LV16257S
FUNCTIONAL DESCRIPTION
The IC41C16257 and the IC41LV16257 are CMOS DRAMs
optimized for high-speed bandwidth, low-power applications.
During READ or WRITE cycles, each bit is uniquely
addressed through the 18 address bits. These are entered
nine bits (A0-A8) at a time. The row address is latched by the
Row Address Strobe (RAS). The column address is latched
by the Column Address Strobe (CAS). RAS is used to latch
the first nine bits and CAS is used to latch the latter nine bits.
The IC41C16257 and the IC41LV16257 have two CAS
controls, LCAS and UCAS. The LCAS and UCAS inputs
internally generate a CAS signal functioning in an identical
manner to the single CAS input on the other 256K x 16
DRAMs. The key difference is that each CAS controls its
corresponding I/O tristate logic (in conjunction with OE and
WE and RAS). LCAS controls
I/O0 - I/O7 and UCAS
controls I/O8 - I/O15.
The IC41C16257/IC41LV16257 CAS function is determined
by the first CAS (LCAS or UCAS) transitioning LOW and the
last transitioning back HIGH. The two CAS controls give the
IC41C16257 both BYTE READ and BYTE WRITE cycle
capabilities.
Memory Cycle
A memory cycle is initiated by bringing RAS LOW and it is
terminated by returning both RAS and CAS HIGH. To
ensure proper device operation and data integrity any
memory cycle, once initiated, must not be ended or aborted
before the minimum tRAS time has expired. A new cycle must
not be initiated until the minimum precharge time tRP, tCP has
elapsed.
Read Cycle
A read cycle is initiated by the falling edge of CAS or OE,
whichever occurs last, while holding WE HIGH. The column
address must be held for a minimum time specified by tAR.
Data Out becomes valid only when tRAC, tAA, tCAC and tOE are
all satisfied. As a result, the access time is dependent on the
timing relationships between these parameters.
Write Cycle
A write cycle is initiated by the falling edge of CAS and WE,
whichever occurs last. The input data must be valid at or
before the falling edge of CAS or WE, whichever occurs last.
Refresh Cycle
To retain data, 512 refresh cycles are required in each
8 ms period. There are two ways to refresh the memory:
1. By clocking each of the 512 row addresses (A0 through
A8) with RAS at least once every 8 ms. Any read, write,
read-modify-write or RAS-only cycle refreshes the addressed row.
2. Using a CAS-before-RAS refresh cycle. CAS-beforeRAS refresh is activated by the falling edge of RAS, while
holding CAS LOW. In CAS-before-RAS refresh cycle, an
internal 9-bit counter provides the row addresses and the
external address inputs are ignored.
CAS-before-RAS is a refresh-only mode and no data access
or device selection is allowed. Thus, the output remains in
the High-Z state during the cycle.
Self Refresh Cycle(1)
The Self Refresh allows the user a dynamic refresh, data
retention mode at the extended refresh period of 64 ms. i.e.,
125 µs per row when using distributed CBR refreshes. The
feature also allows the user the choice of a fully static, low
power data retention mode. The optional Self Refresh feature
is initiated by performing a CBR Refresh cycle and holding
RAS LOW for the specified tRASS.
The Self Refresh mode is terminated by driving RAS HIGH for
a minimum time of tRPS. This delay allows for the completion
of any internal refresh cycles that may be in process at the
time of the RAS LOW-to-HIGH transition. If the DRAM
controller uses a distributed refresh sequence, a burst refresh
is not required upon exiting Self Refresh.
However, if the DRAM controller utilizes a RAS-only or burst
refresh sequence, all 512 rows must be refreshed within the
average internal refresh rate, prior to the resumption of normal
operation.
Power-On
After application of the V CC supply, an initial pause of
200 µs is required followed by a minimum of eight initialization
cycles (any combination of cycles containing a RAS signal).
During power-on, it is recommended that RAS track with VCC
or be held at a valid VIH to avoid current surges.
Note:
1.Self Refresh is for Sversion only.
Integrated Circuit Solution Inc.
DR021-0A 08/11/2001
5
IC41C16257/IC41C16257S
IC41LV16257/IC41LV16257S
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Parameters
VT
Voltage on Any Pin Relative to GND
VCC
Supply Voltage
IOUT
PD
TA
Output Current
Power DICSIpation
Operation Temperature
TSTG
Storage Temperature
5V
3.3V
5V
3.3V
Com.
Ind.
Rating
Unit
–1.0 to +7.0
–0.5 to +4.6
–1.0 to +7.0
–0.5 to +4.6
50
1
0 to +70
-40 to +85
–55 to +125
V
V
V
V
mA
W
o
C
o
C
o
C
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND)
Symbol
Parameter
VCC
Supply Voltage
VIH
Input High Voltage
VIL
Input Low Voltage
TA
Ambient Temperature
5V
3.3V
5V
3.3V
5V
3.3V
Com.
Ind.
Min.
Typ.
Max.
Unit
4.5
3.0
2.4
2.0
–1.0
–0.3
0
–40
5.0
3.3
—
—
—
—
—
—
5.5
3.6
VCC + 1.0
VCC + 0.3
0.8
0.8
70
85
V
V
V
V
V
V
o
C
o
C
CAPACITANCE(1,2)
Symbol
Parameter
CIN1
CIN2
CIO
Input Capacitance: A0-A8
Input Capacitance: RAS, UCAS, LCAS, WE, OE
Data Input/Output Capacitance: I/O0-I/O15
Max.
Unit
5
7
7
pF
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25oC, f = 1 MHz, VCC = 5.0V + 10%, or VCC = 3.3V + 10%.
6
Integrated Circuit Solution Inc.
DR021-0A 08/11/2001
IC41C16257/IC41C16257S
IC41LV16257/IC41LV16257S
ELECTRICAL CHARACTERISTICS(1) (Recommended Operation Conditions unless otherwise noted.)
Symbol Parameter
Test Condition
IIL
Input Leakage Current
IIO
Output Leakage Current
VOH
VOL
Output High Voltage Level
Output Low Voltage Level
Any input 0V ≤ VIN ≤ Vcc
Other inputs not under test = 0V
Output is disabled (Hi-Z)
0V ≤ VOUT ≤ Vcc
IOH = –2.5 mA
IOL = +2.1 mA
ICC1
Stand-by Current: TTL
RAS, LCAS, UCAS ≥ VIH
ICC1
ICC2
ICC2
ICC3
ICC4
ICC5
ICC6
ICCS
Min.
Max.
Unit
–10
10
µA
–10
10
µA
2.4
—
—
0.4
V
V
Com. 5V
Ind. 5V
Stand-by Current: TTL
RAS, LCAS, UCAS ≥ VIH
Com. 3.3V
Ind. 3.3V
Stand-by Current: CMOS
RAS, LCAS, UCAS ≥ VCC – 0.2V
5V
Stand-by Current: CMOS
RAS, LCAS, UCAS ≥ VCC – 0.2V
3.3V
Operating Current:
RAS, LCAS, UCAS,
-35
Random Read/Write(2,3,4)
Address Cycling, tRC = tRC (min.)
-50
Average Power Supply Current
-60
Operating Current:
RAS = VIL, LCAS, UCAS,
-35
Fast Page Mode(2,3,4)
Cycling tPC = tPC (min.)
-50
Average Power Supply Current
-60
Refresh Current:
RAS Cycling, LCAS, UCAS ≥ VIH
-35
RAS-Only(2,3)
tRC = tRC (min.)
-50
Average Power Supply Current
-60
Refresh Current:
RAS, LCAS, UCAS Cycling
-35
CBR(2,3,5)
tRC = tRC (min.)
-50
Average Power Supply Current
-60
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
3
1
2
1
0.5
230
180
170
220
170
160
230
180
170
230
180
170
mA
mA
mA
mA
mA
mA
mA
Self Refresh current(6)
—
—
300
300
Self Refresh Mode
Speed
5V
3.3V
mA
mA
mA
µA
µA
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device
operation is assured.The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each fast page cycle.
5. Enables on-chip refresh and address counters.
6. ICCS is for S version only.
Integrated Circuit Solution Inc.
DR021-0A 08/11/2001
7
IC41C16257/IC41C16257S
IC41LV16257/IC41LV16257S
AC CHARACTERISTICS(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
Symbol
Parameter
tRC
tRAC
tCAC
tAA
tRAS
tRP
tCAS
tCP
tCSH
tRCD
tASR
tRAH
tASC
tCAH
tAR
Random READ or WRITE Cycle Time
Access Time from RAS(6, 7)
Access Time from CAS(6, 8, 15)
Access Time from Column-Address(6)
RAS Pulse Width
RAS Precharge Time
CAS Pulse Width(26)
CAS Precharge Time(9, 25)
CAS Hold Time (21)
RAS to CAS Delay Time(10, 20)
Row-Address Setup Time
Row-Address Hold Time
Column-Address Setup Time(20)
Column-Address Hold Time(20)
Column-Address Hold Time
(referenced to RAS)
RAS to Column-Address Delay Time(11)
Column-Address to RAS Lead Time
RAS to CAS Precharge Time
RAS Hold Time(27)
CAS to Output in Low-Z(15, 29)
CAS to RAS Precharge Time(21)
Output Disable Time(19, 28, 29)
Output Enable Time(15, 16)
OE LOW to CAS HIGH Setup Time
Read Command Setup Time(17, 20)
Read Command Hold Time
(referenced to RAS)(12)
Read Command Hold Time
(referenced to CAS)(12, 17, 21)
Write Command Hold Time(17, 27)
Write Command Hold Time
(referenced to RAS)(17)
Write Command Pulse Width(17)
Write Command to RAS Lead Time(17)
Write Command to CAS Lead Time(17, 21)
Write Command Setup Time(14, 17, 20)
Data-in Hold Time (referenced to RAS)
tRAD
tRAL
tRPC
tRSH
tCLZ
tCRP
tOD
tOE
tOES
tRCS
tRRH
tRCH
tWCH
tWCR
tWP
tRWL
tCWL
tWCS
tDHR
-35
Min. Max.
-50
Min. Max.
-60
Min. Max.
Units
60
—
—
—
35
20
6
5
35
11
0
6
0
6
30
—
35
10
18
10K
—
10K
—
—
28
—
—
—
—
—
90
—
—
—
50
30
8
8
50
19
0
8
0
8
40
—
50
14
25
10K
—
10K
—
—
36
—
—
—
—
—
110
—
—
—
60
40
10
10
60
20
0
10
0
10
40
—
60
15
30
10K
—
10K
—
—
45
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
12
18
0
8
3
5
3
—
5
0
0
20
—
—
—
—
—
15
10
—
—
—
14
25
0
14
3
5
3
—
5
0
0
25
—
—
—
—
—
15
15
—
—
—
15
30
0
15
3
5
3
—
5
0
0
30
—
—
—
—
—
15
15
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
—
0
—
0
—
ns
5
30
—
—
8
40
—
—
10
50
—
—
ns
ns
5
8
8
0
30
—
—
—
—
—
8
14
14
0
40
—
—
—
—
—
10
15
15
0
45
—
—
—
—
—
ns
ns
ns
ns
ns
(Continued)
8
Integrated Circuit Solution Inc.
DR021-0A 08/11/2001
IC41C16257/IC41C16257S
IC41LV16257/IC41LV16257S
AC CHARACTERISTICS(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
-35
Min. Max.
Symbol Parameter
tACH
tOEH
tDS
tDH
tRWC
tRWD
tCWD
tAWD
tPC
tRASP
tCPA
tPRWC
tOFF
tCLCH
tCSR
tCHR
tORD
tREF
tT
Column-Address Setup Time to CAS
Precharge during WRITE Cycle
OE Hold Time from WE during
READ-MODIFY-WRITE cycle(18)
Data-In Setup Time(15, 22)
Data-In Hold Time(15, 22)
READ-MODIFY-WRITE Cycle Time
RAS to WE Delay Time during
READ-MODIFY-WRITE Cycle(14)
CAS to WE Delay Time(14, 20)
Column-Address to WE Delay Time(14)
Fast Page Mode READ or WRITE
Cycle Time(24)
Fast Page Mode RAS Pulse Width
Access Time from CAS Precharge(15)
Fast Page Mode READ-WRITE Cycle Time(24)
Output Buffer Turn-Off Delay from
CAS or RAS(13,15,19, 29)
Last CAS going LOW to First CAS
returning HIGH(23)
CAS Setup Time (CBR REFRESH)(30, 20)
CAS Hold Time (CBR REFRESH)(30, 21)
OE Setup Time prior to RAS during
HIDDEN REFRESH Cycle
Refresh Period (512 Cycles)
Transition Time (Rise or Fall)(2, 3)
-50
Min. Max.
-60
Min. Max.
Units
15
—
15
—
15
—
ns
8
—
10
—
15
—
ns
0
6
80
45
—
—
—
—
0
8
125
70
—
—
—
—
0
10
140
80
—
—
—
—
ns
ns
ns
ns
25
30
12
—
—
—
34
42
20
—
—
—
36
49
25
—
—
—
ns
ns
ns
35 100K
— 21
40 —
3
15
50 100K
— 27
47 —
3
15
60 100K
— 34
56 —
3
15
ns
ns
ns
ns
10
—
10
—
10
—
ns
8
8
0
—
—
—
10
10
0
—
—
—
10
10
0
—
—
—
ns
ns
ns
—
1
8
50
—
1
8
50
—
1
8
50
ms
ns
AC TEST CONDITIONS
Output load:
Two TTL Loads and 50 pF (Vcc = 5.0V ±10%)
One TTL Load and 50 pF (Vcc = 3.3V ±10%)
Input timing reference levels: VIH = 2.4V, VIL = 0.8V (Vcc = 5.0V ±10%);
VIH = 2.0V, VIL = 0.8V (Vcc = 3.3V ±10%)
Output timing reference levels: VOH = 2.0V, VOL = 0.8V (Vcc = 5V ±10%, 3.3V ±10%)
Integrated Circuit Solution Inc.
DR021-0A 08/11/2001
9
IC41C16257/IC41C16257S
IC41LV16257/IC41LV16257S
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between VIH
and VIL (or between VIL and VIH) and assume to be 1 ns for all inputs.
3. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH)
in a monotonic manner.
4. If CAS and RAS = VIH, data output is High-Z.
5. If CAS = VIL, data output may contain data from the last valid READ cycle.
6. Measured with a load equivalent to one TTL gate and 50 pF.
7. Assumes that tRCD ≤ tRCD (MAX). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase
by the amount that tRCD exceeds the value shown.
8. Assumes that tRCD ≥ tRCD (MAX).
9. If CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear the
data output buffer, CAS and RAS must be pulsed for tCP.
10. Operation with the tRCD (MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point only; if tRCD
is greater than the specified tRCD (MAX) limit, access time is controlled exclusively by tCAC.
11. Operation within the tRAD (MAX) limit ensures that tRCD (MAX) can be met. tRAD (MAX) is specified as a reference point only; if tRAD
is greater than the specified tRAD (MAX) limit, access time is controlled exclusively by tAA.
12. Either tRCH or tRRH must be satisfied for a READ cycle.
13. tOFF (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL.
14. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If tWCS ≥ tWCS
(MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If tRWD ≥ tRWD
(MIN), tAWD ≥ tAWD (MIN) and tCWD ≥ tCWD (MIN), the cycle is a READ-WRITE cycle and the data output will contain data read from
the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back
to VIH) is indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled) cycle.
15. Output parameter (I/O) is referenced to corresponding CAS input, I/O0-I/O7 by LCAS and I/O8-I/O15 by UCAS.
16. During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a
LATE WRITE or READ-MODIFY-WRITE is not possible.
17. Write command is defined as WE going low.
18. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOD and tOEH met (OE HIGH during WRITE cycle) in order to ensure
that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS remains LOW
and OE is taken back to LOW after tOEH is met.
19. The I/Os are in open during READ cycles once tOD or tOFF occur.
20. The first χCAS edge to transition LOW.
21. The last χCAS edge to transition HIGH.
22. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READMODIFY-WRITE cycles.
23. Last falling χCAS edge to first rising χCAS edge.
24. Last rising χCAS edge to next cycleÕs last rising χCAS edge.
25. Last rising χCAS edge to first falling χCAS edge.
26. Each χCAS must meet minimum pulse width.
27. Last χCAS to go LOW.
28. I/Os controlled, regardless UCAS and LCAS.
29. The 3 ns minimum is a parameter guaranteed by design.
30. Enables on-chip refresh and address counters.
10
Integrated Circuit Solution Inc.
DR021-0A 08/11/2001
IC41C16257/IC41C16257S
IC41LV16257/IC41LV16257S
READ CYCLE
Note:
1. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last.
Integrated Circuit Solution Inc.
DR021-0A 08/11/2001
11
IC41C16257/IC41C16257S
IC41LV16257/IC41LV16257S
READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles)
12
Integrated Circuit Solution Inc.
DR021-0A 08/11/2001
IC41C16257/IC41C16257S
IC41LV16257/IC41LV16257S
EARLY WRITE CYCLE (OE = DON'T CARE)
Integrated Circuit Solution Inc.
DR021-0A 08/11/2001
13
IC41C16257/IC41C16257S
IC41LV16257/IC41LV16257S
FAST PAGE MODE READ CYCLE
14
Integrated Circuit Solution Inc.
DR021-0A 08/11/2001
IC41C16257/IC41C16257S
IC41LV16257/IC41LV16257S
FAST PAGE MODE READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles)
Integrated Circuit Solution Inc.
DR021-0A 08/11/2001
15
IC41C16257/IC41C16257S
IC41LV16257/IC41LV16257S
FAST PAGE MODE EARLY WRITE CYCLE
AC WAVEFORMS
RAS
RAS-ONLY REFRESH CYCLE (OE, WE = DON'T CARE)
16
Integrated Circuit Solution Inc.
DR021-0A 08/11/2001
IC41C16257/IC41C16257S
IC41LV16257/IC41LV16257S
CBR REFRESH CYCLE (Addresses; WE, OE = DON'T CARE)
HIDDEN REFRESH CYCLE(1) (WE = HIGH; OE = LOW)
Notes:
1. A Hidden Refresh may also be performed after a Write Cycle. In this case, WE = LOW and OE = HIGH.
2. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last.
Integrated Circuit Solution Inc.
DR021-0A 08/11/2001
17
IC41C16257/IC41C16257S
IC41LV16257/IC41LV16257S
SELF REFRESH CYCLE (Addresses : WE and OE = DON'T CARE)
TIMING PARAMETERS
Symbol
Min.
tCHD
tCP
tCSR
tRASS
tRP
tRPS
tRPC
8
5
8
100
20
64
5
18
-35
Max.
—
—
—
—
—
—
—
Min.
10
9
10
100
30
84
5
-50
Max.
—
—
—
—
—
—
—
Min.
10
9
10
100
40
104
5
-60
Max.
—
—
—
—
—
—
—
Units
ns
ns
ns
µs
ns
ns
ns
Integrated Circuit Solution Inc.
DR021-0A 08/11/2001
IC41C16257/IC41C16257S
IC41LV16257/IC41LV16257S
ORDERING INFORMATION
IC41C16257
Commercial Range: 0°°C to 70°°C
Speed (ns) Order Part No.
35
50
60
IC41C16257-35K
IC41C16257-35T
IC41C16257-50K
IC41C16257-50T
IC41C16257-60K
IC41C16257-60T
Package
400mil
400mil
400mil
400mil
400mil
400mil
SOJ
TSOP-2
SOJ
TSOP-2
SOJ
TSOP-2
ORDERING INFORMATION
IC41LV16257
Commercial Range: 0°°C to 70°°C
Speed (ns) Order Part No.
35
50
60
IC41LV16257-35K
IC41LV16257-35T
IC41LV16257-50K
IC41LV16257-50T
IS41LV16257-60K
IC41LV16257-60T
Package
400mil SOJ
400mil TSOP-2
400mil SOJ
400mil TSOP-2
400mil SOJ
400mil TSOP-2
ORDERING INFORMATION
IC41C16257S
Commercial Range: 0°°C to 70°°C
Speed(ns)
35
50
60
OrderPartNo.
Package
IC41C16257S-35K
IC41C16257S-35T
IC41C16257S-50K
IC41C16257S-50T
IC41C16257S-60K
IC41C16257S-60T
400mil SOJ
400mil TSOP-2
400mil SOJ
400mil TSOP-2
400mil SOJ
400mil TSOP-2
ORDERING INFORMATION
IC41LV16257S
Commercial Range: 0°°C to 70°°C
Speed(ns)
35
50
60
OrderPartNo.
Package
IC41LV16257S-35K
IC41LV16257S-35T
IC41LV16257S-50K
IC41LV16257S-50T
IS41LV16257S-60K
IC41LV16257S-60T
400mil SOJ
400mil TSOP-2
400mil SOJ
400mil TSOP-2
400mil SOJ
400mil TSOP-2
Integrated Circuit Solution Inc.
DR021-0A 08/11/2001
Industrial Range: -40°°C to 85°°C
Speed (ns) Order Part No.
35
50
60
IC41C16257-35KI
IC41C16257-35TI
IC41C16257-50KI
IC41C16257-50TI
IC41C16257-60KI
IC41C16257-60TI
Package
400mil
400mil
400mil
400mil
400mil
400mil
SOJ
TSOP-2
SOJ
TSOP-2
SOJ
TSOP-2
Industrial Range: -40°°C to 85°°C
Speed (ns) Order Part No.
35
50
60
IC41LV16257-35KI
IC41LV16257-35TI
IC41LV16257-50KI
IC41LV16257-50TI
IC41LV16257-60KI
IC41LV16257-60TI
Package
400mil
400mil
400mil
400mil
400mil
400mil
SOJ
TSOP-2
SOJ
TSOP-2
SOJ
TSOP-2
Industrial Range: -40°°C to 85°°C
Speed(ns)
35
50
60
Order Part No.
Package
IC41C16257S-35KI
IC41C16257S-35TI
IC41C16257S-50KI
IC41C16257S-50TI
IC41C16257S-60KI
IC41C16257S-60TI
400mil SOJ
400mil TSOP-2
400mil SOJ
400mil TSOP-2
400mil SOJ
400mil TSOP-2
Industrial Range: -40°°C to 85°°C
Speed(ns)
35
50
60
OrderPartNo.
Package
IC41LV16257S-35KI
IC41LV16257S-35TI
IC41LV16257S-50KI
IC41LV16257S-50TI
IC41LV16257S-60KI
IC41LV16257S-60TI
400mil SOJ
400mil TSOP-2
400mil SOJ
400mil TSOP-2
400mil SOJ
400mil TSOP-2
19
IC41C16257/IC41C16257S
IC41LV16257/IC41LV16257S
Integrated Circuit Solution Inc.
HEADQUARTER:
NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,
HSIN-CHU, TAIWAN, R.O.C.
TEL: 886-3-5780333
Fax: 886-3-5783000
BRANCH OFFICE:
7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD,
HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.
TEL: 886-2-26962140
FAX: 886-2-26962252
http://www.icsi.com.tw
20
Integrated Circuit Solution Inc.
DR021-0A 08/11/2001
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