ICST ICS5314BI01L Low skew, 1-to-5 differential-to-2.5v/3.3v lvpecl fanout buffer Datasheet

Integrated
Circuit
Systems, Inc.
ICS85314I-01
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS85314I-01 is a low skew, high performance 1-to-5 Differential-to-2.5V/3.3V LVPECL
HiPerClockS™
Fanout Buffer and a member of the HiPerClockS™
family of High Performance Clock Solutions from
ICS. The ICS85314I-01 has two selectable clock
inputs. The CLK0, nCLK0 pair can accept most standard
differential input levels. The single-ended CLK1 can accept
LVCMOS or LVTTL input levels. The clock enable is internally
synchronized to eliminate runt clock pulses on the outputs
during asynchronous assertion/deassertion of the clock
enable pin.
• 5 differential 2.5V/3.3V LVPECL outputs
Guaranteed output and part-to-part skew characteristics
make the ICS85314I-01 ideal for those applications demanding well defined performance and repeatability.
• Output skew: 30ps (maximum), TSSOP package
50ps (maximum), SOIC package
ICS
• Selectable differential CLK0, nCLK0 or LVCMOS inputs
• CLK0, nCLK0 pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
• CLK1 can accept the following input levels:
LVCMOS or LVTTL
• Maximum output frequency: 700MHz
• Translates any single-ended input signal to 3.3V
LVPECL levels with resistor bias on nCLK input
• Part-to-part skew: 350ps (maximum)
• Propagation delay: 1.8ns (maximum)
• RMS phase jitter @ 155.52MHz (12kHz - 20MHz):
0.05ps (typical)
• LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.8V, VEE = 0V
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS-compliant
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
D
nCLK_EN
Q
LE
CLK0
nCLK0
CLK1
00
1
Q0
nQ0
1
Q1
nQ1
CLK_SEL
Q2
nQ2
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VCC
nCLK_EN
VCC
nc
CLK1
CLK0
nCLK0
nc
CLK_SEL
VEE
ICS85314I-01
Q3
nQ3
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm Package Body
G Package
Top View
Q4
nQ4
ICS85314I-01
20-Lead SOIC
7.5mm x 12.8mm x 2.3mm Package Body
M Package
Top View
85314BGI-01
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1
REV. E SEPTEMBER 23, 2005
ICS85314I-01
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
1, 2
Q0, nQ0
Type
Description
Output
Differential output pair. LVPECL interface levels.
3, 4
Q1, nQ1
Output
Differential output pair. LVPECL interface levels.
5, 6
Q2, nQ2
Output
Differential output pair. LVPECL interface levels.
7, 8
Q3, nQ3
Output
Differential output pair. LVPECL interface levels.
9, 10
Q4, nQ4
Output
Differential output pair. LVPECL interface levels.
11
VEE
Power
12
CLK_SEL
Input
13, 17
nc
Unused
14
nCLK0
Input
15
CLK0
Input
Pulldown Non-inver ting differential clock input.
16
CLK1
Input
Pulldown Clock input. LVTTL / LVCMOS interface levels.
18, 20
VCC
Power
Negative supply pin.
Clock select input. When HIGH, selects CLK1 input.
Pulldown When LOW, selects CLK0, nCLK0 inputs.
LVTTL / LVCMOS interface levels.
No connect.
Pullup
Inver ting differential clock input.
Positive supply pins.
Synchronizing clock enable. When LOW, clock outputs follow clock
19
nCLK_EN
Input
Pulldown input. When HIGH, Q outputs are forced low, nQ outputs are forced
high. LVTTL / LVCMOS interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
CIN
Input Capacitance
4
pF
RPULLUP
Input Pullup Resistor
51
kΩ
RPULLDOWN
Input Pulldown Resistor
51
kΩ
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REV. E SEPTEMBER 23, 2005
ICS85314I-01
Integrated
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LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs
Outputs
nCLK_EN
CLK_SEL
Selected Source
Q0:Q4
nQ0:nQ4
0
0
CLK0, nCLK0
Enabled
Enabled
0
1
CLK1
Enabled
Enabled
1
0
CLK0, nCLK0
Disabled; LOW
Disabled; HIGH
1
1
CLK1
Disabled; LOW
After nCLK_EN switches, the clock outputs are disabled or enabled following a falling input clock edge
as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLK0, nCLK0 and CLK1 inputs
as described in Table 3B.
Disabled; HIGH
Enabled
Disabled
nCLK0
CLK0, CLK1
nCLK_EN
nQ0:nQ4
Q0:Q4
FIGURE 1. nCLK_EN TIMING DIAGRAM
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
Input to Output Mode
Polarity
HIGH
Differential to Differential
Non Inver ting
LOW
Differential to Differential
Non Inver ting
CLK0 or CLK1
nCLK0
Q0:Q4
nQ0:nQ4
0
1
LOW
1
0
HIGH
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REV. E SEPTEMBER 23, 2005
ICS85314I-01
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LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
4.6V
Inputs, VI
-0.5V to VCC + 0.5V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θJA
20 Lead TSSOP
20 Lead SOIC
73.2°C/W (0 lfpm)
46.2°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0V, TA = -40°C TO 85°C
Symbol
Parameter
Test Conditions
VCC
Power Supply Voltage
IEE
Power Supply Current
Minimum
Typical
Maximum
Units
2.375
3.3
3.8
V
80
mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0V, TA = -40°C TO 85°C
Symbol
Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
Input High Current
IIL
Input Low Current
Test Conditions
Minimum
Typical
Maximum
Units
nCLK_EN, CLK_SEL
2
VCC + 0.3
V
CLK1
2
VCC + 0.3
V
nCLK_EN, CLK_SEL
-0.3
0.8
V
CLK1
CLK1,
CLK_SEL, nCLK_EN
CLK1,
CLK_SEL, nCLK_EN
-0.3
1.3
V
150
µA
VIN = VCC = 3.8V
VCC = 3.8V, VIN = 0V
-5
µA
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0V, TA = -40°C TO 85°C
Symbol
Parameter
IIH
Input High Current
IIL
Input Low Current
Test Conditions
nCLK0
Minimum
Typical
VCC = VIN = 3.8V
CLK0
VCC = VIN = 3.8V
nCLK0
VCC = 3.8V, VIN = 0V
-150
CLK0
VCC = 3.8V, VIN = 0V
-5
VPP
Peak-to-Peak Input Voltage
0.15
Common Mode Input Voltage;
0.5
VCMR
NOTE 1, 2
NOTE 1: For single ended applications the maximum input voltage for CLK0, nCLK0 is VCC + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
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Maximum
Units
5
µA
150
µA
µA
µA
1.3
V
VCC - 0.85
V
REV. E SEPTEMBER 23, 2005
ICS85314I-01
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0V, TA = -40°C TO 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VOH
Output High Voltage; NOTE 1
VCC - 1.4
VCC - 0.9
V
VOL
Output Low Voltage; NOTE 1
VCC - 2.0
VCC - 1.7
V
VSWING
Peak-to-Peak Output Voltage Swing
0.6
1.0
V
Maximum
Units
700
MHz
300
MHz
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
TABLE 5. AC CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0V, TA = -40°C TO 85°C
Symbol Parameter
fMAX
Output Frequency
Test Conditions
CLK1
RMS Phase Jitter (Random); NOTE 5
tpLH
Propagation Delay, Low to High; NOTE 1
t sk(o)
Output Skew;
NOTE 3, 6
t sk(pp)
Par t-to-Par t Skew; NOTE 4, 6
t R / tF
Output Rise/Fall Time
Output Duty Cycle
Typical
CLK0, nCLK0
tjit (Ø)
odc
Minimum
Integration Range:
(12kHz - 20MHz)
0.05
1.8
ns
TSSOP Package
30
ps
SOIC Package
50
ps
350
ps
CLK0, nCLK0
1.0
1. 4
20% to 80%
200
700
ps
IJ 700MHz
45
55
%
55
%
CLK1
IJ 250MHz
45
All parameters measured at fMAX unless noted otherwise.
The cycle-to-cycle jitter on the input will equal the jitter on the output. The par t does not add jitter
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Measured from VCC/2 input crossing point to the differential output crossing point.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 5: Please refer to the Phase Noise Plot.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
85314BGI-01
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REV. E SEPTEMBER 23, 2005
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LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
TYPICAL PHASE NOISE AT 155.52MHZ
0
-10
155.52MHz
-20
RMS Phase Jitter (Random)
12kHz to 20MHz = 0.05ps (typical)
NOISE POWER dBc
Hz
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
Raw Phase Noise Data
➤
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
85314BGI-01
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REV. E SEPTEMBER 23, 2005
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Integrated
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LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
2V
VCC
Qx
VCC
SCOPE
nCLK0
LVPECL
V
V
Cross Points
PP
nQx
CMR
CLK0
VEE
-1.8V ± -0.375V
VEE
DIFFERENTIAL INPUT LEVEL
3.3V OUTPUT LOAD AC TEST CIRCUIT
PART 1
nQx
nQx
Qx
Qx
PART 2
nQy
nQy
Qy
Qy
tsk(o)
tsk(o)
OUTPUT SKEW
PART-TO-PART SKEW
Noise Power
Phase Noise Plot
nQ0:nQ4
Q0:Q4
Phase Noise Mask
t PW
t
f1
Offset Frequency
odc =
f2
t PW
x 100%
t PERIOD
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
85314BGI-01
PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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REV. E SEPTEMBER 23, 2005
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LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
nCLK0
CLK1
CLK0
nQ0:nQ4
nQ0:nQ4
Q0:Q4
Q0:Q4
tPD
tPD
PROPAGATION DELAY (DIFFERENTIAL INPUT)
80%
PROPAGATION DELAY (LVCMOS INPUT)
80%
VSW I N G
Clock
Outputs
20%
20%
tR
tF
OUTPUT RISE/FALL TIME
85314BGI-01
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ICS85314I-01
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VCC/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VCC
R1
1K
Single Ended Clock Input
CLK
V_REF
nCLK
C1
0.1u
R2
1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
CLK INPUT:
For applications not requiring the use of a clock input, it can
be left floating. Though not required, but for additional
protection, a 1kΩ resistor can be tied from the CLK input to
ground.
LVPECL OUTPUT
All unused LVPECL outputs can be left floating. We
recommend that there is no trace attached. Both sides of the
differential output pair should either be left floating or
terminated.
CLK/nCLK INPUT:
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required,
but for additional protection, a 1kΩ resistor can be tied from
CLK to ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
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LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both VSWING and VOH must meet the
VPP and VCMR input requirements. Figures 3A to 3E show interface examples for the HiPerClockS CLK/nCLK input driven by
the most common driver types. The input interfaces suggested
here are examples only. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
For example in Figure 3A, the input termination applies for ICS
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
ICS
HiPerClockS
LVHSTL Driver
R1
50
R1
50
HiPerClockS
Input
R2
50
R2
50
R3
50
FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
3.3V
R3
125
R4
125
Zo = 50 Ohm
LVDS_Driv er
Zo = 50 Ohm
CLK
CLK
R1
100
Zo = 50 Ohm
nCLK
LVPECL
R1
84
HiPerClockS
Input
nCLK
Receiv er
Zo = 50 Ohm
R2
84
FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
3.3V
3.3V
LVPECL
Zo = 50 Ohm
C1
Zo = 50 Ohm
C2
R3
125
R4
125
CLK
nCLK
R5
100 - 200
R6
100 - 200
R1
84
HiPerClockS
Input
R2
84
R5,R6 locate near the driver pin.
FIGURE 3E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
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LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
TERMINATION FOR 3.3V LVPECL OUTPUTS
50Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. Figures 4A and 4B show two different layouts which
are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
3.3V
Zo = 50Ω
125Ω
FOUT
125Ω
FIN
Zo = 50Ω
Zo = 50Ω
FOUT
50Ω
RTT =
1
Z
((VOH + VOL) / (VCC – 2)) – 2 o
Zo = 50Ω
VCC - 2V
RTT
84Ω
FIGURE 4A. LVPECL OUTPUT TERMINATION
85314BGI-01
FIN
50Ω
84Ω
FIGURE 4B. LVPECL OUTPUT TERMINATION
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TERMINATION
FOR
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
2.5V LVPECL OUTPUT
Figure 5A and Figure 5B show examples of termination for
2.5V LVPECL driver. These terminations are equivalent to terminating 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very
close to ground level. The R3 in Figure 5B can be eliminated
and the termination is shown in Figure 5C.
2.5V
VCC=2.5V
2.5V
2.5V
VCC=2.5V
R1
250
Zo = 50 Ohm
R3
250
+
Zo = 50 Ohm
+
Zo = 50 Ohm
-
Zo = 50 Ohm
2,5V LVPECL
Driv er
-
R1
50
2,5V LVPECL
Driv er
R2
62.5
R2
50
R4
62.5
R3
18
FIGURE 5B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 5A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCC=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
2,5V LVPECL
Driv er
R1
50
R2
50
FIGURE 5C. 2.5V LVPECL TERMINATION EXAMPLE
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POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85314I-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS85314I-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.8V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.8V * 80mA = 304mW
Power (outputs)MAX = 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 5 * 30.2mW = 151mW
Total Power_MAX (3.465V, with all outputs switching) = 304mW + 151mW = 455mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6A below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.455W * 66.6°C/W = 115°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6A. THERMAL RESISTANCE θJA
20-PIN TSSOP, FORCED CONVECTION
FOR
θJA by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
98.0°C/W
88.0°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
73.2°C/W
66.6°C/W
63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 6B. THERMAL RESISTANCE θJA
FOR
20-PIN SOIC, FORCED CONVECTION
θJA by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
83.2°C/W
65.7°C/W
57.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
46.2°C/W
39.7°C/W
36.8°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
85314BGI-01
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ICS85314I-01
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
3. Calculations and Equations.
LVPECL output driver circuit and termination are shown in Figure 6.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CC
•
For logic high, VOUT = V
OH_MAX
(V
CC_MAX
•
-V
OH_MAX
OL_MAX
CC_MAX
CC_MAX
– 1.0V
) = 1.0V
For logic low, VOUT = V
(V
=V
=V
CC_MAX
– 1.7V
) = 1.7V
-V
OL_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
– (V
CC_MAX
- 2V))/R ] * (V
CC_MAX
L
-V
OH_MAX
) = [(2V - (V
CC_MAX
-V
OH_MAX
))/R ] * (V
CC_MAX
L
-V
OH_MAX
)=
[(2V - 1V)/50Ω] * 1V = 20.0mW
Pd_L = [(V
OL_MAX
– (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OL_MAX
) = [(2V - (V
CC_MAX
-V
OL_MAX
))/R ] * (V
L
CC_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
85314BGI-01
www.icst.com/products/hiperclocks.html
14
REV. E SEPTEMBER 23, 2005
ICS85314I-01
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
RELIABILITY INFORMATION
TABLE 7A. θJAVS. AIR FLOW TABLE
FOR
20 LEAD TSSOP
θ by Velocity (Linear Feet per Minute)
JA
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
114.5°C/W
73.2°C/W
98.0°C/W
66.6°C/W
88.0°C/W
63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 7B.
θJAVS. AIR FLOW TABLE FOR 20 LEAD SOIC
θ by Velocity (Linear Feet per Minute)
JA
0
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
83.2°C/W
46.2°C/W
200
500
65.7°C/W
39.7°C/W
57.5°C/W
36.8°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS85314I-01 is: 674
Compatible to part number MC100LVEL14
85314BGI-01
www.icst.com/products/hiperclocks.html
15
REV. E SEPTEMBER 23, 2005
ICS85314I-01
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - G SUFFIX
FOR
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
20 LEAD TSSOP
TABLE 8A. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
N
Maximum
20
A
--
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
6.40
E
E1
6.60
6.40 BASIC
4.30
e
4.50
0.65 BASIC
L
0.45
α
0°
8°
aaa
--
0.10
0.75
Reference Document: JEDEC Publication 95, MO-153
85314BGI-01
www.icst.com/products/hiperclocks.html
16
REV. E SEPTEMBER 23, 2005
ICS85314I-01
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - M SUFFIX
FOR
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
20 LEAD SOIC
TABLE 8B. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
N
A
Maximum
20
--
2.65
A1
0.10
--
A2
2.05
2.55
B
0.33
0.51
C
0.18
0.32
D
12.60
13.00
E
7.40
e
H
7.60
1.27 BASIC
10.00
10.65
h
0.25
0.75
L
0.40
1.27
α
0°
8°
Reference Document: JEDEC Publication 95, MS-013, MO-119
85314BGI-01
www.icst.com/products/hiperclocks.html
17
REV. E SEPTEMBER 23, 2005
ICS85314I-01
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
TABLE 9. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
ICS85314BGI-01
ICS85314BI01
ICS85314BGI-01T
ICS85314BI01
20 lead TSSOP
tube
-40°C to 85°C
20 lead TSSOP
2500 tape & reel
-40°C to 85°C
ICS85314BGI-01LF
ICS5314BI01L
20 lead "Lead-Free" TSSOP
tube
-40°C to 85°C
ICS85314BGI-01LFT
ICS5314BI01L
20 lead "Lead-Free" TSSOP
2500 tape & reel
-40°C to 85°C
ICS85314BMI-01
ICS85314BI-01
20 lead SOIC
tube
-40°C to 85°C
ICS85314BMI-01T
ICS85314BI-01
20 lead SOIC
1000 tape & reel
-40°C to 85°C
ICS85314BMI-01LF
TBD
20 lead "Lead-Free" SOIC
tube
-40°C to 85°C
ICS85314BMI-01LFT
TB D
20 lead "Lead-Free" SOIC
1000 tape & reel
-40°C to 85°C
NOTE: Parts that are ordered with an “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
85314BGI-01
www.icst.com/products/hiperclocks.html
18
REV. E SEPTEMBER 23, 2005
Integrated
Circuit
Systems, Inc.
ICS85314I-01
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
REVISION HISTORY SHEET
Rev
Table
A
B
T2
T5
Page
7
8
9
15
1
2
5
6
8
9
1
4
5
7
C
T5
D
T5
1
5
T4D
5
E
9
T9
85314BGI-01
18
Description of Change
Updated Figure 2, Single Ended Signal Diagram.
Added "Termination for 2.5V LVPECL Outputs" section.
Added "Differential Input Interface" section.
Corrected Order Number and Marking from Rev. A to Rev. B.
Added Phase Noise Bullet to Features section.
Changed CIN from 4pF max. to 4pF typical.
AC Characteristics Table - added RMS Phase Jitter.
Added Phase Jitter Plot.
Updated Termination for 3.3V LVPECL Output diagrams.
Updated Termination for 2.5V LVPECL Output section.
Features section - added SOIC package output skew.
Absolute Maximum Ratings - added SOIC Package Thermal Impedance.
AC Characteristics table - added SOIC package for Output Skew.
Parameter Measurement Information - added Par t-to-Par t Skew and RMS
Phase Jitter Diagrams.
Features section - changed Par t-to-Par t Skew from 250ps max. to 350ps max.
AC Characteristics table - changed Par t-to-Par t Skew from 250ps max. to
350ps max.
LVPECL DC Characteristics Table - changed VOH max from VCC - 1.0V to
VCC - 0.9V.
Application Information Section - added Recommendations for Unused Input
and Output Pins.
Added TSSOP Lead-Free par t number.
www.icst.com/products/hiperclocks.html
19
Date
3/31/03
8/11/04
3/22/05
5/24/05
9/23/05
REV. E SEPTEMBER 23, 2005
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