ICST ICS83026AMIT Low skew, 1-to-2 differential-to-lvcmos/lvttl fanout buffer Datasheet

ICS83026I
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS83026I is a low skew, 1-to-2 Differential-to-LVCMOS/LVTTL Fanout Buffer and a
HiPerClockS™
member of the HiPerClockS™ family of High
Perfor mance Clock Solutions from ICS.The
differential input can accept most differential signal types (LVDS, LVHSTL, LVPECL, SSTL, and HCSL) and
translate to two single-ended LVCMOS/LVTTL outputs with a
maximum output skew of 20ps. The small 8-lead SOIC footprint makes this device ideal for use in applications with limited board space.
• 2 LVCMOS / LVTTL outputs
ICS
• Differential CLK, nCLK input pair
• CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• Output frequency: 350MHz (typical)
• Output skew: 20ps (maximum)
• Part-to-part skew: 600ps (maximum)
• Small 8 lead SOIC package saves board space
• 3.3V operating supply
• -40°C to 85°C ambient operating temperature
• Lead-Free package available
• Pin-to-pin compatible with MC100EPT26
BLOCK DIAGRAM
PIN ASSIGNMENT
Q0
nc
CLK
nCLK
nc
CLK
nCLK
Q1
1
2
3
4
8
7
6
5
VDD
Q0
Q1
GND
ICS83026I
8-Lead SOIC
3.8mm x 4.8mm, x 1.47mm package body
M Package
Top View
83026AMI
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1
REV. B NOVEMBER 9, 2004
ICS83026I
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
1, 4
nc
Unused
Type
Description
2
CLK
Input
3
nCLK
Input
5
GND
Power
Power supply ground.
No connect.
Pulldown Non-inver ting differential clock input.
Pullup
Inver ting differential clock input.
6
Q1
Output
Single clock output. LVCMOS / LVTTL interface levels.
7
Q0
Output
Single clock output. LVCMOS / LVTTL interface levels.
8
VDD
Power
Positive supply pin.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
RPULLUP
Input Capacitance
Power Dissipation Capacitance
(per output)
Input Pullup Resistor
RPULLDOWN
Input Pulldown Resistor
ROUT
Output Impedance
CPD
83026AMI
Test Conditions
Minimum
VDD = 3.6V
5
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2
Typical
Maximum
Units
4
pF
23
pF
51
KΩ
51
KΩ
7
12
Ω
REV. B NOVEMBER 9, 2004
ICS83026I
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5 V
Outputs, VO
-0.5V to VDD + 0.5V
Package Thermal Impedance, θJA
112.7°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±0.3V, TA = -40°C TO 85°C
Symbol
Parameter
Test Conditions
VDD
Power Supply Voltage
IDD
Power Supply Current
Minimum
Typical
Maximum
Units
3.0
3.3
3.6
V
35
mA
TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V±0.3V, TA = -40°C TO 85°C
Symbol
Parameter
Test Conditions
VOH
Output High Voltage; NOTE 1
VOL
Output Low Voltage; NOTE 1
Minimum
Typical
Maximum
2.6
Units
V
0.5
V
NOTE 1: Outputs terminated with 50Ω to VDD/2. See Parameter Measurement Information, 3.3V Output Load Test Circuit.
TABLE 3C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V±0.3V, TA = -40°C TO 85°C
Symbol
IIH
IIL
Parameter
Input High Current
Input Low Current
Test Conditions
nCLK
Minimum
Typical
VIN = VDD = 3.6V
Units
5
µA
150
µA
CLK
VIN = VDD = 3.6V
nCLK
VIN = 0V, VDD = 3.6V
-150
µA
CLK
VIN = 0V, VDD = 3.6V
-5
µA
Peak-to-Peak Input Voltage
0.15
Common Mode Input Voltage;
VCMR
GND + 0.5
NOTE 1, 2
NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
VPP
83026AMI
Maximum
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3
1.3
V
VDD - 0.85
V
REV. B NOVEMBER 9, 2004
Integrated
Circuit
Systems, Inc.
ICS83026I
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
TABLE 4. AC CHARACTERISTICS, VDD = 3.3V±0.3V, TA = -40°C TO 85°C
Symbol Parameter
fMAX
Output Frequency
tPD
Propagation Delay, NOTE 1
tsk(o)
Output Skew; NOTE 2, 4
tsk(pp)
Par t-to-Par t Skew; NOTE 3, 4
tR / tF
Output Rise/Fall Time
Test Conditions
Minimum
Typical
IJ 350MHz
1.7
2.1
5
0.8V to 2V
150
300
odc
Output Duty Cycle
40
50
All parameters measured at fMAX unless noted otherwise. See Parameter Measurement Information.
NOTE 1: Measured from the differential input crossing point to the output at VDD/2.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDD/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at VDD/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
83026AMI
Maximum
350
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4
Units
MHz
2.5
ns
20
ps
600
ps
450
ps
60
%
REV. B NOVEMBER 9, 2004
ICS83026I
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
1.65V±0.15V
VDD
SCOPE
V DD
nCLK
Qx
LVCMOS
V
GND
DIFFERENTIAL INPUT LEVEL
3.3VCORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
PART 1
V
DDO
Qx
2
V
DDO
2
PART 2
V
V
DDO
DDO
Qy
CMR
GND
-1.65V±0.15V
Qx
V
Cross Points
PP
CLK
Qy
2
t sk(o)
2
t sk(pp)
PART-TO-PART SKEW
OUTPUT SKEW
nCLK
80%
CLK
Q0, Q1
VDDO
2
t
Clock
Outputs
80%
20%
20%
tR
tF
PD
PROPAGATION DELAY
OUTPUT RISE/FALL TIME
V
DDO
2
Q0, Q1
Pulse Width
t
odc =
PERIOD
t PW
t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
83026AMI
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REV. B NOVEMBER 9, 2004
Integrated
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Systems, Inc.
ICS83026I
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VDD
R1
1K
Single Ended Clock Input
CLK
V_REF
nCLK
C1
0.1u
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
83026AMI
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REV. B NOVEMBER 9, 2004
ICS83026I
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both VSWING and VOH must meet the
VPP and VCMR input requirements. Figures 2A to 2E show interface examples for the HiPerClockS CLK/nCLK input driven by
the most common driver types. The input interfaces suggested
here are examples only. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
For example in Figure 2A, the input termination applies for ICS
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
ICS
HiPerClockS
LVHSTL Driver
R1
50
R1
50
HiPerClockS
Input
R2
50
R2
50
R3
50
FIGURE 2A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN
ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 2B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN
3.3V LVPECL DRIVER
BY
3.3V
3.3V
3.3V
3.3V
3.3V
R3
125
BY
R4
125
Zo = 50 Ohm
LVDS_Driv er
Zo = 50 Ohm
CLK
CLK
R1
100
Zo = 50 Ohm
nCLK
LVPECL
R1
84
HiPerClockS
Input
nCLK
Receiv er
Zo = 50 Ohm
R2
84
FIGURE 2C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN
3.3V LVPECL DRIVER
FIGURE 2D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN
3.3V LVDS DRIVER
BY
BY
3.3V
3.3V
3.3V
LVPECL
Zo = 50 Ohm
C1
Zo = 50 Ohm
C2
R3
125
R4
125
CLK
nCLK
R5
100 - 200
R6
100 - 200
R1
84
HiPerClockS
Input
R2
84
R5,R6 locate near the driver pin.
FIGURE 2E. HIPERCLOCKS CLK/nCLK INPUT DRIVEN
3.3V LVPECL DRIVER WITH AC COUPLE
83026AMI
BY
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7
REV. B NOVEMBER 9, 2004
ICS83026I
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
RELIABILITY INFORMATION
TABLE 5. θJAVS. AIR FLOW TABLE
FOR
8 LEAD SOIC
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
153.3°C/W
112.7°C/W
128.5°C/W
103.3°C/W
115.5°C/W
97.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS83026I is: 416
83026AMI
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8
REV. B NOVEMBER 9, 2004
ICS83026I
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - SUFFIX M
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
FOR
8 LEAD SOIC
TABLE 6. PACKAGE DIMENSIONS
SYMBOL
Millimeters
MINIMUM
N
MAXIMUM
8
A
1.35
1.75
A1
0.10
0.25
B
0.33
0.51
C
0.19
0.25
D
4.80
5.00
E
3.80
e
H
4.00
1.27 BASIC
5.80
6.20
h
0.25
0.50
L
0.40
1.27
α
0°
8°
Reference Document: JEDEC Publication 95, MS-012
83026AMI
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9
REV. B NOVEMBER 9, 2004
ICS83026I
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
TABLE 7. ORDERING INFORMATION
Part/Order Number
Marking
Package
ICS83026AMI
83026AMI
8 Lead SOIC
ICS83026AMIT
83026AMI
8 Lead SOIC on Tape and Reel
ICS83026AMILF
83026AIL
ICS83026AMILFT
83026AIL
8 Lead "Lead-Free" SOIC
8 Lead "Lead-Free" SOIC on
Tape and Reel
Count
Temperature
96 per tube
2500
-40°C to 85°C
96 per tube
2500
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
83026AMI
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10
REV. B NOVEMBER 9, 2004
Integrated
Circuit
Systems, Inc.
ICS83026I
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
REVISION HISTORY SHEET
Rev
Table
A
Page
1
1
T2
2
T7
6-7
11
B
83026AMI
Description of Change
Revised General Description.
Added Lead-Free bullet to Features section.
Pin Characteristics Table - changed CIN from 4pF max. to 4pF typical
and added 5Ω min. & 12Ω max. to ROUT row.
Added Application Information section.
Added Lead-Free P/N to Ordering Information table.
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11
Date
8/9/02
11/9/04
REV. B NOVEMBER 9, 2004
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