ICST ICS83054AGILF 4 : 1, single-ended multiplexer Datasheet

ICS83054I
Integrated
Circuit
Systems, Inc.
4:1, SINGLE-ENDED MULTIPLEXER
GENERAL DESCRIPTION
FEATURES
The ICS83054I is a low skew, 4:1, Singleended Multiplexer and a member of the
HiPerClockS™ HiPerClockS ™ family of High Performance
Clock Solutions from ICS. The ICS83054I
has four selectable single-ended clock inputs
and one single-ended clock output. The output has a
VDDO pin which may be set at 3.3V, 2.5V, or 1.8V, making
the device ideal for use in voltage translation applications.
An output enable pin places the output in a high
impedance state which may be useful for testing or
debug. The device operates up to 250MHz and is packaged in a 16 TSSOP.
• 4:1 single-ended multiplexer
ICS
• Q nominal output impedance: 7Ω (VDDO =3 .3V)
• Maximum output frequency: 250MHz
• Propagation delay: 3ns (maximum), VDD = VDDO = 3.3V
• Input skew: 225ps (maximum), VDD = VDDO = 3.3V
• Part-to-part skew: 475ps (maximum), VDD = VDDO = 3.3V
• Operating supply modes:
VDD/VDDO
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
2.5V/2.5V
2.5V/1.8V
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS-compliant
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
Q
nc
OE
CLK3
GND
nc
SEL1
CLK2
CLK0
CLK1
Q
CLK2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDDO
nc
CLK0
nc
VDD
nc
CLK1
SEL0
CLK3
ICS83054I
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm package body
G Package
Top View
SEL1
SEL0
OE
83054AGI
www.icst.com/products/hiperclocks.html
1
REV. A JANUARY 3, 2006
ICS83054I
Integrated
Circuit
Systems, Inc.
4:1, SINGLE-ENDED MULTIPLEXER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
1
Q
Output
3
OE
Input
4, 8,
10, 14
5
CLK3, CLK2,
CLK1, CLK0
GND
Input
Pulldown Single-ended clock inputs. LVCMOS/LVTTL interface levels.
Power
7, 9
SEL1, SEL0
Input
2, 6, 11, 13, 15
nc
Unused
Power supply ground.
Clock select input. See Control Input Function Table.
Pulldown
LVCMOS / LVTTL interface levels.
No connect.
12
VDD
Power
Core and input supply pin.
16
VDDO
Power
Output supply pin.
Pullup
Description
Single-ended clock output. LVCMOS/LVTTL interface levels.
Output enable. When LOW, outputs are in HIGH impedance state.
When HIGH, outputs are active. LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
CIN
Input Capacitance
4
pF
RPULLUP
Input Pullup Resistor
51
kΩ
RPULLDOWN
Input Pulldown Resistor
Power Dissipation Capacitance
(per output)
C PD
ROUT
Output Impedance
51
kΩ
VDDO = 3.465V
18
pF
VDDO = 2.625V
20
pF
VDDO = 1.89V
30
pF
VDDO = 3.465V
7
Ω
VDDO = 2.625V
7
Ω
VDDO = 1.89V
10
Ω
TABLE 3. CONTROL INPUT FUNCTION TABLE
Control Inputs
SEL1
SEL0
0
0
83054AGI
Input Selected to Q
CLK0
0
1
CLK1
1
0
CLK2
1
1
CLK3
www.icst.com/products/hiperclocks.html
2
REV. A JANUARY 3, 2006
ICS83054I
Integrated
Circuit
Systems, Inc.
4:1, SINGLE-ENDED MULTIPLEXER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5 V
Outputs, VO
-0.5V to VDDO + 0.5V
Package Thermal Impedance, θJA
89°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VDD
Core Supply Voltage
3.135
3.3
3.465
V
VDDO
Output Supply Voltage
3.135
3.3
3.465
V
IDD
Power Supply Current
40
mA
IDDO
Output Supply Current
5
mA
Maximum
Units
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = -40°C TO 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
VDD
Core Supply Voltage
3.135
3.3
3.465
V
VDDO
Output Supply Voltage
2.375
2. 5
2.625
V
IDD
Power Supply Current
40
mA
IDDO
Output Supply Current
5
mA
TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = -40°C TO 85°C
Symbol
Parameter
V DD
Core Supply Voltage
Test Conditions
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
1.71
1.8
VDDO
Output Supply Voltage
1.89
V
IDD
Power Supply Current
40
mA
IDDO
Output Supply Current
5
mA
TABLE 4D. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = -40°C TO 85°C
Symbol
Parameter
Minimum
Typical
Maximum
Units
VDD
Core Supply Voltage
Test Conditions
2.375
2.5
2.625
V
VDDO
Output Supply Voltage
2.375
2.5
2.625
V
IDD
Power Supply Current
35
mA
IDDO
Output Supply Current
5
mA
TABLE 4E. POWER SUPPLY DC CHARACTERISTICS, VDD = 2.5V±5%, VDDO = 1.8V±0.2V, TA = -40°C TO 85°C
Symbol
Parameter
VDD
Core Supply Voltage
Test Conditions
Minimum
Typical
Maximum
Units
2.375
2. 5
2.625
V
1.71
1. 8
VDDO
Output Supply Voltage
1.89
V
IDD
Power Supply Current
35
mA
IDDO
Output Supply Current
5
mA
83054AGI
www.icst.com/products/hiperclocks.html
3
REV. A JANUARY 3, 2006
ICS83054I
Integrated
Circuit
Systems, Inc.
4:1, SINGLE-ENDED MULTIPLEXER
TABLE 4F. LVCMOS/LVTTL DC CHARACTERISTICS, TA = -40°C TO 85°C
Symbol
VIH
VIL
IIH
IIL
VOH
VOL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
CLK0:CLK3,
SEL0, SEL1
OE
CLK0:CLK3,
SEL0, SEL1
OE
Output HighVoltage
Output Low Voltage
Test Conditions
Minimum
Maximum
Units
VDD = 3.3V ± 5%
2
Typical
VDD + 0.3
V
VDD = 2.5V ± 5%
1.7
VDD + 0.3
V
VDD = 3.3V ± 5%
-0.3
0.8
V
VDD = 2.5V ± 5%
-0.3
0.7
V
VDD = 3.3V or 2.5V ± 5%
150
µA
VDD = 3.3V or 2.5V ± 5%
5
µA
VDD = 3.3V or 2.5V ± 5%
-5
µA
VDD = 3.3V or 2.5V ± 5%
-150
µA
VDDO = 3.3V ± 5%; NOTE 1
2.6
V
VDDO = 2.5V ± 5%; NOTE 1
1.8
V
VDDO = 1.8V ± 5%; NOTE 1
VDD - 0.3
V
VDDO = 3.3V ± 5%; NOTE 1
0.5
V
VDDO = 2.5V ± 5%; NOTE 1
0.45
V
VDDO = 1.8V ± 5%; NOTE 1
0.35
V
NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement section, "Load Test Circuit" diagrams.
TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V ± 5%, TA = -40°C TO 85°C
Symbol Parameter
fMAX
Output Frequency
Test Conditions
Minimum
Typical
Maximum
Units
250
MHz
tpLH
Propagation Delay, Low to High; NOTE 1
2.4
2. 7
3.0
ns
tpHL
Propagation Delay, High to Low; NOTE 1
2.5
2.7
2.9
ns
t sk(i)
Input Skew; NOTE 2
t sk(pp)
Par t-to-Par t Skew; NOTE 2, 3
tR / tF
Output Rise/Fall Time
odc
Output Duty Cycle
55
20% to 80%
22 5
ps
475
ps
50
50 0
ps
45
55
@ 100MHz
45
MUXISOL MUX Isolation
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2.
83054AGI
www.icst.com/products/hiperclocks.html
4
%
dB
REV. A JANUARY 3, 2006
ICS83054I
Integrated
Circuit
Systems, Inc.
4:1, SINGLE-ENDED MULTIPLEXER
TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = -40°C TO 85°C
Symbol Parameter
fMAX
Output Frequency
Test Conditions
Minimum
Typical
Maximum
Units
250
MHz
tpLH
Propagation Delay, Low to High; NOTE 1
2.5
2.8
3.1
ns
tpHL
Propagation Delay, High to Low; NOTE 1
2.6
2.8
3.0
ns
t sk(i)
Input Skew; NOTE 2
45
150
ps
t sk(pp)
Par t-to-Par t Skew; NOTE 2, 3
tR / tF
Output Rise/Fall Time
odc
Output Duty Cycle
20% to 80%
400
ps
50
50 0
ps
45
55
@ 100MHz
45
MUXISOL MUX Isolation
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2.
%
dB
TABLE 5C. AC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 1.8V ± 5%, TA = -40°C TO 85°C
Symbol Parameter
fMAX
Output Frequency
Test Conditions
Minimum
Typical
Maximum
Units
250
MHz
tpLH
Propagation Delay, Low to High; NOTE 1
2.7
3.2
3.8
ns
tpHL
Propagation Delay, High to Low; NOTE 1
2.8
3.3
3.8
ns
t sk(i)
Input Skew; NOTE 2
t sk(pp)
Par t-to-Par t Skew; NOTE 2, 3
tR / tF
Output Rise/Fall Time
odc
Output Duty Cycle
50
20% to 80%
150
ps
475
ps
100
700
ps
45
55
@ 100MHz
45
MUXISOL MUX Isolation
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2.
83054AGI
www.icst.com/products/hiperclocks.html
5
%
dB
REV. A JANUARY 3, 2006
ICS83054I
Integrated
Circuit
Systems, Inc.
4:1, SINGLE-ENDED MULTIPLEXER
TABLE 5D. AC CHARACTERISTICS, VDD = VDDO = 2.5V ± 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
250
MHz
3.5
ns
fMAX
Output Frequency
tpLH
Propagation Delay, Low to High; NOTE 1
2.5
3.0
2.5
2.9
3.4
ns
60
17 5
ps
tpHL
Propagation Delay, High to Low; NOTE 1
t sk(i)
Input Skew; NOTE 2
t sk(pp)
Par t-to-Par t Skew; NOTE 2, 3
tR / tF
Output Rise/Fall Time
odc
Output Duty Cycle
20% to 80%
300
ps
100
500
ps
40
60
%
@ 100MHz
45
MUXISOL MUX Isolation
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2.
dB
TABLE 5E. AC CHARACTERISTICS, VDD = 2.5V ± 5%, VDDO = 1.8V ± -5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
250
MHz
4.0
ns
fMAX
Output Frequency
tpLH
Propagation Delay, Low to High; NOTE 1
2.6
3.3
2.7
3.3
4.0
ns
50
150
ps
325
ps
10 0
70 0
ps
40
60
%
tpHL
Propagation Delay, High to Low; NOTE 1
t sk(i)
Input Skew; NOTE 2
t sk(pp)
Par t-to-Par t Skew; NOTE 2, 3
tR / tF
Output Rise/Fall Time
odc
Output Duty Cycle
20% to 80%
@ 100MHz
45
MUXISOL MUX Isolation
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2.
83054AGI
www.icst.com/products/hiperclocks.html
6
dB
REV. A JANUARY 3, 2006
ICS83054I
Integrated
Circuit
Systems, Inc.
4:1, SINGLE-ENDED MULTIPLEXER
PARAMETER MEASUREMENT INFORMATION
1.65V±5%
1.25V±5%
SCOPE
VDD,
VDDO
LVCMOS
SCOPE
VDD,
VDDO
Qx
Qx
LVCMOS
GND
GND
-1.65V±5%
-1.25V±5%
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
2.05V±5%
2.4±5%
1.25V±5%
SCOPE
V DD
VDDO
LVCMOS
0.9V±5%
SCOPE
V DD
VDDO
Qx
Qx
LVCMOS
GND
GND
-0.9V±5%
-1.25V±5%
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
1.6V±5% 0.9V±5%
Part 1
SCOPE
VDD
VDDO
LVCMOS
Qx
V
DDO
2
Qx
Part 2
GND
Qy
V
DDO
2
tsk(pp)
-0.9V±5%
2.5 CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
83054AGI
PART-TO-PART SKEW
www.icst.com/products/hiperclocks.html
7
REV. A JANUARY 3, 2006
ICS83054I
Integrated
Circuit
Systems, Inc.
VDD
VDD
CLK0:CLK7
2
2
VDDO
Q
4:1, SINGLE-ENDED MULTIPLEXER
2
tpLH
VDDO
Clock
Outputs
2
tpHL
PROPAGATION DELAY
80%
80%
tR
tF
20%
20%
OUTPUT RISE/FALL TIME
CLKx
V
DDO
2
Q
Q
t PW
t
tPD1
odc =
PERIOD
t PW
x 100%
t PERIOD
CLKy
Q
tPD2
tsk(i) = ⏐tPD2 – tPD1⏐
INPUT SKEW
83054AGI
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
www.icst.com/products/hiperclocks.html
8
REV. A JANUARY 3, 2006
ICS83054I
Integrated
Circuit
Systems, Inc.
4:1, SINGLE-ENDED MULTIPLEXER
APPLICATION INFORMATION
RECOMMENDATIONS FOR UNUSED INPUT PINS
INPUTS:
CLK INPUT:
For applications not requiring the use of a clock input, it can
be left floating. Though not required, but for additional
protection, a 1kΩ resistor can be tied from the CLK input to
ground.
83054AGI
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs;
additional resistance is not required but can be added for
additional protection. A 1kΩ resistor can be used.
www.icst.com/products/hiperclocks.html
9
REV. A JANUARY 3, 2006
ICS83054I
Integrated
Circuit
Systems, Inc.
4:1, SINGLE-ENDED MULTIPLEXER
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE FOR 16 LEAD TSSOP
θJA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
137.1°C/W
89.0°C/W
200
118.2°C/W
81.8°C/W
500
106.8°C/W
78.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS83054I is: 874
83054AGI
www.icst.com/products/hiperclocks.html
10
REV. A JANUARY 3, 2006
ICS83054I
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - G SUFFIX
4:1, SINGLE-ENDED MULTIPLEXER
FOR
16 LEAD TSSOP
TABLE 7. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
N
Maximum
16
A
--
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
4.90
5.10
E
E1
6.40 BASIC
4.30
e
4.50
0.65 BASIC
L
0.45
0.75
α
0°
8°
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
83054AGI
www.icst.com/products/hiperclocks.html
11
REV. A JANUARY 3, 2006
ICS83054I
Integrated
Circuit
Systems, Inc.
4:1, SINGLE-ENDED MULTIPLEXER
TABLE 8. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
ICS83054AGI
83054AGI
16 Lead TSSOP
tube
-40°C to 85°C
ICS83054AGIT
83054AGI
16 Lead TSSOP
2500 tape & reel
-40°C to 85°C
ICS83054AGILF
83054AIL
16 Lead "Lead-Free" TSSOP
tube
-40°C to 85°C
ICS83054AGILFT
83054AIL
16 Lead "Lead-Free" TSSOP
2500 tape & reel
-40°C to 85°C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
83054AGI
www.icst.com/products/hiperclocks.html
12
REV. A JANUARY 3, 2006
ICS83054I
Integrated
Circuit
Systems, Inc.
4:1, SINGLE-ENDED MULTIPLEXER
REVISION HISTORY SHEET
Rev
Table
Page
A
T8
12
83054AGI
Description of Change
Ordering Information Table - corrected Par t/Order Numbers.
www.icst.com/products/hiperclocks.html
13
Date
1/3/06
REV. A JANUARY 3, 2006
Similar pages