ICST ICS8421002AI Femtoclocksâ ¢ crystal-to-hstl frequency synthesizer Datasheet

ICS8421002I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TOHSTL FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
FEATURES
The ICS8421002I is a 2 output HSTL Synthesizer
optimized to generate Fibre Channel reference
HiPerClockS™ clock frequencies and is a member of the
HiPerClocksTM family of high performance clock
solutions from ICS. Using a 26.5625MHz 18pF
parallel resonant crystal, the following frequencies can be
generated based on the 2 frequency select pins (F_SEL[1:0]):
212.5MHz, 187.5MHz, 159.375MHz, 106.25MHz and
53.125MHz. The ICS8421002I uses ICS’ 3rd generation low
phase noise VCO technology and can achieve 1ps or lower
typical rms phase jitter, easily meeting Fibre Channel jitter
requirements. The ICS8421002I is packaged in a small 20-pin
TSSOP package.
• Two HSTL outputs (VOHmax = 1.5V)
ICS
• Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
• Supports the following output frequencies: 212.5MHz,
187.5MHz, 159.375MHz, 106.25MHz, 53.125MHz
• VCO range: 560MHz - 680MHz
• RMS phase jitter @ 212.5MHz, using a 26.5625MHz crystal
(637kHz - 10MHz): 0.59ps (typical)
• Power supply modes:
Core/Output
3.3V/1.8V
2.5V/1.8V
• -40°C to 85°C ambient operating temperature
• Available in both standard an lead-free RoHS compliant
packages
PIN ASSIGNMENT
FREQUENCY SELECT FUNCTION TABLE
Input
Frequency
(MHz)
Inputs
M Divider N Divider
Value
Value
24
3
F_SEL1 F_SEL0
26.5625
0
0
26.5625
0
1
24
26.5625
1
0
26.5625
1
1
23.4375
0
0
M/N
Divider Value
8
Output
Frequency
(MHz)
212.5
4
6
159.375
24
6
4
106.25
24
12
2
53.125
24
3
8
187.5
nPLL_SEL
nQ0
MR
nPLL_SEL
nc
VDDA
F_SEL0
VDD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VDDO
Q1
nQ1
GND
VDD
nXTAL_SEL
REF_CLK
XTAL_IN
XTAL_OUT
F_SEL1
ICS8421002I
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm
package body
G Package
Top View
BLOCK DIAGRAM
2
F_SEL[1:0] Pulldown
nc
VDDO
Q0
Pulldown
Q0
REF_CLK Pulldown
F_SEL[1:0]
0 0 ÷3 (default)
1
1
26.5625MHz
XTAL_IN
OSC
0
Phase
Detector
VCO
0
01
÷4
10
11
÷6
÷12
nQ0
Q1
nQ1
XTAL_OUT
nXTAL_SEL
Pulldown
M = 24 (fixed)
MR
Pulldown
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
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1
ICS8421002I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TOHSTL FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
Name
1, 7
nc
Unused
2, 20
VDDO
Power
3, 4
Q0, nQ0
Ouput
5
MR
Input
6
nPLL_SEL
Input
8
Power
Input
Pulldown Frequency select pins. LVCMOS/LVTTL interface levels.
Power
14
VDDA
F_SEL0,
F_SEL1
VDD
XTAL_OUT,
XTAL_IN
REF_CLK
Differential output pair. HSTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs Qx to go low and the inver ted outputs nQx
Pulldown
to go high. When logic LOW, the internal dividers and the outputs are
enabled. LVCMOS/LVTTL interface levels.
Selects between the PLL and REF_CLK as input to the dividers. When
Pulldown LOW, selects PLL (PLL Enable). When HIGH, deselects the reference clock
(PLL Bypass). LVCMOS/LVTTL interface levels.
Analog supply pin.
15
nXTAL_SEL
Input
Core supply pin.
Parallel resonant cr ystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
Pulldown LVCMOS/LVTTL reference clock input.
Selects between cr ystal or REF_CLK inputs as the the PLL Reference
Pulldown source. Selects XTAL inputs when LOW. Selects REF_CLK when HIGH.
LVCMOS/LVTTL interface levels.
Power supply ground.
9, 11
10, 16
12, 13
Type
Input
Input
17
GND
Power
18, 19
nQ1, Q1
Output
Description
No connect.
Output supply pins.
Differential output pair. HSTL interface levels.
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
Input Capacitance
4
pF
RPULLDOWN
Input Pulldown Resistor
51
kΩ
8421002AGI
Test Conditions
Minimum
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2
Typical
Maximum
Units
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FEMTOCLOCKS™ CRYSTAL-TOHSTL FREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θJA
73.2°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 1.8V±0.2V, TA = -40°C TO 85°C
Symbol
Parameter
Minimum
Typical
Maximum
Units
VDD
Core Supply Voltage
Test Conditions
3.135
3.3
3.465
V
VDDA
Analog Supply Voltage
3.135
3.3
3.465
V
3.135
3.3
VDDO
Output Supply Voltage
3.465
V
IDD
Power Supply Current
110
mA
IDDA
Analog Supply Current
12
mA
IDDO
Output Supply Current
No Load
0
mA
TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 2.5V±5%, VDDO = 1.8V±0.2V, TA = -40°C TO 85°C
Symbol
Parameter
Minimum
Typical
Maximum
Units
VDD
Core Supply Voltage
Test Conditions
2.375
2.5
2.625
V
VDDA
Analog Supply Voltage
2.375
2.5
2.625
V
VDDO
Output Supply Voltage
2.375
2.5
2.625
V
IDD
Power Supply Current
96
mA
12
mA
IDDA
Analog Supply Current
IDDO
Output Supply Current
No Load
0
mA
TABLE 3C. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V±5% OR 2.5V±5%, VDDO = 1.8V±0.2V,
TA = -40°C TO 85°C
Symbol
Parameter
VIH
Input High Voltage
VIL
Input
Low Voltage
IIH
Input
High Current
IIL
Input
Low Current
8421002AGI
Test Conditions
VDD = 3.3V
REF_CLK, MR,
F_SEL0, F_SEL1,
nPLL_SEL, nXTAL_SEL
REF_CLK, MR,
F_SEL0, F_SEL1,
nPLL_SEL, nXTAL_SEL
Minimum Typical
2
Maximum
VDD + 0.3
Units
V
VDD = 2.5V
1.7
VDD + 0.3
V
VDD = 3.3V
-0.3
0.8
V
VDD = 2.5V
-0.3
0.7
V
150
µA
VDD = VIN = 3.465V
or 2.5V
VDD = 3.465V or 2.5V,
VIN = 0V
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3
-150
µA
REV. A FEBRUARY 7, 2006
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FEMTOCLOCKS™ CRYSTAL-TOHSTL FREQUENCY SYNTHESIZER
TABLE 3D. HSTL DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 1.8V±0.2V, TA = -40°C TO 85°C
Symbol Parameter
Maximum
Units
VOH
Output High Voltage; NOTE 1
Test Conditions
Minimum
1.0
1.5
V
VOL
Output Low Voltage; NOTE 1
0
0.5
V
VOX
Output Crossover Voltage; NOTE 2
40
60
%
0.6
1.3
V
Peak-to-Peak Output Voltage Swing
VSWING
NOTE 1: Outputs terminated with 50Ω to ground.
NOTE 2: Defined with respect to output voltage swing at a given condition.
Typical
TABLE 3E. HSTL DC CHARACTERISTICS, VDD = VDDA = 2.5V±5%, VDDO = 1.8V±0.2V, TA = -40°C TO 85°C
Symbol Parameter
Maximum
Units
VOH
Output High Voltage; NOTE 1
Test Conditions
Minimum
0.8
1.5
V
VOL
Output Low Voltage; NOTE 1
0
0.6
V
VOX
Output Crossover Voltage; NOTE 2
40
60
%
0.5
1.5
V
Maximum
Units
Peak-to-Peak Output Voltage Swing
VSWING
NOTE 1: Outputs terminated with 50Ω to ground.
NOTE 2: Defined with respect to output voltage swing at a given condition.
Typical
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Mode of Oscillation
Typical
Fundamental
28.33
MHz
Equivalent Series Resistance (ESR)
Frequency
23.33
26.5625
50
Ω
Shunt Capacitance
7
pF
Drive Level
1
mW
NOTE: Characterized using an 18pF parallel resonant crystal.
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FEMTOCLOCKS™ CRYSTAL-TOHSTL FREQUENCY SYNTHESIZER
TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 1.8V±0.2V, TA = -40°C TO 85°C
Symbol
Parameter
fOUT
Output Frequency
tsk(o)
Output Skew; NOTE 1, 3
tjit(Ø)
t R / tF
RMS Phase Jitter (Random);
NOTE 2
Output Rise/Fall Time
Test Conditions
Minimum
F_SEL[1:0] = 00
186.67
Typical
Maximum
Units
226.66
MHz
F_SEL[1:0] = 01
140
170
MHz
F_SEL[1:0] = 10
93.33
113.33
MH z
F_SEL[1:0] = 11
46.67
56.66
MHz
20
ps
212.5MHz, (637kHz - 10MHz)
0.59
ps
187.5MHz, (1.875MHz - 20MHz)
0.51
ps
159.375MHz, (637kHz - 10MHz)
0.56
ps
106.25MHz, (637kHz - 10MHz)
0.69
ps
53.125MHz, (637kHz - 10MHz)
0.66
ps
20% to 80%
175
N Divider = 4, 6, 12
48
odc
Output Duty Cycle
N Divider = 3
44
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
875
ps
52
56
%
%
Maximum
Units
226.66
MHz
TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = 2.5V±5%, VDDO = 1.8V±0.2V, TA = -40°C TO 85°C
Symbol
Parameter
fOUT
Output Frequency
t sk(o)
Output Skew; NOTE 1, 3
t jit(Ø)
tR / tF
RMS Phase Jitter (Random);
NOTE 2
Output Rise/Fall Time
Test Conditions
Minimum
F_SEL[1:0] = 00
186.67
Typical
F_SEL[1:0] = 01
140
170
MHz
F_SEL[1:0] = 10
93.33
113.33
MHz
F_SEL[1:0] = 11
46.67
56.66
MHz
20
ps
212.5MHz, (637kHz - 10MHz)
0.60
ps
187.5MHz, (1.875MHz - 20MHz)
0.70
ps
159.375MHz, (637kHz - 10MHz)
0.64
ps
106.25MHz, (637kHz - 10MHz)
0.70
ps
53.125MHz, (637kHz - 10MHz)
0.68
ps
20% to 80%
200
N Divider = 4, 6, 12
48
odc
Output Duty Cycle
N Divider = 3
44
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
8421002AGI
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5
700
ps
52
56
%
%
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FEMTOCLOCKS™ CRYSTAL-TOHSTL FREQUENCY SYNTHESIZER
TYPICAL PHASE NOISE
0
AT
212.5MHZ @ 3.3V
➤
-10
-20
Fibre Channel Jitter Filter
-30
-40
-50
212.5MHz
RMS Phase Jitter (Random)
637kHz to 10MHz = 0.59ps (typical)
-70
-80
-90
Raw Phase Noise Data
-100
-110
➤
NOISE POWER dBc
Hz
-60
-120
-130
-140
➤
-150
-160
-170
-180
Phase Noise Result by adding
Fibre Channel Filter to raw data
-190
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE
0
AT
53.125MHZ @ 3.3V
➤
-10
-20
Fibre Channel Jitter Filter
-30
-50
53.125MHz
-60
RMS Phase Jitter (Random)
637kHz to 10MHz = 0.66ps (typical)
-70
-80
-90
-100
Raw Phase Noise Data
-110
-120
➤
NOISE POWER dBc
Hz
-40
-130
-140
-150
➤
-160
-170
-180
Phase Noise Result by adding
Fibre Channel Filter to raw data
-190
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
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FEMTOCLOCKS™ CRYSTAL-TOHSTL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
VDD
VDD
VDDA
VDDA
VDDO
VDDO
Qx
SCOPE
Qx
SCOPE
HSTL
HSTL
GND
GND
nQx
nQx
0V
0V
HSTL 3.3V/1.8V OUTPUT LOAD AC TEST CIRCUIT
HSTL 2.5V/1.8V OUTPUT LOAD AC TEST CIRCUIT
nQx
80%
80%
Qx
VSW I N G
Clock
Outputs
nQy
20%
20%
Qy
tF
tR
tsk(o)
OUTPUT SKEW
OUTPUT RISE/FALL TIME
Phase Noise Plot
nQ0, nQ1
Noise Power
Q0, Q1
Pulse Width
t
Phase Noise Mask
odc =
f1
Offset Frequency
PERIOD
t PW
t PERIOD
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
8421002AGI
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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FEMTOCLOCKS™ CRYSTAL-TOHSTL FREQUENCY SYNTHESIZER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS8421002I provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VDD, VDDA, and VDDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10µF and a .01μF bypass
capacitor should be connected to each VDDA.
3.3V or 2.5V
VDD
.01μF
10Ω
VDDA
.01μF
10μF
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
below were determined using a 26.5625MHz 18pF parallel
resonant crystal and were chosen to minimize the ppm error.
The ICS8421002I has been characterized with 18pF parallel
resonant crystals. The capacitor values shown in Figure 2
XTAL_OUT
C1
22p
X1
18pF Parallel Crystal
XTAL_IN
C2
22p
ICS8421002I
Figure 2. CRYSTAL INPUt INTERFACE
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
CRYSTAL INPUT:
For applications not requiring the use of the crystal oscillator
input, both XTAL_IN and XTAL_OUT can be left floating.
Though not required, but for additional protection, a 1kΩ
resistor can be tied from XTAL_IN to ground.
HSTL OUTPUT
All unused HSTL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential
output pair should either be left floating or terminated.
REF_CLK INPUT:
For applications not requiring the use of the reference clock,
it can be left floating. Though not required, but for additional
protection, a 1kΩ resistor can be tied from the REF_CLK to
ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
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FEMTOCLOCKS™ CRYSTAL-TOHSTL FREQUENCY SYNTHESIZER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8421002I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8421002I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 122mA = 422.7mW
Power (outputs)MAX = 32.8mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 32.8mW = 65.6mW
Total Power_MAX (3.465V, with all outputs switching) = 422.7mW + 65.6mW = 488.3mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.488W * 66.6°C/W = 117.5°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA
FOR
20-PIN TSSOP, FORCED CONVECTION
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
114.5°C/W
73.2°C/W
98.0°C/W
66.6°C/W
88.0°C/W
63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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FEMTOCLOCKS™ CRYSTAL-TOHSTL FREQUENCY SYNTHESIZER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
HSTL output driver circuit and termination are shown in Figure 3.
VDDO
Q1
VOUT
RL
50Ω
FIGURE 3. HSTL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load.
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = (V
/R ) * (V
OH_MAX
Pd_L = (V
OL_MAX
L
-V
DD_MAX
/R ) * (V
L
DD_MAX
)
OH_MAX
-V
)
OL_MAX
Pd_H = (1V/50Ω) * (2V - 1V) = 20mW
Pd_L = (0.4V/50Ω) * (2V - 0.4V) = 12.8mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 32.8mW
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FEMTOCLOCKS™ CRYSTAL-TOHSTL FREQUENCY SYNTHESIZER
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE
FOR
20 LEAD TSSOP
θJA by Velocity (Meters per Second)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
114.5°C/W
73.2°C/W
98.0°C/W
66.6°C/W
88.0°C/W
63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8421002I is: 2951
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PACKAGE OUTLINE - G SUFFIX
FOR
FEMTOCLOCKS™ CRYSTAL-TOHSTL FREQUENCY SYNTHESIZER
20 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
Millimeters
SYMBOL
MIN
N
MAX
20
A
--
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
6.40
E
E1
6.60
6.40 BASIC
4.30
e
4.50
0.65 BASIC
L
0.45
0.75
α
0°
8°
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
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TABLE 9. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
ICS8421002AGI
ICS8421002AI
20 Lead TSSOP
tube
-40°C to 85°C
ICS8421002AGIT
ICS8421002AI
20 Lead TSSOP
2500 tape & reel
-40°C to 85°C
ICS8421002AGILF
ICS421002AIL
20 Lead "Lead-Free" TSSOP
tube
-40°C to 85°C
ICS8421002AGILFT
ICS421002AIL
20 Lead "Lead-Free" TSSOP
2500 tape & reel
-40°C to 85°C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free Configuration and are RoHS compliant.
The aforementioned trademarks, HiPerClockS and FEMTOCLOCKS are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended
without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in
life support devices or critical medical instruments.
8421002AGI
www.icst.com/products/hiperclocks.html
13
REV. A FEBRUARY 7, 2006
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