ICST ICS8430-51 600mhz, low jitter lvcmos/ lvttl-to-3.3v lvpecl frequency synthesizer Datasheet

PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8430-51
600MHZ, LOW JITTER
LVCMOS/ LVTTL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
FEATURES
The ICS8430-51 is a general purpose, dual output
,&6
Crystal-to-3.3V Differential LVPECL High Frequency
HiPerClockS™ Synthesizer and a member of the HiPerClockS™
family of High Performance Clock Solutions from
ICS. The ICS8430-51 has a selectable TEST_CLK
or crystal inputs. The VCO operates at a frequency range of
200MHz to 700MHz. With FOUT0 configured to divide the
VCO frequency by 2, output frequency steps as small as
2MHz can be achieved using a 16MHz crystal or reference clock.
FOUT1 provides an additional divide by 16 and 180° phase shift.
Output frequencies up to 600MHz can be programmed using
the serial or parallel interfaces to the configuration logic. The low
jitter and frequency range of the ICS8430-51 make it an ideal
clock generator for most clock tree applications.
• Dual differential 3.3V LVPECL outputs
• Selectable crystal oscillator interface
or LVCMOS/LVTTL TEST_CLK
• Maximum output frequency: 600MHz
• Crystal input frequency range: 14MHz to 25MHz
• VCO range: 200MHz to 700MHz
• Parallel or serial interface for programming counter
and output dividers
• RMS period jitter: 2.6ps (typical)
• Cycle-to-cycle jitter: 17ps (typical)
• 3.3V supply voltage
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
BLOCK DIAGRAM
PIN ASSIGNMENT
XTAL2
nP_LOAD
VCO_SEL
M0
M1
M2
M3
M4
VCO_SEL
XTAL_SEL
32 31 30 29 28 27 26 25
TEST_CLK
0
XTAL1
OSC
1
XTAL2
÷ 16
PLL
PHASE DETECTOR
MR
VCO
÷N
XTAL_SEL
M8
4
21
VCCA
N0
5
20
S_LOAD
N1
6
19
S_DATA
N2
7
18
S_CLOCK
VEE
8
17
MR
ICS8430-51
9 10 11 12 13 14 15 16
VEE
nFOUT0
FOUT0
nFOUT0
FOUT1
nFOUT1
TEST
M0:M8
22
FOUT0
CONFIGURATION
INTERFACE
LOGIC
3
VCCO
÷16
TEST_CLK
M7
nFOUT1
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
XTAL1
23
FOUT1
÷2
24
2
VCC
1
1
M6
TEST
÷M
0
M5
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
N0:N2
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
8430AY-51
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1
REV. D FEBRUARY 11, 2003
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8430-51
600MHZ, LOW JITTER
LVCMOS/LVTTL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes operation using a 16MHz crystal. Valid PLL loop divider values for
different crystal or input frequencies are defined in the Input Frequency Characteristics, Table 5, NOTE 1.
The ICS8430-51 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth. A parallel-resonant, fundamental crystal is used as the input to the on-chip oscillator. The output of the oscillator is
divided by 16 prior to the phase detector. With a 16MHz crystal, this provides a 1MHz reference frequency. The VCO of the
PLL operates over a range of 200MHz to 700MHz. The output of the M divider is also applied to the phase detector.
The phase detector and the M divider force the VCO output frequency to be 2M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too high or too low), the PLL will not achieve lock. The output of the
VCO is scaled by a divider prior to being sent to each of the LVPECL output buffers. The divider provides a 50% output duty cycle.
The programmable features of the ICS8430-51 support two input modes, programmable M divider and N output divider.
The two input operational modes are parallel and serial. Figure 1 shows the timing diagram for each mode. In parallel mode,
the nP_LOAD input is initially LOW. The data on inputs M0 through M8 and N0 through N2 is passed directly to the M divider
and N output divider. On the LOW-to-HIGH transition of the nP_LOAD input, the data is latched and the M divider remains
loaded until the next LOW transition on nP_LOAD or until a serial event occurs. As a result, the M and N bits can be
hardwired to set the M divider and N output divider to a specific default state that will automatically occur during power-up.
The TEST output is LOW when operating in the parallel input mode. The relationship between the VCO frequency, the crystal
frequency and the M divider is defined as follows:
fxtal x 2M
fVCO =
16
The M value and the required values of M0 through M8 are shown in Table 3B, Programmable VCO Frequency Function Table.
Valid M values for which the PLL will achieve lock for a 16MHz reference are defined as 100 ≤ M ≤ 350. The frequency out is
defined as follows:
fout = fVCO = fxtal x 2M
N
16
N
Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider and N output divider
when S_LOAD transitions from LOW-to-HIGH. The M divide and N output divide values are latched on the HIGH-to-LOW
transition of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is passed directly to the M divider and N output
divider on each rising edge of S_CLOCK. The serial mode can be used to program the M and N bits and test bits T1 and T0.
The internal registers T0 and T1 determine the state of the TEST output as follows:
T1
T0
TEST Output
0
0
LOW
0
1
S_Data
1
0
Output of M divider
1
1
CMOS Fout
SERIAL LOADING
S_CLOCK
T1
S_DATA
t
S_LOAD
S
t
T0
N2
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
H
t
nP_LOAD
S
PARALLEL LOADING
M0:M8, N0:N2
M, N
nP_LOAD
t
S
t
Time
H
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
*NOTE: The NULL timing slot must be observed.
8430AY-51
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2
REV. D FEBRUARY 11, 2003
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8430-51
600MHZ, LOW JITTER
LVCMOS/ LVTTL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
1, 2, 3,
28, 29, 30
31, 32,
4
Name
M5, M6, M7,
M0, M1, M2,
M3, M4
M8
Input
5, 6
N0, N1
Input
7
8, 16
N2
VEE
Input
Power
9
TEST
Output
10
VCC
FOUT1,
nFOUT1
VCCO
FOUT0,
nFOUT0
Power
11, 12
13
14, 15
Type
Input
Description
Pulldown M divider inputs. Data latched on LOW-to-HIGH transition
of nP_LOAD input. LVCMOS / LVTTL interface levels.
Pullup
Pulldown Determines output divider value as defined in Table 3C
Function Table. LVCMOS / LVTTL interface levels.
Pullup
Power
Negative supply pins.
Test output which is ACTIVE in the serial mode of operation.
Output driven LOW in parallel mode. LVCMOS/ LVTTL interface levels.
Core power supply pin.
Differential output for the synthesizer with shifted divide by 16.
3.3V LVPECL interface levels.
Output supply pin.
Output
Differential output for the synthesizer. 3.3V LVPECL interface levels.
Output
Active High Master Reset. When logic HIGH, the internal dividers
are reset causing the true outputs FOUTx to go low and the inver ted
17
MR
Input
Pulldown outputs nFOUTx to go high. When logic LOW, the internal dividers
and the outputs are enabled. Asser tion of MR does not affect loaded
M, N, and T values. LVCMOS / LVTTL interface levels.
Clocks in serial data present at S_DATA input into the shift regiser
18
S_CLOCK
Input
Pulldown
on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge
19
S_DATA
Input
Pulldown
of S_CLOCK. LVCMOS / LVTTL interface levels.
Controls transition of data from shift register into the dividers.
20
S_LOAD
Input
Pulldown
LVCMOS / LVTTL interface levels.
21
VCCA
Power
Analog supply pin.
Selects between the crystal oscillator or test clock as the PLL
22
XTAL_SEL
Input
Pullup
reference source. Selects XTAL inputs when HIGH. Selects
TEST_CLK when LOW. LVCMOS / LVTTL interface levels.
23
TEST_CLK
Input
Pulldown Test clock input. LVCMOS / LVTTL interface levels.
24, 25
XTAL1, XTAL2
Input
Crystal oscillator interface. XTAL1 is the input. XTAL2 is the output.
Parallel load input. Determines when data present at M8:M0 is
26
nP_LOAD
Input
Pulldown loaded into the M divider, and when data present at N2:N0 sets
the N output divider value. LVCMOS / LVTTL interface levels.
Determines whether synthesizer is in PLL or bypass mode.
27
VCO_SEL
Input
Pullup
LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
Input Capacitance
RPULLUP
Input Pullup Resistor
51
KΩ
RPULLDOWN
Input Pulldown Resistor
51
KΩ
8430AY-51
Test Conditions
Minimum
Typical
Maximum
4
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3
Units
pF
REV. D FEBRUARY 11, 2003
PRELIMINARY
Integrated
Circuit
Systems, Inc.
TABLE 3A. PARALLEL
AND
ICS8430-51
600MHZ, LOW JITTER
LVCMOS/LVTTL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
SERIAL MODE FUNCTION TABLE
Inputs
Conditions
MR
nP_LOAD
M
N
S_LOAD
S_CLOCK
S_DATA
H
X
X
X
X
X
X
Reset. Forces outputs LOW.
L
L
Data
Data
X
X
X
Data on M and N inputs passed directly to the M
divider and N output divider. TEST output forced LOW.
L
↑
Data
Data
L
X
X
L
H
X
X
L
↑
Data
L
H
X
X
↑
L
Data
L
H
X
X
↓
L
Data
L
H
X
X
L
X
X
H
↑
Data
L
H
X
X
NOTE: L = LOW
H = HIGH
X = Don't care
↑ = Rising edge transition
↓ = Falling edge transition
Data is latched into input registers and remains loaded
until next LOW transition or until a serial event occurs.
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
Contents of the shift register are passed to the
M divider and N output divider.
M divider and N output divider values are latched.
Parallel or serial input do not affect shift registers.
S_DATA passed directly to M divider as it is clocked.
TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE (NOTE 1)
VCO Frequency
(MHz)
M Divide
200
100
202
204
206
•
•
696
698
700
NOTE 1: These M divide
16MHz.
8430AY-51
256
M8
0
128
M7
0
101
0
102
0
103
0
•
•
•
•
348
1
349
1
350
1
values and the resulting
64
M6
1
32
M5
1
16
M4
0
8
M3
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
•
•
•
•
•
•
•
•
•
•
0
1
0
1
1
0
1
0
1
1
0
1
0
1
1
frequencies correspond to cr ystal or TEST_CLK
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4
4
M2
1
2
M1
0
1
0
1
1
1
1
•
•
•
•
1
0
1
0
1
1
input frequency of
1
M0
0
1
0
1
•
•
0
1
0
REV. D FEBRUARY 11, 2003
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8430-51
600MHZ, LOW JITTER
LVCMOS/ LVTTL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
Inputs
N2
0
N1
0
0
0
N Divider Value
FOUT0, nFOUT0 Output Frequency
(MHz)
Minimum
Maximum
100
350
N0
0
2
0
1
4
50
175
1
0
8
25
87.5
0
1
1
16
12.5
43.75
1
0
0
1
200
600
1
0
1
2
100
350
1
1
0
4
50
175
1
1
1
8
25
87.5
nFOUT0
FOUT0
nFOUT1
FOUT1
FIGURE 2. FOUTX TIMING DIAGRAM
8430AY-51
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5
REV. D FEBRUARY 11, 2003
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8430-51
600MHZ, LOW JITTER
LVCMOS/LVTTL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
4.6V
Inputs, VI
-0.5V to VCC + 0.5 V
Outputs, VO
-0.5V to VCCO + 0.5V
Package Thermal Impedance, θJA
47.9°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
VCC
Core Supply Voltage
Test Conditions
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
VCCA
Analog Supply Voltage
3.135
3.3
3.465
V
VCCO
Output Supply Voltage
3.135
3.3
3.465
V
IEE
Power Supply Current
120
mA
ICCA
Analog Supply Current
10
mA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
VIH
Input
High Voltage
VIL
Input
Low Voltage
IIH
Input
High Current
IIL
Input
Low Current
Test Conditions
TEST_CLK
VCO_SEL, S_LOAD, S_DATA,
S_CLOCK, nP_LOAD, MR,
M0:M8, N0:N2, XTAL_SEL
TEST_CLK
VCO_SEL, S_LOAD, S_DATA,
S_CLOCK, nP_LOAD,
M0:M8, N0:N2, XTAL_SEL
M0-M7, N0, N1, MR,
S_CLOCK, S_DATA, S_LOAD,
TEST_CLK, nP_LOAD
M8, N2, XTAL_SEL,
VCO_SEL
M0-M7, N0, N1, MR,
S_CLOCK, S_DATA, S_LOAD,
TEST_CLK, nP_LOAD
Maximum
Units
2
VCC + 0.3
V
2
VCC + 0.3
V
-0.3
1.3
V
-0.3
0.8
V
VCC = VIN = 3.465V
150
µA
VCC = VIN = 3.465V
5
µA
M8, N2, XTAL_SEL,
VCO_SEL
Typical
VCC = 3.465V,
VIN = 0V
-5
µA
VCC = 3.465V,
VIN = 0V
-150
µA
2.6
V
Output
TEST; NOTE 1
High Voltage
Output
TEST; NOTE 1
VOL
Low Voltage
NOTE 1: Outputs terminated with 50Ω to VCCO/2.
VOH
8430AY-51
Minimum
0.5
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6
V
REV. D FEBRUARY 11, 2003
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8430-51
600MHZ, LOW JITTER
LVCMOS/ LVTTL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Maximum
Units
VOH
Output High Voltage; NOTE 1
Parameter
Test Conditions
Minimum
VCC - 1.4
Typical
VCC - 1.0
V
VOL
Output Low Voltage; NOTE 1
VCC - 2.0
VCC - 1.7
V
1.0
V
VSWING
Peak-to-Peak Output Voltage Swing
0.6
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V. See "Parameter Information" section,
"3.3V Output Load Test Circuit" figure.
TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
fIN
Input Frequency
Test Conditions
Minimum
Typical
Maximum
Units
TEST_CLK; NOTE 1
14
25
MHz
XTAL1, XTAL2; NOTE 1
14
25
MHz
S_CLOCK
TBD
MHz
NOTE 1: For the input crystal and reference frequency range, the M value must be set for the VCO to operate within the
200MHz to 700MHz range. Using the minimum input frequency of 14MHz, valid values of M are 115 ≤ M ≤ 400.
Using the maximum frequency of 25MHz, valid values of M are 64 ≤ M ≤ 224.
TABLE 6. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Mode of Oscillation
Typical Maximum
Units
Fundamental
Frequency
14
25
Equivalent Series Resistance (ESR)
50
70
Ω
7
pF
Shunt Capacitance
MHz
TABLE 7. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
600
MHz
FMAX
Output Frequency
tjit(cc)
Cycle-to-Cycle Jitter ; NOTE 1, 3
17
ps
tjit(per)
Period Jitter, RMS; NOTE 1
2.6
ps
tsk(o)
Output Skew; NOTE 2, 3
tR
Output Rise Time
tF
Output Fall Time
M, N to nP_LOAD
tS
tH
odc
Setup Time
Hold Time
50
ps
200
700
ps
200
700
ps
5
ns
S_DATA to S_CLOCK
5
ns
S_CLOCK to S_LOAD
5
ns
M, N to nP_LOAD
5
ns
S_DATA to S_CLOCK
5
ns
S_CLOCK to S_LOAD
5
ns
Output Duty Cycle
47
PLL Lock Time
tLOCK
Parameter Measurement Information section.
NOTE 1: Jitter performance using XTAL inputs.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
8430AY-51
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7
53
%
1
ms
REV. D FEBRUARY 11, 2003
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8430-51
600MHZ, LOW JITTER
LVCMOS/LVTTL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
VCC , VCCA , VCCO = 2V
Qx
SCOPE
nFOUTx
FOUTx
LVPECL
nFOUTy
nQx
FOUTy
tsk(o)
VEE = -1.3V ± 0.165V
OUTPUT SKEW
VOH
nFOUTx
VREF
FOUTx
➤
VOL
1σ contains 68.26% of all measurements
2σ contains 95.4% of all measurements
3σ contains 99.73% of all measurements
4σ contains 99.99366% of all measurements
6σ contains (100-1.973x10-7)% of all measurements
tcycle
➤
tcycle n+1
➤
t jit(cc) = tcycle n –tcycle n+1
1000 Cycles
Histogram
Reference Point
n
➤
3.3V OUTPUT LOAD AC TEST CIRCUIT
Mean Period
(Trigger Edge)
(First edge after trigger)
PERIOD JITTER
CYCLE-TO-CYCLE JITTER
nFOUTx
FOUTx
Pulse Width
t
odc =
PERIOD
t PW
t PERIOD
odc & tPERIOD
8430AY-51
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REV. D FEBRUARY 11, 2003
PRELIMINARY
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ICS8430-51
600MHZ, LOW JITTER
LVCMOS/ LVTTL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS8430-51 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VCC, VCCA, and VCCO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 3 illustrates how
a 10Ω resistor along with a 10µF and a .01µF bypass
capacitor should be connected to each VCCA pin.
AND
.01µF
10Ω
V CCA
10 µF
.01µF
FIGURE 3. POWER SUPPLY FILTERING
OSCILLATOR INTERFACE
The ICS8430-51 features an internal oscillator that uses an
external quartz crystal as the source of its reference frequency.
A 16MHz crystal divided by 16 before being sent to the phase
detector provides the reference frequency. The oscillator is a
series resonant, multi-vibrator type design. This design provides
better stability and eliminates the need for large on chip capacitors.
Though a series resonant crystal is preferred, a parallel resonant
crystal can be used. A parallel resonant mode crystal used in a
series resonant circuit will exhibit a frequency of oscillation a few
hundred ppm lower than specified. A few hundred ppm translates
to KHz inaccuracy. In general computing applications this level
of inaccuracy is irrelevant. If better ppm accuracy is required, an
external capacitor can be added to a parallel resonant crystal in
series to pin 24. Figure 4A shows how to interface with a crystal.
ppm performance over various parallel resonant crystals.
Figure 4C shows the recommended tuning capacitance for
various parallel resonant crystals.
ICS8430-51
XTAL2
(Pin 25, LQFP)
XTAL1
(Pin 24, LQFP)
➤
CRYSTAL INPUT
3.3V
VCC
Optional
Figures 4A, 4B, and 4C show various crystal parameters
which are recommended only as guidelines. Figure 4A shows
how to interface a capacitor with a parallel resonant crystal.
Figure 3B shows the capacitor value needed for the optimum
FIGURE 4A. CRYSTAL INTERFACE
FIGURE 4B. Recommended tuning capacitance for various parallel
resonant crystals.
FIGURE 4C. Recommended tuning capacitance for various
parallel resonant crystals.
14.318
Frequency Accuracy (ppm)
Series Capacitor, C1 (pF)
60
50
15.000
40
16.667
30
19.440
20.000
20
24.000
10
0
14
15
16
17
18
19
20
21
22
23
24
25
Crystal Frequency (MHz)
100
80
60
40
20
0
-20 0
-40
-60
-80
-100
10
20
30
40
50
60
19.44MHz
Series Capacitor, C1 (pF)
16MHz
15.00MHz
8430AY-51
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REV. D FEBRUARY 11, 2003
PRELIMINARY
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ICS8430-51
600MHZ, LOW JITTER
LVCMOS/LVTTL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
drive 50Ω transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion. Figures 5A and 5B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
3.3V
Zo = 50Ω
Zo = 50Ω
5
2 Zo
FOUT
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
(VOH + VOL / VCC –2) –2
FIN
Zo = 50Ω
VCC - 2V
➤
1
FOUT
50 Ω
50Ω
RTT =
5
2 Zo
FIN
RTT
Zo = 50Ω
3
2 Zo
Zo
FIGURE 5A. LVPECL OUTPUT TERMINATION
3
2 Zo
FIGURE 5B. LVPECL OUTPUT TERMINATION
LAYOUT GUIDELINE
The schematic of the ICS8430-51 layout example used in
this layout guideline is shown in Figure 6A. The ICS8430-51
recommended PCB board layout for this example is shown
in Figure 6B. This layout example is used as a general guide-
32
31
30
29
28
27
26
25
XTAL1
REF_IN
nXTAL_SEL
VCCA
S_LOAD
S_DATA
S_CLOCK
MR
VDD
FOUT
FOUTN
VDD
TEST
8430-01
M4
M3
M2
M1
M0
VCO_SEL
nP_LOAD
XTAL2
M5
M6
M7
M8
N0
N1
N2
GND
TEST
VCC
FOUT1
nFOUT1
VCCO
FOUT0
nFOUT0
GND
1
2
3
4
5
6
7
8
X1
R7
VDD
10
24
23
22
21
20
19
18
17
C11
0.01u
REF_IN
XTAL_SEL
C16
22u
S_LOAD
S_DATA
S_CLOCK
MR
Termination A
VDD
9
10
11
12
13
14
15
16
U1
line. The layout in the actual system will depend on the
selected component types, the density of the components,
the density of the traces, and the stack up of the P.C. board.
R1
125
R3
125
Termination
B (Not shown
in the layout)
IN+
Zo = 50 Ohm
IN+
IN-
TL1
R2
50
Zo = 50 Ohm
C14
0.1u
INC15
0.1u
TL2
R2
84
FIGURE 6A. SCHEMATIC
8430AY-51
R1
50
OF
R4
84
RECOMMENDED LAYOUT
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• The traces with 50Ω transmission lines TL1 and TL2 at
FOUT and nFOUT should have equal delay and run adjacent to each other. Avoid sharp angles on the clock trace.
Sharp angle turns cause the characteristic impedance to
change on the transmission lines.
The following component footprints are used in this layout
example: All the resistors and capacitors are size 0603.
POWER
AND
GROUNDING
Place the decoupling capacitors C14 and C15 as close as possible to the power pins. If space allows, placing the decoupling
capacitor at the component side is preferred. This can reduce
unwanted inductance between the decoupling capacitor and the
power pin generated by the via.
• Keep the clock trace on the same layer. Whenever possible, avoid any vias on the clock traces. Any via on the
trace can affect the trace characteristic impedance and
hence degrade signal quality.
• To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow more space between the clock trace
and the other signal trace.
Maximize the pad size of the power (ground) at the decoupling
capacitor. Maximize the number of vias between power (ground)
and the pads. This can reduce the inductance between the power
(ground) plane and the component power (ground) pins.
• Make sure no other signal trace is routed between the
clock trace pair.
If VCCA shares the same power supply with VCC, insert the RC
filter R7, C11, and C16 in between. Place this RC filter as close
to the VCCA as possible.
CLOCK TRACES
AND
ICS8430-51
The matching termination resistors R1, R2, R3 and R4 should
be located as close to the receiver input pins as possible. Other
termination schemes can also be used but are not shown in
this example.
TERMINATION
The component placements, locations and orientations should be
arranged to achieve the best clock signal quality. Poor clock signal
quality can degrade the system performance or cause system failure. In the synchronous high-speed digital system, the clock signal
is less tolerable to poor signal quality than other signals. Any ringing on the rising or falling edge or excessive ring back can cause
system failure. The trace shape and the trace delay might be restricted by the available space on the board and the component
location. While routing the traces, the clock signal traces should be
routed first and should be locked prior to routing other signal traces.
CRYSTAL
The crystal X1 should be located as close as possible to the pins
24 (XTAL1) and 25 (XTAL2). The trace length between the X1
and U1 should be kept to a minimum to avoid unwanted parasitic
inductance and capacitance. Other signal traces should not be
routed near the crystal traces.
X1
GND
VCC
VIA
U1
PIN 1
C11
C16
VCCA
R7
Close to the input
pins of the
receiver
R4
R3
TL1N
TL1N
C15
C14
TL1
TL1
R2
TL1, TL2 are 50 Ohm traces and
equal length
FIGURE 6B. PCB BOARD LAYOUT
8430AY-51
FOR
ICS8430-51
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POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8430-51.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8430-51 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 120mA = 416mW
Power (outputs)MAX = 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30.2mW = 60.4mW
Total Power_MAX (3.465V, with all outputs switching) = 416mW + 60.4mW = 476.4mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 8 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.476W * 42.1°C/W = 90°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 8. THERMAL RESISTANCE qJA
FOR
32-PIN LQFP, FORCED CONVECTION
qJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
67.8°C/W
47.9°C/W
55.9°C/W
42.1°C/W
50.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 7.
VCCO
Q1
VOUT
RL
50
VCCO - 2V
FIGURE 7. LVPECL DRIVER CIRCUIT
TERMINATION
AND
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CCO
•
For logic high, VOUT = V
OH_MAX
(V
CCO_MAX
•
-V
OH_MAX
OL_MAX
CCO_MAX
-V
OL_MAX
– 1.0V
CCO_MAX
) = 1.0V
For logic low, VOUT = V
(V
=V
=V
CCO_MAX
– 1.7V
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
– (V
CCO_MAX
- 2V))/R ] * (V
CCO_MAX
L
-V
) = [(2V - (V
OH_MAX
CCO_MAX
-V
OH_MAX
))/R ] * (V
CCO_MAX
L
-V
OH_MAX
)=
[(2V - 1V)/50Ω] * 1V = 20.0mW
Pd_L = [(V
OL_MAX
– (V
CCO_MAX
- 2V))/R ] * (V
L
CCO_MAX
-V
OL_MAX
) = [(2V - (V
CCO_MAX
-V
OL_MAX
))/R ] * (V
L
CCO_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
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RELIABILITY INFORMATION
TABLE 9. θJAVS. AIR FLOW TABLE
qJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
67.8°C/W
47.9°C/W
55.9°C/W
42.1°C/W
50.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8430-51 is: 4,534
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PACKAGE OUTLINE - Y SUFFIX
TABLE 10. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
32
N
1.60
A
A1
0.05
0.15
A2
1.35
1.40
1.45
b
0.30
0.37
0.45
c
0.09
0.20
D
9.00 BASIC
D1
7.00 BASIC
D2
5.60
E
9.00 BASIC
E1
7.00 BASIC
E2
5.60
e
0.80 BASIC
L
0.45
q
0°
0.60
0.75
7°
0.10
ccc
Reference Document: JEDEC Publication 95, MS-026
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TABLE 11. ORDERING INFORMATION
Part/Order Number
ICS8430AY-51
ICS8430AY-51T
Marking
ICS8430AY-51
ICS8430AY-51
Package
32 Lead LQFP
32 Lead LQFP on Tape and Reel
Count
250 per tray
1000
Temperature
0°C to 70°C
0°C to 70°C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements
are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
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