ICST ICS843001AG-21 Femtoclocksâ ¢ crystal-to-3.3v lvpecl frequency synthesizer Datasheet

ICS843001-21
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
FEATURES
The ICS843001-21 is a a highly versatile, low
ICS
phase noise LVPECL Synthesizer which can
HiPerClockS™ generate low jitter reference clocks for a variety
of communications applications and is a
member of the HiPerClocks TM family of high
performance clock solutions from ICS. The dual
crystal interface allows the synthesizer to support up to
two communications standards in a given application (i.e.
1GB Ethernet with a 25MHz crystal and 1Gb Fibre Channel
using a 25.5625MHz cr ystal). The r ms phase jitter
performance is typically less than 1ps, thus making the
device acceptable for use in demanding applications such
as OC48 SONET and 10Gb Ethernet. The ICS843001-21
is packaged in a small 24-pin TSSOP package.
• One 3.3V LVPECL output pair and one LVCMOS output
• Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
• VCO range: 560MHz - 700MHz
• Supports the following applications:
SONET, Ethernet, Fibre Channel, Serial ATA, and HDTV
• RMS phase jitter @ 622.08MHz (12kHz - 20MHz):
0.80ps (typical)
Offset
Noise Power
100Hz ............... -60.3 dBc/Hz
1kHz ............... -88.5 dBc/Hz
10kHz ............. -111.9 dBc/Hz
100kHz ............. -113.0 dBc/Hz
• Full 3.3V supply mode
• 0°C to 70°C ambient operating temperature
• Available in both standard and lead-free RoHS-compliant
packages
PIN ASSIGNMENT
VCCO_CMOS
N0
N1
N2
VCCO_PECL
Q0
nQ0
VEE
VCCA
VCC
XTAL_OUT1
XTAL_IN1
BLOCK DIAGRAM
3
N2:N0
SEL0 Pulldown
N
XTAL_IN0
00
11
XTAL_OUT0
XTAL_IN1
OSC
01
Phase
Detector
10
01
00
VCO
XTAL_OUT1
TEST_CLK Pulldown
MR
24
23
22
21
20
19
18
17
16
15
14
13
REF_CLK
VEE
REF_OE
M2
M1
M0
MR
SEL1
SEL0
TEST_CLK
XTAL_IN0
XTAL_OUT0
ICS843001-21
SEL1 Pulldown
OSC
1
2
3
4
5
6
7
8
9
10
11
12
10
000
001
010
011
100
101
000
001
010
011
÷1
÷2
÷3
÷4 (default)
100
101
110
111
÷5
÷6
÷8
÷10
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
Top View
Q0
nQ0
M
÷18
÷22
÷24
÷25
÷32 (default)
÷40
Pulldown
3
M2:M0
REF_CLK
OE_REF Pulldown
843001AG-21
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1
REV. A OCTOBER 26, 2005
ICS843001-21
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
Name
1
VCCO_CMOS
Power
Type
2, 3
N0, N1
Input
Description
Output supply pin for LVCMOS output.
Pullup
4
N2
Input
Output divider select pins. Default ÷4.
L
Pulldown VCMOS/LVTTL interface levels.
5
VCCO_LVPECL
Power
Output supply pin for LVPECL output.
6, 7
Q0, nQ0
Ouput
Differential output pair. LVPECL interface levels.
8, 23
VEE
Power
Negative supply pin.
9
VCCA
Power
Analog supply pin.
10
11
12
13
14
15
VCC
XTAL_OUT1,
XTAL_IN1
XTAL_OUT0,
XTAL_IN0
TEST_CLK
Power
16, 17
SEL0, SEL1
Input
18
MR
Input
19, 20
M0, M1
Input
21
M2
Input
Pulldown Input MUX select pins. LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true output Q0 to go low and the inver ted output nQ0
Pulldown
to go high. When logic LOW, the internal dividers and the outputs are
enabled. LVCMOS/LVTTL interface levels.
Pulldown Feedback divider select pins. Default ÷32.
LVCMOS/LVTTL interface levels.
Pullup
22
REF_OE
Input
Pulldown
24
REF_CLK
Output
Input
Input
Input
Core supply pin.
Parallel resonant cr ystal interface. XTAL_OUT1 is the output,
XTAL_IN1 is the input.
Parallel resonant cr ystal interface. XTAL_OUT0 is the output,
XTAL_IN0 is the input.
Pulldown LVCMOS/LVTTL clock input.
Reference clock output enable. Default Low.
LVCMOS/LVTTL interface levels.
Reference clock output. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
Input Capacitance
4
pF
RPULLDOWN
Input Pulldown Resistor
51
kΩ
RPULLUP
Input Pullup Resistor
51
kΩ
Rout
Output Impedance
7
Ω
843001AG-21
Test Conditions
Minimum
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2
Typical
Maximum
Units
REV. A OCTOBER 26, 2005
ICS843001-21
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FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
TABLE 3A. COMMON CONFIGURATIONS TABLE
Input
Reference Clock
M Divider Value
N Divider Value
VCO (MHz)
Output Frequency
(MHz)
Application
27
22
8
594
74.25
HDTV
24.75
24
8
594
74.25
HDTV
14.8351649
40
8
593.4066
74.1758245
HDTV
19.44
32
4
622.08
155.52
SONET
19.44
32
8
622.08
77.76
SONET
19.44
32
1
622.08
622.08
SONET
19.44
32
2
622.08
311.04
SONET
19.53125
32
4
625
156.25
10 GigE
25
25
5
62 5
125
1 GigE
25
25
10
625
62.5
1 GigE
25
24
6
600
100
PCI Express
25
24
4
60 0
150
SATA
25
24
8
600
75
SATA
26.5625
24
6
637.5
106.25
Fibre Channel 1
26.5625
24
3
637.5
212.5
4 Gig Fibre Channel
26.5625
24
4
637.5
159.375
10 Gig Fibre Channel
31.25
18
3
562.5
187.5
12 Gig Ethernet
TABLE 3C. PROGRAMMABLE N OUTPUT DIVIDER
FUNCTION TABLE
TABLE 3B. PROGRAMMABLE M OUTPUT DIVIDER
FUNCTION TABLE
Inputs
Input Frequency
M2
M1
M0
M Divider
Value
0
0
0
18
31.1
38.9
0
0
0
0
1
22
25.5
31.8
0
0
1
2
0
1
0
24
23.3
29.2
0
1
0
3
0
1
1
25
22.4
28.0
0
1
1
4
1
0
0
32
17.5
21.9
1
0
0
5
1
0
1
40
14.0
17.5
1
0
1
6
1
1
0
8
1
1
1
10
Inputs
Minimum
Maximum
N2
N1
N0
0
N Divide Value
1
TABLE 3D. BYPASS MODE FUNCTION TABLE
Inputs
Reference
PLL Mode
0
XTAL0
Active
1
XTAL1
Active
1
0
TEST_CLK
Active
1
1
TEST_CLK
Bypass
SEL1
SEL0
0
0
843001AG-21
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3
REV. A OCTOBER 26, 2005
ICS843001-21
Integrated
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Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
4.6V
Inputs, VI
-0.5V to VCC + 0.5V
Outputs, IO (LVPECL)
Continuous Current
Surge Current
50mA
100mA
Outputs, VO (LVCMOS)
-0.5V to VCCO + 0.5V
Package Thermal Impedance, θJA
70°C/W (0 mps)
Storage Temperature, TSTG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
VCC
Core Supply Voltage
Test Conditions
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
VCCA
Analog Supply Voltage
3.135
3.3
3.465
V
VCCO_PECL, _CMOS
Output Supply Voltage
3.135
3.3
3.465
V
IEE
Power Supply Current
170
mA
ICCA
Analog Supply Current
11
mA
ICCO_PECL, _CMOS
Output Supply Current
8
mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
VIH
Input High Voltage
SEL0, SEL1, OE_REF,
Input
MR, M0:M2, N0:N2
Low Voltage
TEST_CLK
TEST_CLK, SEL0, SEL1,
Input
OE_REF, MR, M0, M1, N2
High Current
M2, N0, N1
VIL
IIH
IIL
VOH
Input
Low Current
Test Conditions
Minimum Typical
Maximum
Units
2
VCC + 0.3
V
-0.3
0.8
V
-0.3
1.3
V
VCC = VIN = 3.465V
150
µA
VCC = VIN = 3.465V
5
µA
TEST_CLK, SEL0, SEL1,
OE_REF, MR, M0, M1, N2
VCC = 3.465V, VIN = 0V
-5
µA
M2, N0, N1
VCC = 3.465V, VIN = 0V
-150
µA
REF_CLK
2.6
V
Output High Voltage; NOTE 1
VOL
Output Low Voltage: Note 1
REF_CLK
NOTE 1: Output terminated with 50Ω to VCCO _CMOS/2. See Parameter Measurement Information Section,
"3.3V Output Load Test Circuit Diagram".
843001AG-21
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4
0.5
V
REV. A OCTOBER 26, 2005
ICS843001-21
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
Maximum
Units
VOH
Output High Voltage; NOTE 1
Test Conditions
Minimum
VCCO - 1.4
Typical
VCCO - 0.9
V
VOL
Output Low Voltage; NOTE 1
VCCO - 2.0
VCCO - 1.7
V
VSWING
Peak-to-Peak Output Voltage Swing
0.6
1. 0
V
Maximum
Units
NOTE 1: Outputs terminated with 50Ω to VCCO_PECL - 2V.
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Mode of Oscillation
Typical
Fundamental
Frequency
12
MHz
40
MHz
Equivalent Series Resistance (ESR)
50
Ω
Shunt Capacitance
7
pF
Maximum
Units
56
700
MHz
2.3
2.8
ns
NOTE: Characterized using an 18pF parallel resonant crystal.
TABLE 6. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
fOUT
Output Frequency
Propagation Delay, TEST_CLK to
NOTE 1
REF_CLK
RMS Phase Jitter, (Random);
NOTE 2, 3
PLL VCO Lock Range
tPD
t jit(Ø)
fVCO
t R / tF
Output
Rise/Fall Time
Test Conditions
Minimum
622.08MHz (12kHz - 20MHz)
0.80
ps
560
700
MHz
LVPECL
20% to 80%
200
500
ps
LVCMOS
20% to 80%
300
800
ps
45
44
55
56
%
%
LVPECL
odc
Output Duty Cycle
LVCMOS
NOTE 1: Measured from the VCC/2 of the input to VCCO_CMOS/2 of the output.
NOTE 2: Phase jitter measured using a 19.44MHz quar tz cr ystal.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
843001AG-21
Typical
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REV. A OCTOBER 26, 2005
ICS843001-21
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FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
TYPICAL PHASE NOISE AT 622.08MHZ
➤
0
-10
OC-12 Filter
-20
-30
622.08MHz
-40
RMS Phase Jitter (Random)
12kHz to 20MHz = 0.80ps (typical)
-50
-70
Raw Phase Noise Data
-80
-90
➤
-100
-110
-120
➤
NOISE POWER dBc
Hz
-60
-130
-140
Phase Noise Result by adding
Sonet OC-12 Filter to raw data
-150
-160
-170
-180
-190
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
843001AG-21
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REV. A OCTOBER 26, 2005
ICS843001-21
Integrated
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Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
1.65±5%
2V
V CC ,
VCCA,
VCCO_LVPECL
SCOPE
Qx
SCOPE
VCC ,
VCCA,
VCCO_LVCMOS
LVPECL
Qx
LVCMOS
nQx
VEE
VEE
-1.3V±0.165V
-1.65V±5%
3.3V LVPECL OUTPUT LOAD AC TEST CIRCUIT
3.3V LVCMOS OUTPUT LOAD AC TEST CIRCUIT
nQ0
Q0
t PW
Phase Noise Plot
Noise Power
t
PERIOD
t PW
odc =
Phase Noise Mask
f1
Offset Frequency
x 100%
t PERIOD
V
CCO_LVCMOS
f2
2
REF_CLK
t PW
RMS Jitter = Area Under the Masked Phase Noise Plot
t
odc =
PERIOD
t PW
x 100%
t PERIOD
RMS PHASE JITTER
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
80%
TEST_CLK
VSW I N G
Clock
Outputs
VCC
2
80%
20%
20%
tR
VCCO_LVCMOS
tF
REF_CLK
2
t
PD
OUTPUT RISE/FALL TIME
843001AG-21
PROPAGATION DELAY
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REV. A OCTOBER 26, 2005
ICS843001-21
Integrated
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FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS843001-21 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VCC, VCCA, and VCCO_x
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10µF and a .01μF bypass
capacitor should be connected to each VCCA. The 10Ω resistor can also be replaced by a ferrite bead.
3.3V
VCC
.01μF
10Ω
VCCA
.01μF
10μF
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
below were determined using a 19.44MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error.
The ICS843001-21 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2
XTAL_IN
C1
22p
X1
18pF Parallel Cry stal
XTAL_OUT
C2
22p
ICS843001-21
ICS84332
Figure 2. CRYSTAL INPUt INTERFACE
843001AG-21
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REV. A OCTOBER 26, 2005
ICS843001-21
Integrated
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FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
CRYSTAL INPUT:
For applications not requiring the use of the crystal oscillator
input, both XTAL_IN and XTAL_OUT can be left floating.
Though not required, but for additional protection, a 1kΩ
resistor can be tied from XTAL_IN to ground.
LVCMOS OUTPUT:
All unused LVCMOS output can be left floating. We
recommend that there is no trace attached.
LVPECL OUTPUT
All unused LVPECL outputs can be left floating. We
recommend that there is no trace attached. Both sides of the
differential output pair should either be left floating or
terminated.
TEST_CLK INPUT:
For applications not requiring the use of the test clock, it can
be left floating. Though not required, but for additional
protection, a 1kΩ resistor can be tied from the TEST_CLK to
ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts
mentioned are recommended only as guidelines.
outputs are designed to drive 50Ω transmission lines.
Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which
are recommended only as guidelines. Other suitable
clock layouts may exist and it would be recommended
that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs
that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground)
or current sources must be used for functionality. These
3.3V
Zo = 50Ω
125Ω
FOUT
125Ω
FIN
Zo = 50Ω
Zo = 50Ω
FOUT
50Ω
RTT =
1
Z
((VOH + VOL) / (VCC – 2)) – 2 o
VCC - 2V
Zo = 50Ω
RTT
84Ω
FIGURE 3A. LVPECL OUTPUT TERMINATION
843001AG-21
FIN
50Ω
84Ω
FIGURE 3B. LVPECL OUTPUT TERMINATION
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REV. A OCTOBER 26, 2005
ICS843001-21
Integrated
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FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843001-21.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843001-21 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 170mA = 589.05mW
Power (outputs)MAX = 30mW/Loaded Output pair
Total Power_MAX (3.465V, with all outputs switching) = 589.05mW + 30mW = 619.05mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 65°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.619W * 65°C/W = 110.2°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE θJA
FOR
24-PIN TSSOP, FORCED CONVECTION
θJA by Velocity (Meters per Second)
Multi-Layer PCB, JEDEC Standard Test Boards
843001AG-21
0
1
2.5
70°C/W
65°C/W
62°C/W
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REV. A OCTOBER 26, 2005
ICS843001-21
Integrated
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Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 4.
VCCO
Q1
VOUT
RL
50
VCCO - 2V
FIGURE 4. LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CC
•
For logic high, VOUT = V
OH_MAX
(V
CCO_MAX
•
-V
OH_MAX
OL_MAX
CCO_MAX
-V
CC_MAX
– 0.9V
) = 0.9V
For logic low, VOUT = V
(V
=V
=V
CC_MAX
– 1.7V
) = 1.7V
OL_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
– (V
CC_MAX
- 2V))/R ] * (V
CC_MAX
L
-V
OH_MAX
) = [(2V - (V
CC_MAX
-V
OH_MAX
))/R ] * (V
CC_MAX
L
-V
OH_MAX
)=
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
– (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
) = [(2V - (V
OL_MAX
CC_MAX
-V
))/R ] * (V
OL_MAX
L
CC_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
843001AG-21
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REV. A OCTOBER 26, 2005
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FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
RELIABILITY INFORMATION
TABLE 8. θJAVS. AIR FLOW TABLE
FOR
24 LEAD TSSOP
θJA by Velocity (Meters per Second)
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
70°C/W
65°C/W
62°C/W
TRANSISTOR COUNT
The transistor count for ICS843001-21 is: 4057
843001AG-21
www.icst.com/products/hiperclocks.html
12
REV. A OCTOBER 26, 2005
ICS843001-21
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - G SUFFIX
FOR
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
24 LEAD TSSOP
TABLE 9. PACKAGE DIMENSIONS
SYMBOL
Millimeters
Minimum
N
A
Maximum
24
--
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
7.70
7.90
E
E1
6.40 BASIC
4.30
e
4.50
0.65 BASIC
L
0.45
0.75
α
0°
8°
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
843001AG-21
www.icst.com/products/hiperclocks.html
13
REV. A OCTOBER 26, 2005
ICS843001-21
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
TABLE 10. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
ICS843001AG-21
ICS843001A21
24 Lead TSSOP
tube
0°C to 70°C
ICS843001AG-21T
ICS843001A21
24 Lead TSSOP
2500 tape & reel
0°C to 70°C
ICS843001AG-21LF
ICS843001A21L
24 Lead "Lead-Free" TSSOP
tube
0°C to 70°C
ICS843001AG-21LFT
ICS843001A21L
24 Lead "Lead-Free" TSSOP
2500 tape & reel
0°C to 70°C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademarks, HiPerClockS and FemtoClocks are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use
in life support devices or critical medical instruments.
843001AG-21
www.icst.com/products/hiperclocks.html
14
REV. A OCTOBER 26, 2005
Integrated
Circuit
Systems, Inc.
ICS843001-21
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
REVISION HISTORY SHEET
Rev
A
Table
T10
T3C
Page
1
14
3
T10
9
10
A
843001AG-21
Description of Change
Features Section - added Lead-Free bullet.
Ordering Information table - added Lead-Free marking.
Programmable N Output Divider Function Table - corrected heading from
M Divide Value to N Divide value.
Added Recommendations for Unused Input and Output Pins.
Ordering Information Table - added lead-free note.
www.icst.com/products/hiperclocks.html
15
Date
2/8/05
10/26/05
REV. A OCTOBER 26, 2005
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