ICST ICS843001BGIT Femtoclocksâ ¢ crystal-to-3.3v lvpecl clock generator Datasheet

PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS843001BI
FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
GENERAL DESCRIPTION
FEATURES
The ICS843001BI is a Fibre Channel Clock
Generator and a member of the HiPerClocksTM
HiPerClockS™
family of high performance devices from ICS.
The ICS843001BI uses either a 26.5625MHz or
a 23.4375MHz crystal to synthesize 106.25MHz,
187.5MHz or 212.5MHz, using the FREQ_SEL pin. The
ICS843001BI has excellent <1ps phase jitter performance,
over the 637kHz – 10MHz integration range. The ICS843001BI
is packaged in a small 8-pin TSSOP and 16 VFQFN, making
it ideal for use in systems with limited board space.
• One differential 3.3V LVPECL output
ICS
• Crystal oscillator interface designed for 23.4375MHz or
26.5625MHz, 18pF parallel resonant crystal
• Selectable 106.25MHz, 187.5MHz or 212.5MHz
output frequency
• VCO range: 560MHz - 680MHz
• RMS phase jitter @ 106.255MHz, using a 26.5625MHz
crystal (637kHz - 10MHz): 0.60ps (typical)
• 3.3V operating supply
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS-compliant
packages
0
106.25MHz (Default)
1
212.5MHz
23.4375MHz
1
187.5MHz
NC
16 15 14 13
12
nc 2
11
Q
XTAL_OUT 3
10
nQ
9
V EE
XTAL_IN 4
5
V EE
26.5625MHz
VEE 1
6
7
VCC
26.5625MHz
Output Frequencies
nc
V CCA
FREQ_SEL
8
BLOCK DIAGRAM
FREQ_SEL
OSC
XTAL_OUT
ICS843001BI
(Pulldown)
XTAL_IN
VCC
FREQ_SEL
Crystal Frequency
nc
Inputs
nc
PIN ASSIGNMENT
FUNCTION TABLE
Phase
Detector
VCO
637.5MHz w/
26.5625MHz Ref.
÷3
16-Lead VFQFN
3mm x 3mm x 0.95 package body
K Package
Top View
1
Q
nQ
÷6
M = ÷24 (fixed)
0
VCCA
VEE
XTAL_OUT
XTAL_IN
1
2
3
4
8
7
6
5
VCC
Q
nQ
FREQ_SEL
ICS843001BI
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm package body
G Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on
initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications
without notice.
843001BKI
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REV. A OCTOBER 6, 2005
1
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS843001BI
FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Name
Type
Description
VCC
Power
Power supply pin.
VCCA
Power
Analog supply pin.
VEE
XTAL_OUT,
XTAL_IN
FREQ_SEL
Power
nQ, Q
Output
Differential clock outputs. LVPECL interface levels.
nc
Unused
No connect.
Input
Input
Negative supply pin.
Cr ystal oscillator interface. XTAL_IN is the input,
XTAL_OUT is the output.
Pulldown Frequency select pin. LVCMOS/LVTTL interface levels.
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
Input Capacitance
4
pF
RPULLDOWN
Input Pulldown Resistor
51
kΩ
843001BKI
Test Conditions
Minimum
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2
Typical
Maximum
Units
REV. A OCTOBER 6, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS843001BI
FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
4.6V
NOTE: Stresses beyond those listed under Absolute
Inputs, VI
-0.5V to VCC + 0.5V
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θJA
8 Lead TSSOP
16 Lead VFQFN
101.7°C/W (0 mps)
51.5°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
VCC
VCCA
Test Conditions
Minimum
Typical
Maximum
Units
Power Supply Voltage
3.135
3.3
3.465
V
Analog Supply Voltage
3.135
3.3
3.465
V
ICCA
Analog Supply Current
IEE
Power Supply Current
included in IEE
8
mA
60
mA
TABLE 3B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VIH
Input High Voltage
2
VCC + 0.3
V
VIL
Input Low Voltage
-0.3
0.8
V
IIH
Input High Current
FREQ_SEL
VCC = VIN = 3.465V
IIL
Input Low Current
FREQ_SEL
VCC = 3.465V, VIN = 0V
150
-5
µA
µA
TABLE 3C. LVPECL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
Maximum
Units
VOH
Output High Voltage; NOTE 1
Test Conditions
Minimum
VCC - 1.4
Typical
VCC - 0.9
V
VOL
Output Low Voltage; NOTE 1
VCC - 2.0
VCC - 1.7
V
VSWING
Peak-to-Peak Output Voltage Swing
0.6
1.0
V
Maximum
Units
26.5625
MHz
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Mode of Oscillation
Typical
Fundamental
Frequency
23.4375
Equivalent Series Resistance (ESR)
50
Ω
Shunt Capacitance
7
pF
Drive Level
1
mW
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REV. A OCTOBER 6, 2005
PRELIMINARY
Integrated
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ICS843001BI
FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
TABLE 5. AC CHARACTERISTICS, VCC = 3.3V±5%, TA = -40°C TO 85°C
Symbol
fOUT
Parameter
Output Frequency
t jit(Ø)
RMS Phase Jitter, (Random);
NOTE 1
tR / tF
Output Rise/Fall Time
odc
Output Duty Cycle
Test Conditions
Minimum
FREQ_SEL = 1
186.67
FREQ_SEL = 0
93.33
Typical
Maximum
Units
226.66
MHz
113.33
MHz
212.5MHz, (637kHz to 10MHz)
0.60
ps
187.5MHz, (1.875MHz to 20MHz)
TBD
ps
106.25MHz, (637kHz to 10MHz)
0.60
ps
20% to 80%
40 0
ps
FSEL = 0
FSEL = 1
50
50
%
%
NOTE 1: Please refer to Phase Noise Plot.
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REV. A OCTOBER 6, 2005
PRELIMINARY
Integrated
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Systems, Inc.
ICS843001BI
FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
2V
Phase Noise Plot
Qx
SCOPE
Noise Power
V CC
LVPECL
Phase Noise Mask
nQx
VEE
f1
-1.3V ± 0.165V
Offset Frequency
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
3.3V OUTPUT LOAD AC TEST CIRCUIT
RMS PHASE JITTER
nQ
80%
Q
80%
VSW I N G
Pulse Width
t
odc =
Clock
Outputs
PERIOD
20%
20%
t PW
tR
tF
t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
843001BKI
OUTPUT RISE/FALL TIME
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REV. A OCTOBER 6, 2005
PRELIMINARY
Integrated
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ICS843001BI
FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS843001BI provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VCC and VCCA should
be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10μF and a .01μF bypass
capacitor should be connected to each VCCA pin.
3.3V
VCC
.01μF
10Ω
V CCA
.01μF
10μF
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
parallel resonant crystal and were chosen to minimize the
ppm error. The optimum C1 and C2 values can be slightly
adjusted for different board layouts.
The ICS843001BI has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 2 below were determined using a 26.5625MHz, 18pF
XTAL_OUT
C1
33p
X1
18pF Parallel Crystal
XTAL_IN
C2
27p
Figure 2. CRYSTAL INPUt INTERFACE
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REV. A OCTOBER 6, 2005
PRELIMINARY
Integrated
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ICS843001BI
FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
LAYOUT GUIDELINE
an 18pF parallel resonant crystal is used. The C1 = 27pF and
C2 = 33pF are recommended for frequency accuracy. The C1
and C2 values may be slightly adjusted for optimizing frequency accuracy.
Figure 3A shows a schematic example of the ICS843001BI.
An example of LVEPCL termination is shown in this schematic. Additional LVPECL termination approaches are shown
in the LVPECL Termination Application Note. In this example,
VCC
VCCA
VCC
VCC
R2
10
C3
10uF
C4
0.01u
R1
1K
R3
133
U1
R5
133
Zo = 50 Ohm
Q
1
2
3
4
C2
33pF
26.5625MHz
18pF
VCCA
VEE
XTAL_OUT
XTAL_IN
VCC
Q0
nQ0
FREQ_SEL
8
7
6
5
VCC
+
Zo = 50 Ohm
nQ
X1
-
ICS843001
R4
82.5
C5
0.1u
C1
27pF
R6
82.5
FIGURE 3A. ICS843001BI SCHEMATIC EXAMPLE
PC BOARD LAYOUT EXAMPLE
Figure 3B shows an example of ICS843001BI P.C. board
layout. The crystal X1 footprint shown in this example allows
installation of either surface mount HC49S or through-hole
HC49 package. The footprints of other components in this
example are listed in the Table 6. There should be at least
one decoupling capacitor per power pin. The decoupling capacitors should be located as close as possible to the power
pins. The layout assumes that the board has clean analog
power ground plane.
TABLE 6. FOOTPRINT TABLE
Reference
Size
C1, C2
0402
C3
0805
C4, C5
0603
R2
0603
NOTE: Table 6, lists component
sizes shown in this layout example.
FIGURE 3B. ICS843001BI PC BOARD LAYOUT EXAMPLE
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REV. A OCTOBER 6, 2005
PRELIMINARY
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ICS843001BI
FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843001BI.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843001BI is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 60mA = 207.9mW
Power (outputs)MAX = 30mW/Loaded Output pair
Total Power_MAX (3.465V, with all outputs switching) = 207.9mW + 30mW = 237.9mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5°C/W per Table 7A below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.238W * 90.5°C/W = 106.5°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 7A. THERMAL RESISTANCE θJA
FOR
8-PIN TSSOP, FORCED CONVECTION
θJA by Velocity (Meters per Second)
Multi-Layer PCB, JEDEC Standard Test Boards
TABLE 7B.
0
1
2.5
101.7°C/W
90.5°C/W
89.8°C/W
θJAVS. AIR FLOW TABLE FOR 16 LEAD VFQFN
θJA at 0 Air Flow (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards
843001BKI
51.5°C/W
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REV. A OCTOBER 6, 2005
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ICS843001BI
FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 4.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 4. LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CC
•
For logic high, VOUT = V
OH_MAX
(V
CCO_MAX
•
-V
OH_MAX
OL_MAX
CCO_MAX
-V
CC_MAX
– 0.9V
) = 0.9V
For logic low, VOUT = V
(V
=V
=V
CC_MAX
– 1.7V
) = 1.7V
OL_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
– (V
CC_MAX
- 2V))/R ] * (V
CC_MAX
L
-V
OH_MAX
) = [(2V - (V
CC_MAX
-V
OH_MAX
))/R ] * (V
CC_MAX
L
-V
OH_MAX
)=
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
– (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OL_MAX
) = [(2V - (V
CC_MAX
-V
OL_MAX
))/R ] * (V
L
CC_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
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REV. A OCTOBER 6, 2005
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ICS843001BI
FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
RELIABILITY INFORMATION
TABLE 8A. θJAVS. AIR FLOW TABLE
FOR
8 LEAD TSSOP
θJA by Velocity (Meters Per Second)
Multi-Layer PCB, JEDEC Standard Test Boards
TABLE 8B.
0
1
2.5
101.7°C/W
90.5°C/W
89.8°C/W
θJAVS. AIR FLOW TABLE FOR 16 LEAD VFQFN
θJA at 0 Air Flow (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards
51.5°C/W
TRANSISTOR COUNT
The transistor count for ICS843001BI is: 2069
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REV. A OCTOBER 6, 2005
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ICS843001BI
FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
PACKAGE OUTLINE - G SUFFIX 8 LEAD TSSOP
TABLE 9A. PACKAGE DIMENSIONS
SYMBOL
Millimeters
Minimum
N
Maximum
8
A
--
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
2.90
E
E1
3.10
6.40 BASIC
4.30
e
4.50
0.65 BASIC
L
0.45
0.75
α
0°
8°
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
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PACKAGE OUTLINE - K SUFFIX
FOR
ICS843001BI
FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
16 LEAD VFQFN
TABLE 9B. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
SYMBOL
MINIMUM
MAXIMUM
16
N
A
0.80
1.0
A1
0
0.05
0.25 Reference
A3
b
0.18
0.30
e
0.50 BASIC
ND
4
NE
4
3.0
D
D2
0.25
1.25
3.0
E
E2
0.25
1.25
L
0.30
0.50
Reference Document: JEDEC Publication 95, MO-220
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ICS843001BI
FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
TABLE 10. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
ICS843001BGI
TBD
8 Lead TSSOP
tube
-40°C to 85°C
ICS843001BGIT
TBD
8 Lead TSSOP
2500 tape & reel
-40°C to 85°C
ICS843001BGILF
TBD
8 Lead "Lead-Free" TSSOP
tube
-40°C to 85°C
ICS843001BGILFT
TBD
8 Lead "Lead-Free" TSSOP
2500 tape & reel
-40°C to 85°C
ICS843001BKI
TBD
16 Lead VFQFN
tube
-40°C to 85°C
ICS843001BKIT
TBD
16 Lead VFQFN
2500 tape & reel
-40°C to 85°C
ICS843001BKILF
TBD
16 Lead "Lead-Free" VFQFN
tube
-40°C to 85°C
ICS843001BKILFT
TBD
16 Lead "Lead-Free" VFQFN
2500 tape & reel
-40°C to 85°C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademarks, HiPerClockS and FemtoClocks are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without
additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical
medical instruments.
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