ICST ICS843020AY-01LFT Femtoclocks-tm 680mhz, crystal-to- 3.3v differential lvpecl frequency synthesizer Datasheet

ICS843020-01
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ 680MHZ, CRYSTAL-TO3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
FEATURES
The ICS843020-01 is a general purpose, dual output Crystal-to-3.3V Differential LVPECL High FreHiPerClockS™
quency Synthesizer and a member of the
FemtoClocks™ family of High Performance Clock
Solutions from ICS. The ICS843020-01 is based
on ICS’ 3rd generation VCO technology and is capable of sub1ps RMS Phase Jitter performance, making it ideal for use in
10 Gigabit Ethernet, 10 Gigabit Fibre Channel, SONET and
Serial ATA applications.
• Dual differential 3.3V LVPECL outputs
ICS
• Selectable crystal oscillator interface
or LVCMOS/LVTTL TEST_CLK
• Output frequency range: 70MHz to 680MHz
• Crystal input frequency range: 12MHz to 32MHz
• VCO range: 560MHz to 680MHz
• Parallel or serial interface for programming feedback
and output dividers
The ICS843020-01 is a highly flexible programmable synthesizer capable of generating output frequencies over a range of
70MHz to 680MHz. The output frequency can be programmed
in small step sizes as low as 250kHz when using a 16MHz
crystal, ÷8 input divider, and output divider = ÷8.
• Input P_DIV under parallel load control
• RMS phase jitter at 156.25MHz (1.875MHz to 20MHz):
0.49ps (typical), P_DIV = ÷1
• 3.3V supply voltage
• 0°C to 70°C ambient operating temperature
• Lead-Free package fully RoHS compliant
BLOCK DIAGRAM
PIN ASSIGNMENT
VCO_SEL
XTAL_IN
PLL
MR
VCO
÷M
0
1
÷N
÷1
÷2
÷4
÷8
1
24
XTAL_OUT
M6
2
23
TEST_CLK
M7
3
22
XTAL_SEL
M8
4
21
VCCA
N0
5
20
S_LOAD
N1
6
19
S_DATA
P_DIV
7
18
S_CLOCK
VEE
8
17
MR
ICS843020-01
9 10 11 12 13 14 15 16
VEE
nFOUT0
FOUT0
VCCO
nFOUT1
FOUT1
TEST
VCC
CONFIGURATION
INTERFACE
LOGIC
M5
TEST
FOUT0
nFOUT0
FOUT1
nFOUT1
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
M0:M8
N0:N1
843020AY-01
M0
32 31 30 29 28 27 26 25
÷P
0
÷8
Float ÷1 (default)
1
÷4
PHASE DETECTOR
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
M1
1
XTAL_OUT
P_DIV
M2
OSC
M3
M4
0
XTAL_IN
nP_LOAD
TEST_CLK
VCO_SEL
XTAL_SEL
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1
REV. B APRIL 14, 2005
ICS843020-01
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ 680MHZ, CRYSTAL-TO3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes operation using a 25MHz crystal. Valid PLL loop divider values
for different crystal or input frequencies are defined in the Input Frequency Characteristics, Table 5, NOTE 1.
default state that will automatically occur during power-up. The
TEST output is LOW when operating in the parallel input mode.
The relation-ship between the VCO frequency, the crystal frequency and the M divider is defined as follows:
fVCO = fxtal x M
P
The M value and the required values of M0 through M8 are
shown in Table 3B to program the VCO Frequency Function
Table. Valid M values for which the PLL will achieve lock for a
25MHz reference are defined as 23 ≤ M ≤ 27 (P = ÷1). The
frequency out is defined as follows:
FOUT = fVCO = fxtal x M
N
NxP
The ICS843020-01 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth. A fundamental crystal is used as the input to the onchip oscillator. The output of the oscillator is fed into the phase
detector. A 25MHz crystal provides a 25MHz phase detector
reference frequency. The VCO of the PLL operates over a
range of 560MHz to 680MHz. The output of the M divider is
also applied to the phase detector.
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the
shift register are loaded into the M divider and N output divider when S_LOAD transitions from LOW-to-HIGH. The M
divide and N output divide values are latched on the HIGH-toLOW transition of S_LOAD. If S_LOAD is held HIGH, data at
the S_DATA input is passed directly to the M divider and N
output divider on each rising edge of S_CLOCK. The serial
mode can be used to program the M and N bits and test bits
T1 and T0. The internal registers T0 and T1 determine the state
of the TEST output as follows:
The phase detector and the M divider force the VCO output frequency to be M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too
high or too low), the PLL will not achieve lock. The output of the
VCO is scaled by a divider prior to being sent to each of the LVPECL
output buffers. The divider provides a 50% output duty cycle.
The ICS843020-01 supports either serial or parallel programming modes to program the M feedback divider and N output
divider. The input divider P can only be changed using the P_DIV
pin. It cannot be changed from the default ÷1 setting using the
serial interface. Figure 1 shows the timing diagram for each mode.
In parallel mode, the nP_LOAD input is initially LOW. The data
on inputs M0 through M8 and N0 and N1 is passed directly to
the M divider and N output divider. On the LOW-to-HIGH transition of the nP_LOAD input, the data is latched and the M divider
remains loaded until the next LOW transition on nP_LOAD or
until a serial event occurs. As a result, the M and N bits can be
hardwired to set the M divider and N output divider to a specific
T1
T0
TEST Output
0
0
LOW
0
1
S_Data, Shift Register Input
1
0
Output of M divider
1
1
CMOS Fout
SERIAL LOADING
S_CLOCK
S_DATA
T1
t
S
S_LOAD
T0
*NULL
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
t
H
nP_LOAD
t
S
PARALLEL LOADING
M0:M8, N0:N1, P_DIV
M, N, P
nP_LOAD
t
S
t
Time
H
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
*NOTE: The NULL timing slot must be observed.
843020AY-01
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2
REV. B APRIL 14, 2005
ICS843020-01
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ 680MHZ, CRYSTAL-TO3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
Name
1
2, 3, 4,
28, 29,
30, 31, 32
M5
M6, M7, M8,
M0, M1,
M2, M3, M4
5, 6
Type
Input
Description
Pullup
Input
M divider inputs. Data latched on LOW-to-HIGH transition of
Pulldown nP_LOAD input. LVCMOS / LVTTL interface levels.
N0, N1
Input
Pulldown
7
P_DIV
Input
8 , 16
VEE
Power
9
TEST
Output
10
VCC
Power
11, 12
FOUT1, nFOUT1
Output
Determines output divider value as defined in Table 3C,
Function Table. LVCMOS / LVTTL interface levels.
Pullup/
Input divide select. 0 = ÷8, Float = ÷1 (default), 1 = ÷4.
Pulldown
Negative supply pins.
Test output which is ACTIVE in the serial mode of operation.
Output driven LOW in parallel mode.
LVCMOS/LVTTL interface levels.
Core supply pin.
Differential output for the synthesizer. LVPECL interface levels.
13
VCCO
Power
Output supply pin.
14, 15
FOUT0, nFOUT0
Output
17
MR
Input
Pulldown
18
S_CLOCK
Input
Pulldown
19
S_DATA
Input
Pulldown
20
S_LOAD
Input
Pulldown
21
VCCA
Power
22
XTAL_SEL
Input
Pullup
23
TEST_CLK
XTAL_OUT,
XTAL_IN
Input
Pulldown
26
nP_LOAD
Input
Pulldown
27
VCO_SEL
Input
Pullup
Differential output for the synthesizer. LVPECL interface levels.
Active High Master Reset. When logic HIGH, forces the internal
dividers are reset causing the true outputs FOUTx to go low and the
inver ted outputs nFOUTx to go high. When logic LOW, the internal
dividers and the outputs are enabled. Asser tion of MR does not
affect loaded M, N, and T values. LVCMOS / LVTTL interface levels.
Clocks in serial data present at S_DATA input into the shift register
on the rising edge of S_CLOCK. LVCMOS/LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge of
S_CLOCK. LVCMOS/LVTTL interface levels.
Controls transition of data from shift register into the dividers.
LVCMOS / LVTTL interface levels.
Analog supply pin.
Selects between cr ystal or test inputs as the PLL reference source.
Selects XTAL inputs when HIGH. Selects TEST_CLK when LOW.
LVCMOS / LVTTL interface levels.
Test clock input. LVCMOS / LVTTL interface levels.
Crystal oscillator interface. XTAL_IN is the input.
XTAL_OUT is the output.
Parallel load input. Determines when data present at M8:M0 is
loaded into M divider, and when data present at N1:N0 sets the
N output divider value. LVCMOS / LVTTL interface levels.
Determines whether synthesizer is in PLL or bypass mode.
LVCMOS / LVTTL interface levels.
24, 25
Input
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
Input Capacitance
4
pF
RPULLUP
Input Pullup Resistor
51
kΩ
RPULLDOWN
Input Pulldown Resistor
51
kΩ
843020AY-01
Test Conditions
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3
Minimum
Typical
Maximum
Units
REV. B APRIL 14, 2005
ICS843020-01
Integrated
Circuit
Systems, Inc.
TABLE 3A. PARALLEL
AND
FEMTOCLOCKS™ 680MHZ, CRYSTAL-TO3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
SERIAL MODE FUNCTION TABLE
Inputs
Conditions
MR
nP_LOAD
M
N
S_LOAD S_CLOCK
S_DATA
H
X
X
X
X
X
X
Reset. Forces outputs LOW.
L
L
Data
Data
X
X
X
Data on M and N inputs passed directly to the M
divider and N output divider. TEST output forced LOW.
L
↑
Data
Data
L
X
X
L
H
X
X
L
↑
Data
L
H
X
X
↑
L
Data
L
H
X
X
↓
L
Data
M divider and N output divider values are latched.
L
H
X
X
L
X
X
Parallel or serial input do not affect shift registers.
L
H
X
X
H
↑
Data
Data is latched into input registers and remains loaded
until next LOW transition or until a serial event occurs.
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
Contents of the shift register are passed to the
M divider and N output divider.
S_DATA passed directly to M divider as it is clocked.
NOTE: L = LOW
H = HIGH
X = Don't care
↑ = Rising edge transition
↓ = Falling edge transition
TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE
WITH
P = ÷1 (P_DIV = FLOAT)
256
128
64
32
16
8
4
2
1
M8
M7
M6
M5
M4
M3
M2
M1
M0
23
0
0
0
0
1
0
1
1
1
•
•
•
•
•
•
•
•
•
•
600
24
0
0
0
0
1
1
0
0
0
•
•
•
•
•
•
•
•
•
•
•
VCO Frequency
(MHz)
M Divide
575
•
675
27
0
0
0
0
1
1
0
1
NOTE 1: These M divide values and the resulting frequencies correspond to crystal or TEST_CLK input frequency
of 25MHz.
TABLE 3C. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE
VCO Frequency
(MHz)
M Divide
575
92
WITH
1
P = ÷4 (P_DIV = 1)
256
128
64
32
16
8
4
2
1
M8
M7
M6
M5
M4
M3
M2
M1
M0
0
0
1
0
1
1
1
0
0
•
•
•
•
•
•
•
•
•
•
•
600
96
0
0
1
1
0
0
0
0
0
•
•
•
•
•
•
•
•
•
•
675
108
0
0
1
1
0
1
1
0
NOTE 1: These M divide values and the resulting frequencies correspond to crystal or TEST_CLK input frequency
of 25MHz.
843020AY-01
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4
•
0
REV. B APRIL 14, 2005
ICS843020-01
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ 680MHZ, CRYSTAL-TO3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
TABLE 3D. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE
VCO Frequency
(MHz)
M Divide
575
184
WITH
P = ÷8 (P_DIV = 0)
256
128
64
32
16
8
4
2
1
M8
M7
M6
M5
M4
M3
M2
M1
M0
0
1
0
1
1
1
0
0
0
•
•
•
•
•
•
•
•
•
•
•
600
192
0
1
1
0
0
0
0
0
0
•
•
•
•
•
•
•
•
•
•
675
216
0
1
1
0
0
1
1
1
NOTE 1: These M divide values and the resulting frequencies correspond to crystal or TEST_CLK input frequency
of 25MHz.
•
0
TABLE 3E. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
Inputs
N Divider Value
Output Frequency (MHz)
N1
N0
Minimum
Maximum
0
0
1
560
680
0
1
2
280
340
1
0
4
140
17 0
1
1
8
70
85
843020AY-01
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5
REV. B APRIL 14, 2005
ICS843020-01
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ 680MHZ, CRYSTAL-TO3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
4.6V
Inputs, VI
-0.5V to VCC + 0.5 V
Outputs, VO (LVCMOS)
-0.5V to VDDO + 0.5V
Outputs, IO (LVPECL)
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θJA
47.9°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VCC
Core Supply Voltage
3.135
3.3
3.465
V
VCCA
Analog Supply Voltage
3.135
3.3
3.465
V
VCCO
Output Supply Voltage
3.135
3.3
3.465
V
IEE
Power Supply Current
180
mA
ICCA
Analog Supply Current
13
mA
ICCO
Output Supply Current
14
mA
843020AY-01
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REV. B APRIL 14, 2005
ICS843020-01
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ 680MHZ, CRYSTAL-TO3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
VIH
Parameter
Input
High Voltage
VIL
Input
Low Voltage
VIM
Input
Mid Voltage
IIH
IIL
Input
High Current
Input
Low Current
Test Conditions
VCO_SEL, XTAL_SEL, MR,
S_LOAD, nP_LOAD, S_DATA,
S_CLOCK, TEST_CLK,
M0:M8, N0:N1
P_DIV
VCO_SEL, XTAL_SEL, MR,
S_LOAD, nP_LOAD, S_DATA,
S_CLOCK, TEST_CLK,
M0:M8, N0:N1
P_DIV
Minimum
Typical
2
Maximum
Units
VCC + 0.3
V
VCC - 0.4
V
-0.3
VCC/2 - 0.1
P_DIV
0.8
V
VCC + 0.4
V
VCC/2 + 0.1
V
M0-M4, M6-M8, N0, N1, MR,
S_CLOCK, TEST_CLK, P_DIV
S_DATA, S_LOAD, nP_LOAD
VCC = VIN = 3.465V
150
µA
M5, XTAL_SEL, VCO_SEL
VCC = VIN = 3.465V
5
µA
M0-M4, M6-M8, N0, N1, MR,
S_CLOCK, TEST_CLK,
S_DATA, S_LOAD, nP_LOAD
VCC = 3.465V,
VIN = 0V
-5
µA
M5, P_DIV,
XTAL_SEL, VCO_SEL,
VCC = 3.465V,
VIN = 0V
-150
µA
2.6
V
VOH
Output
High Voltage
TEST; NOTE 1
VOL
Output
Low Voltage
TEST; NOTE 1
0.5
V
Maximum
Units
NOTE 1: Outputs terminated with 50Ω to VCCO/2.
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
VOH
Output High Voltage; NOTE 1
VCCO - 1.4
VCCO - 0.9
V
VOL
Output Low Voltage; NOTE 1
VCCO - 2.0
VCCO - 1.7
V
1.0
V
VSWING
Peak-to-Peak Output Voltage Swing
0.6
NOTE 1: Outputs terminated with 50 Ω to VCCO - 2V. See "Parameter Measurement Information" section,
"3.3V Output Load Test Circuit".
843020AY-01
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REV. B APRIL 14, 2005
ICS843020-01
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ 680MHZ, CRYSTAL-TO3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
TEST_CLK; NOTE 1
12
32
MHz
XTAL_IN, XTAL_OUT;
Input Frequency
12
32
MHz
fIN
NOTE 1
S_CLOCK
32
MHz
e
s
e
t
f
o
r
t
h
e
V
C
O
t
o
o
p
e
r
a
t
e
w
i
t
h
i
n
the
NOTE 1: For the input crystal and TEST_CLK frequency range, the M value must b
560MHz to 680MHz range. Using the minimum input frequency of 12MHz, valid values of M are 47 ≤ M ≤ 57, with input
divider P = ÷1 (P_DIV = Float). Using the maximum frequency of 32MHz, valid values of M are 18 ≤ M ≤ 21.
TABLE 6. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Mode of Oscillation
Typical Maximum
Units
Fundamental
32
MHz
Equivalent Series Resistance (ESR)
Frequency
12
50
Ω
Shunt Capacitance
7
pF
Drive Level
1
mW
TABLE 7. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
tsk(o)
Output Frequency
RMS Phase Jitter, (Random);
NOTE 1, 4
Output Skew; NOTE 2, 3
tR / tF
Output Rise/Fall Time
tS
Setup Time
FOUT
tjit(Ø)
tH
odc
Hold Time
Minimum
Typical
70
156.25MHz
(1.875MHz to 20MHz)
20% to 80%
Units
680
MHz
0.49
175
ps
10
ps
800
ps
M, N to nP_LOAD
5
ns
S_DATA to S_CLOCK
5
ns
S_CLOCK to S_LOAD
5
ns
M, N to nP_LOAD
5
ns
S_DATA to S_CLOCK
5
ns
S_CLOCK to S_LOAD
5
ns
Output Duty Cycle
47
PLL Lock Time
tLOCK
See Parameter Measurement Information section.
NOTE 1: Please refer to the Phase Noise Plot.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Tested with P_DIV = VCC/2.
843020AY-01
Maximum
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8
53
%
1
ms
REV. B APRIL 14, 2005
ICS843020-01
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ 680MHZ, CRYSTAL-TO3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
TYPICAL PHASE NOISE AT 156.25MHZ
➤
0
-10
-20
Filter
-40
156.25MHz
-50
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.49ps (typical)
-60
-70
-80
-90
Raw Phase Noise Data
-100
➤
NOISE POWER dBc
Hz
-30
-110
-120
-130
-140
➤
-150
-160
-170
Phase Noise Result by adding
a Filter to raw data
-180
-190
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
843020AY-01
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REV. B APRIL 14, 2005
ICS843020-01
Integrated
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Systems, Inc.
FEMTOCLOCKS™ 680MHZ, CRYSTAL-TO3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
2V
V CC ,
VCCA,
VCCO
SCOPE
Qx
nFOUTx
FOUTx
LVPECL
nFOUTy
nQx
VEE
FOUTy
t sk(o)
-1.3V ± 0.165V
OUTPUT SKEW
3.3V OUTPUT LOAD AC TEST CIRCUIT
Phase Noise Plot
nFOUTx
Noise Power
FOUTx
Pulse Width
t
Phase Noise Mask
odc =
f1
Offset Frequency
PERIOD
t PW
t PERIOD
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
PHASE JITTER
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
80%
80%
VSW I N G
Clock
Outputs
20%
20%
tR
tF
OUTPUT RISE/FALL TIME
843020AY-01
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REV. B APRIL 14, 2005
ICS843020-01
Integrated
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Systems, Inc.
FEMTOCLOCKS™ 680MHZ, CRYSTAL-TO3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS843020-01 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VCC, VCCA, and VCCO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 2 illustrates how
a 10Ω resistor along with a 10μF and a .01μF bypass
capacitor should be connected to each VCCA pin.
3.3V
VCC
.01μF
10Ω
V CCA
.01μF
10μF
FIGURE 2. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
suitable for most applications. Additional accuracy can be
achieved by adding two small capacitors C1 and C2 as shown in
Figure 3.
A crystal can be characterized for either series or parallel mode
operation. The ICS843020-01 has a built-in crystal oscillator circuit.
This interface can accept either a series or parallel crystal without
additional components and generate frequencies with accuracy
XTAL_OUT
C1
18p
X1
18pF Parallel Crystal
XTAL_IN
C2
22p
Figure 3. CRYSTAL INPUt INTERFACE
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TERMINATION
FOR
FEMTOCLOCKS™ 680MHZ, CRYSTAL-TO3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
drive 50Ω transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion. Figures 4A and 4B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
3.3V
Zo = 50Ω
125Ω
FOUT
125Ω
FIN
Zo = 50Ω
Zo = 50Ω
FOUT
50Ω
RTT =
1
Z
((VOH + VOL) / (VCC – 2)) – 2 o
Zo = 50Ω
VCC - 2V
RTT
84Ω
FIGURE 4A. LVPECL OUTPUT TERMINATION
843020AY-01
FIN
50Ω
84Ω
FIGURE 4B. LVPECL OUTPUT TERMINATION
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FEMTOCLOCKS™ 680MHZ, CRYSTAL-TO3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
LAYOUT GUIDELINE
The schematic of the ICS843020-01 layout example used in
this layout guideline is shown in Figure 5A. The ICS84302001 recommended PCB board layout for this example is shown
in Figure 5B. This layout example is used as a general guide-
line. The layout in the actual system will depend on the selected component types, the density of the components, the
density of the traces, and the stack up of the P.C. board.
C1
C2
VCC
'1'
Float
'0'
M5
M6
M7
M8
N0
N1
P_DIV
VEE
R6
1K
VCC
ICS843020-01
Logic Input Pin Examples
Set Logic
Input to
'1'
VCC
RU1
1K
Set Logic
Input to
'0'
VCC
XTAL_O
T_CLK
nXTAL_SEL
VCCA
S_LOAD
S_DATA
S_CLOCK
MR
9
10
11
12
VCC
13
FOUT
14
FOUTN 15
16
1
2
3
4
5
6
7
8
R5
1K
TEST
VCC
FOUT1
nFOUT1
VCCO
FOUT0
nFOUT0
VEE
U1
M4
M3
M2
M1
M0
VCO_SEL
nP_LOAD
XTAL_I
32
31
30
29
28
27
26
25
X1
RD1
Not Install
24
23
22
21
20
19
18
17
R7
10
REF_IN
XTAL_SEL
VCCA
S_LOAD
S_DATA
S_CLOCK
C11
0.01u
C16
10u
VCC
R1
133
R3
133
Zo = 50 Ohm
C14
0.1u
TL1
C15
0.1u
RU2
Not Install
To Logic
Input
pins
VCC
+
Zo = 50 Ohm
-
TL2
To Logic
Input
pins
R2
82.5
R4
82.5
RD2
1K
FIGURE 5A. SCHEMATIC OF RECOMMENDED LAYOUT
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FEMTOCLOCKS™ 680MHZ, CRYSTAL-TO3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
The following component footprints are used in this layout
example:
• The differential 50Ω output traces should have the
same length.
All the resistors and capacitors are size 0603.
• Avoid sharp angles on the clock trace. Sharp angle
turns cause the characteristic impedance to change on
the transmission lines.
POWER AND GROUNDING
Place the decoupling capacitors C14 and C15, as close as possible to the power pins. If space allows, placement of the
decoupling capacitor on the component side is preferred. This
can reduce unwanted inductance between the decoupling capacitor and the power pin caused by the via.
• Keep the clock traces on the same layer. Whenever possible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power
and ground planes and the component power and ground pins.
• To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
The RC filter consisting of R7, C11, and C16 should be placed
as close to the VCCA pin as possible.
• Make sure no other signal traces are routed between the
clock trace pair.
CLOCK TRACES AND TERMINATION
• The matching termination resistors should be located as
close to the receiver input pins as possible.
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital systems,
the clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
trace delay might be restricted by the available space on the board
and the component location. While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
CRYSTAL
The crystal X1 should be located as close as possible to the pins
25 (XTAL_IN) and 24 (XTAL_OUT). The trace length between the
X1 and U1 should be kept to a minimum to avoid unwanted parasitic inductance and capacitance. Other signal traces should not
be routed near the crystal traces.
GND
X1
C1
C2
VCC
VIA
U1
PIN 1
C16
C11
VCCA
R7
Close to the input
pins of the
receiver
TL1N
C15
TL1
C14
TL1
R1
R2
TL1N
R3
R4
TL1, TL21N are 50 Ohm
traces and equal length
FIGURE 5B. PCB BOARD LAYOUT FOR ICS843020-01
843020AY-01
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FEMTOCLOCKS™ 680MHZ, CRYSTAL-TO3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843020-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843020-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 180mA = 623.7mW
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power_MAX (3.465V, with all outputs switching) = 623.7mW + 60mW = 683.7mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 8 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.684W * 42.1°C/W = 98.8°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 8. THERMAL RESISTANCE θJA
FOR
32-PIN LQFP, FORCED CONVECTION
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
67.8°C/W
47.9°C/W
55.9°C/W
42.1°C/W
50.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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FEMTOCLOCKS™ 680MHZ, CRYSTAL-TO3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 6.
VCCO
Q1
VOUT
RL
50
VCCO - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CCO
•
For logic high, VOUT = V
OH_MAX
(V
CCO_MAX
•
-V
OH_MAX
OL_MAX
CCO_MAX
-V
OL_MAX
CCO_MAX
– 0.9V
) = 0.9V
For logic low, VOUT = V
(V
=V
=V
CCO_MAX
– 1.7V
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
– (V
CCO_MAX
- 2V))/R ] * (V
CCO_MAX
L
-V
OH_MAX
) = [(2V - (V
CCO_MAX
-V
OH_MAX
))/R ] * (V
CCO_MAX
L
-V
OH_MAX
)=
[(2V - 0.9V)/50Ω) * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
– (V
CCO_MAX
- 2V))/R ] * (V
L
CCO_MAX
-V
OL_MAX
) = [(2V - (V
CCO_MAX
-V
OL_MAX
))/R ] * (V
L
CCO_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50Ω) * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
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FEMTOCLOCKS™ 680MHZ, CRYSTAL-TO3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
RELIABILITY INFORMATION
TABLE 9. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
67.8°C/W
47.9°C/W
55.9°C/W
42.1°C/W
50.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS843020-01 is: 5371
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FEMTOCLOCKS™ 680MHZ, CRYSTAL-TO3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP
TABLE 10. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
32
N
A
--
--
1.60
A1
0.05
--
0.15
A2
1.35
1.40
1.45
b
0.30
0.37
0.45
c
0.09
--
0.20
D
9.00 BASIC
D1
7.00 BASIC
D2
5.60 Ref.
E
9.00 BASIC
E1
7.00 BASIC
E2
5.60 Ref.
e
0.80 BASIC
0.75
L
0.45
0.60
θ
0°
--
7°
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
843020AY-01
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FEMTOCLOCKS™ 680MHZ, CRYSTAL-TO3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
TABLE 11. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
ICS843020AY-01
ICS843020A01
32 Lead LQFP
tray
0°C to 70°C
ICS843020AY-01T
ICS843020A01
32 Lead LQFP
1000 tape & reel
0°C to 70°C
ICS843020AY-01LF
TBD
32 Lead "Lead-Free" LQFP
tray
0°C to 70°C
ICS843020AY-01LFT
TB D
32 Lead "Lead-Free" LQFP
1000 tape & reel
0°C to 70°C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademarks, HiPerClockS™ and FemtoClocks™ are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
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ICS843020-01
FEMTOCLOCKS™ 680MHZ, CRYSTAL-TO3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
REVISION HISTORY SHEET
Rev
Table
Page
1
B
T5
8
Input Frequency Characteristics Table - changed 14MHz to 12MHz, and
changed M values to correspond with the 12MHz change.
T6
8
Cr ystal Characteristics Table - Change Frequency min. from 14MHz to 12MHz.
843020AY-01
Description of Change
Features section - changed Cr ystal frequency range bullet from 14MHz to
12MHz.
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20
Date
4/14/05
REV. B APRIL 14, 2005
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