ICST ICS843404 Lvcmos/crystal-to-3.3v lvpecl and lvds clock generator Datasheet

ICS843404
Integrated
Circuit
Systems, Inc.
LVCMOS/CRYSTAL-TO-3.3V LVPECL AND
LVDS CLOCK GENERATOR
GENERAL DESCRIPTION
FEATURES
The ICS843404 is a low phase noise Fibre
Channel Clock Generator and is a member of
HiPerClockS™ the HiPerClockSTM family of high performance
clock solutions from ICS. The device provides
two banks of one LVPECL output per bank and
one bank of two LVDS outputs. Each bank can be
independently set by using their respective frequency select
pins for the following output frequencies: 318.75MHz,
212.5MHz, 159.375MHz or 106.25MHz, using a 25.5MHz
18pF parallel resonant crystal. The ICS843404 can also be
driven from a 25.5MHz single-ended reference clock. For
system debug or test purposes, the PLL can be bypassed
using the VCO_SEL pin.
• Three banks of outputs: one bank of two LVDS outputs
and two banks of one LVPECL output
ICS
• Selectable crystal oscillator interface or
LVCMOS/LVTTL single-ended reference clock input
• Four independently selectable output frequency on each
bank: 318.75MHz, 212.5MHz, 159.375MHz and 106.25MHz
• Maximum output frequency: 318.75MHz
• Crystal input frequency: 25.5MHz
• VDDO_LVPECL can be set for 3.3V or 2.5V, allowing the
device to generate 3.3V or 2.5V LVPECL levels
• RMS phase jitter at 106.25MHz, using a 25.5MHz crystal
(637kHz to 10MHz intergration): 2.65ps (typical)
PIN ASSIGNMENT
MR
VCO_SEL
VDDo_LVDS
LVDS0
nLVDS0
LVDS1
nLVDS1
nc
LVPECL_FSELB0
LVPECL_FSELB1
nc
V DDA
LVPECL_FSELA0
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Offset
Noise Power
100Hz ................. -89.1 dBc/Hz
1kHz ................. -112.7 dBc/Hz
10kHz ................. -128.0 dBc/Hz
100kHz ................. -130.2 dBc/Hz
LVDS_FSEL0
LVDS_FSEL1
VDDO _LVPECL
LVPECLA0
nLVPECLA0
LVPECLB0
nLVPECLB0
XTAL_SEL
TEST_CLK
GND
GND
• Supply voltage modes:
• VDD = VDDA = 3.3V
• VDDO_LVPECL = 3.3V or 2.5V
• VDDO_LVDS = 3.3V
XTAL_IN
XTAL_OUT
LVPECL_FSELA1
• 0°C to 70°C ambient operating temperature
• Available in both standard and lead-free RoHS-compliant
packages
ICS843404
• Industrial termperature information available upon request
28-Lead TSSOP, 173-MIL
4.4mm x 9.7mm x 0.92mm
body package
G Package
Top View
BLOCK DIAGRAM
VCO_SEL Pullup
LVPECL_FSELA1:0
00
01
10
11
TEST_CLK Pulldown
0
0
25.5MHz
XTAL_IN
OSC
XTAL_OUT
1
Phase
Detector
VCO
637.5MHz
1
VDDO_LVPECL
LVPECLA0
÷2
÷3
÷4
÷6
nLVPECLA0
LVPECL_FSELB1:0
00
01
10
11
LVPECLB0
÷2
÷3
÷4
÷6
nLVPECLB0
(Fixed)
LVDS0
LVDS_FSEL1:0
XTAL_SEL Pullup
M = 25 (fixed)
00
01
10
11
÷2
÷3
÷4
÷6
nLVDS0
LVDS1
nLVDS1
MR Pulldown
843404AG
VDDO_LVDS
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1
REV. A OCTOBER 17, 2005
ICS843404
Integrated
Circuit
Systems, Inc.
LVCMOS/CRYSTAL-TO-3.3V LVPECL AND
LVDS CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
1
MR
Input
2
VCO_SEL
Input
3
VDDO_LVDS
Power
4, 5
LVDS0, nLVDS0
Output
Differential output pair. LVDS interface levels.
6, 7
LVDS1, nLVDS1
Output
Differential output pair. LVDS interface levels.
8, 11
nc
Unused
9
LVPECL_FSELB0
Input
10
LVPECL_FSELB1
Input
12
VDDA
Power
13
LVPECL_FSELA0
Input
14
VDD
Power
15
LVPECL_FSELA1
Input
18, 19
XTAL_OUT,
XTAL_IN
GND
Power
20
TEST_CLK
Input
21
XTAL_SEL
Input
16, 17
Input
Description
Active HIGH Master Reset. When logic HIGH, the internal dividers
are reset causing the true outputs LVPECLx/LVDSx to go low and the
Pulldown inver ted outputs nLVPECLx/nLVDSx to go high. When logic LOW, the
internal dividers and the outputs are enabled.
LVCMOS/LVTTL interface levels.
VCO select pin. When HIGH, PLL is enabled. When LOW, PLL is in
Pullup
Bypass mode. LVCMOS/LVTTL interface levels.
Output supply pin for LVDS outputs.
No connect.
Frequency select pin for LVPECLB outputs. See Table 3B.
Pulldown
LVCMOS/LVTTL interface levels.
Frequency select pin for LVPECLB outputs. See Table 3B.
Pullup
LVCMOS/LVTTL interface levels.
Analog supply pin.
Frequency select pin for LVPECLA outputs. See Table 3B.
Pulldown
LVCMOS/LVTTL interface levels.
Core supply pin.
Frequency select pin for LVPECLA outputs. See Table 3B.
Pullup
LVCMOS/LVTTL interface levels.
Parallel resonant cr ystal interface. XTAL_IN is the input,
XTAL_OUT is the output.
Negative supply pin.
Pulldown LVCMOS/LVTTL clock input.
Selects between cr ystal or TEST_CLK inputs as the the PLL
Pullup Reference source. Selects XTAL inputs when HIGH. Selects
TEST_CLK when LOW. LVCMOS/LVTTL interface levels.
nLVPECLB0,
Output
Differential output pair. LVPECL interface levels.
LVPECLB0
nLVPECLA0,
24, 25
Ouput
Differential output pair. LVPECL interface levels.
LVPECLA0
26
VDDO_LVPECL
Power
Output supply pin for LVPECL outputs.
LVDS_FSEL1,
Frequency select pins for LVDS outputs. See Table 3A.
27, 28
Input
Pulldown
LVDS_FSEL0
LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
22, 23
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
Input Capacitance
4
pF
RPULLUP
Input Pullup Resistor
51
kΩ
RPULLDOWN
Input Pulldown Resistor
51
kΩ
843404AG
Test Conditions
Minimum
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2
Typical
Maximum
Units
REV. A OCTOBER 17, 2005
ICS843404
Integrated
Circuit
Systems, Inc.
LVCMOS/CRYSTAL-TO-3.3V LVPECL AND
LVDS CLOCK GENERATOR
TABLE 3A. LVDS FREQUENCY SELECT FUNCTION TABLE
Inputs
LVDS_FSEL1
LVDS_FSEL0
LVDS Output Divider
LVDS Output Frequency (MHz)
(25.5MHz Crystal)
0
0
2
318.75 (default)
0
1
3
212.5
1
0
4
159.375
1
1
6
106.25
TABLE 3B. LVPECLA0 FREQUENCY SELECT FUNCTION TABLE
Inputs
LVPECL_FSELA1
LVPECL_FSELA0
0
0
LVPECLA0
Output Divider
2
LVPECLA0
Output Frequency (MHz)
(25.5MHz Crystal)
318.75
0
1
3
212.5
1
0
4
159.375 (default)
1
1
6
106.25
TABLE 3C. LVPECLB0 FREQUENCY SELECT FUNCTION TABLE
Inputs
LVPECLB0
Output Frequency (MHz)
(25.5MHz Crystal)
LVPECL_FSELB1
LVPECL_FSELB0
0
0
LVPECLB0
Output Divider
2
0
1
3
212.5
1
0
4
159.375 (default)
1
1
6
106.25
843404AG
318.75
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3
REV. A OCTOBER 17, 2005
ICS843404
Integrated
Circuit
Systems, Inc.
LVCMOS/CRYSTAL-TO-3.3V LVPECL AND
LVDS CLOCK GENERATOR
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
NOTE: Stresses beyond those listed under Absolute
Inputs, VI
-0.5V to VDD + 0.5V
Outputs, IO (LVPECL Outputs)
Continuous Current
Surge Current
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
50mA
100mA
operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Character-
Outputs, IO (LVDS Outputs)
Continuous Current
Surge Current
10mA
15mA
Package Thermal Impedance, θJA
49.8°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO_LVPECL = VDDO_LVDS = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
Minimum
Typical
Maximum
Units
VDD
Core Supply Voltage
Test Conditions
3.135
3.3
3.465
V
VDDA
Analog Supply Voltage
3.135
3.3
3.465
V
VDDO_LVPECL
Output Supply Voltage
3.135
3.3
3.465
V
3.135
3.3
3.465
VDDO_LVDS
Output Supply Voltage
IDD
Power Supply Current
100
mA
IDDA
IDDO_LVPECL
Analog Supply Current
25
mA
Output Supply Current
20
mA
IDDO_LVDS
Output Supply Current
55
mA
V
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO_LVPECL = 2.5V±5%, TA = 0°C TO 70°C
Symbol
Parameter
VDD
VDDA
Minimum
Typical
Maximum
Units
Core Supply Voltage
3.135
3.3
3.465
V
Analog Supply Voltage
3.135
3.3
3.465
V
VDDO_LVPECL
Output Supply Voltage
2.375
2.5
2.625
V
IDD
Power Supply Current
IDDA
IDDO_LVPECL
Analog Supply Current
20
mA
Output Supply Current
20
mA
843404AG
Test Conditions
70
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4
mA
REV. A OCTOBER 17, 2005
ICS843404
Integrated
Circuit
Systems, Inc.
LVCMOS/CRYSTAL-TO-3.3V LVPECL AND
LVDS CLOCK GENERATOR
TABLE 4C. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDD = VDDO_LVPECL = VDDO_LVDS = 3.3V±5%,
A
VDD = VDD = 3.3V±5%, VDDO_LVPECL = 2.5V±5%, TA = 0°C TO 70°C
A
Symbol Parameter
Test Conditions
VIH
Input High Voltage
VIL
Input Low Voltage
TEST_CLK, MR,
LVPECL_FSELA0,
LVPECL_FSELB0,
Input
LVDS_FSEL0, LVDS_FSEL1
High Current
LVPECL_FSELA1,
LVPECL_FSELB1,
VCO_SEL, XTAL_SEL
TEST_CLK, MR,
LVPECL_FSELA0,
LVPECL_FSELB0,
Input
LVDS_FSEL0, LVDS_FSEL1
Low Current
LVPECL_FSELA1,
LVPECL_FSELB1,
VCO_SEL, XTAL_SEL
IIH
IIL
Minimum Typical
Maximum
Units
2
VDD + 0.3
V
-0.3
0.8
V
150
µA
VDD = VIN = 3.465V
VDD = VIN = 3.465V
5
µA
VDD = 3.465V, VIN = 0V
-5
µA
VDD = 3.465V, VIN = 0V
-150
µA
TABLE 4D. LVPECL DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO_LVPECL = 3.3V±5% OR 2.5V±5%, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VOH
Output High Voltage; NOTE 1
VDDO_LVPECL - 1.4
VDDO_LVPECL - 0.9
V
VOL
Output Low Voltage; NOTE 1
VDDO_LVPECL - 2.0
VDDO_LVPECL - 1.7
V
VSWING
Peak-to-Peak Output Voltage Swing
0.6
1. 0
V
NOTE 1: Outputs terminated with 50Ω to VDDO_LVPECL - 2V.
TABLE 4E. LVDS DC CHARACTERISTICS, VDD = VDDA = VDDO_LVDS = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
VOD
Differential Output Voltage
Δ VOD
VOD Magnitude Change
VOS
Offset Voltage
Δ VOS
VOS Magnitude Change
Test Conditions
Minimum
Typical
Maximum
Units
350
mV
4
mV
1.35
V
5
mV
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Mode of Oscillation
Typical Maximum
Units
Fundamental
Frequency
25.5
MHz
Ω
Equivalent Series Resistance (ESR)
50
Shunt Capacitance
7
pF
Drive Level
1
mW
NOTE: Characterized using an 18pF parallel resonant cr ystal.
843404AG
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5
REV. A OCTOBER 17, 2005
ICS843404
Integrated
Circuit
Systems, Inc.
LVCMOS/CRYSTAL-TO-3.3V LVPECL AND
LVDS CLOCK GENERATOR
TABLE 6A. AC CHARACTERISTICS, VDD = VDDA = VDDO_LVPECL = VDDO_LVDS = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
fIN
Cr ystal Input Frequency
Test Conditions
fMAX
Output Frequency
Bank Skew; NOTE 1
t sk(o)
Output Skew; NOTE 2, 3
LVPECL
RMS Phase Jitter,
(Random); NOTE 4
LVDS
PLL Lock Time
tR / tF
Output Rise/Fall Time
Maximum
25.5
LVPECL
tL
Typical
LVDS
t sk(b)
t jit(Ø)
Minimum
Units
MHz
318.75
MHz
30
ps
65
ps
585
ps
318.75MHz (12kHz - 20MHz)
3.22
ps
212.5MHz (1.274MHz - 20MHz)
3.18
ps
159.375MHz (12kHz- 20MHz)
3.06
ps
106.25MHz (637kHz - 10MHz)
2.65
ps
318.75MHz (12kHz - 20MHz)
2.84
ps
212.5MHz (1.274MHz - 20MHz)
2.93
ps
159.375MHz (12kHz- 20MHz)
4.32
ps
106.25MHz (637kHz - 10MHz)
3.81
ps
20% to 80%
350
1
ms
850
ps
odc
Output Duty Cycle
48
52
NOTE 1: Defined as skew within a bank of outputs at the same voltages and with equal load conditions.
NOTE 2: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at the differential cross point.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: All phase noise plots are taken using 25.5MHz cr ystal. Refer to the Phase Noise Plots on the next page.
%
TABLE 6B. AC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO_LVPECL = 2.5V±5%, TA = 0°C TO 70°C
Symbol
Parameter
fIN
Cr ystal Input Frequency
Test Conditions
fMAX
Output Frequency
ps
LVPECL
65
ps
585
LVPECL
RMS Phase Jitter,
(Random); NOTE 4
LVDS
Output Rise/Fall Time
MHz
MHz
Output Skew; NOTE 2, 3
tR / tF
ps
318.75MHz (12kHz - 20MHz)
2.84
ps
212.5MHz (1.274MHz - 20MHz)
4.22
ps
159.375MHz (12kHz- 20MHz)
4.74
ps
106.25MHz (637kHz - 10MHz)
3.96
ps
318.75MHz (12kHz - 20MHz)
2.84
ps
212.5MHz (1.274MHz - 20MHz)
2.93
ps
159.375MHz (12kHz- 20MHz)
4.32
ps
106.25MHz (637kHz - 10MHz)
3.81
20% to 80%
350
ps
1
ms
850
ps
odc
Output Duty Cycle
48
52
NOTE 1: Defined as skew within a bank of outputs at the same voltages and with equal load conditions.
NOTE 2: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at the differential cross point.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: All phase noise plots are taken using 25.5MHz cr ystal. Refer to the Phase Noise Plots on the next page.
843404AG
Units
30
t sk(o)
PLL Lock Time
Maximum
25.5
318.75
Bank Skew; NOTE 1
tL
Typical
LVDS
t sk(b)
t jit(Ø)
Minimum
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6
%
REV. A OCTOBER 17, 2005
ICS843404
Integrated
Circuit
Systems, Inc.
LVCMOS/CRYSTAL-TO-3.3V LVPECL AND
LVDS CLOCK GENERATOR
TYPICAL PHASE NOISE AT 106.25MHZ FOR LVPECL
➤
0
-10
-20
Fibre Channel Filter
-30
106.25MHz
RMS Phase Jitter (Random)
637kHz to 10MHz = 2.65ps (typical)
-50
-60
-70
-80
-90
Raw Phase Noise Data
-100
➤
NOISE POWER dBc
Hz
-40
-110
-120
-130
-140
-150
➤
-160
-170
Phase Noise Result by adding
Fibre Channel Filter to raw data
-180
-190
10
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE AT 106.25MHZ FOR LVDS
0
➤
-10
-20
Fibre Channel Filter
-40
106.25MHz
-50
RMS Phase Jitter (Random)
637kHz to 10MHz = 3.81ps (typical)
-60
-70
-80
-90
-100
➤
NOISE POWER dBc
Hz
-30
-110
Raw Phase Noise Data
-120
-130
-140
-150
-160
➤
-170
Phase Noise Result by adding
Fibre Channel Filter to raw data
-180
-190
10
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
843404AG
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7
REV. A OCTOBER 17, 2005
ICS843404
Integrated
Circuit
Systems, Inc.
LVCMOS/CRYSTAL-TO-3.3V LVPECL AND
LVDS CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
2V
VDD,
VDDA,
VDDO_LVPECL
Qx
SCOPE
Qx
3.3V±5%
POWER SUPPLY
+ Float GND -
LVPECL
SCOPE
LVDS
nQx
nQx
GND
-1.3V±0.165V
LVPECL 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
LVDS 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
2.8V±0.04V
2V
Phase Noise Plot
Qx
Noise Power
VDD,
VDDA,
VDDO_LVPECL
SCOPE
LVPECL
GND
Phase Noise Mask
nQx
Offset Frequency
f1
-0.5V±0.125V
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
LVPECL 3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
RMS PHASE JITTER
nLVPECLx,
nLVDSx
LVPECLx,
LVDSx
nLVPECLy,
nLVDSy
LVPECLy,
LVDSy
nLVPECLx,
nLVDSx
LVPECLx,
LVDSx
t PERIOD
tsk(o)
OUTPUT SKEW
843404AG
Pulse Width
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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8
REV. A OCTOBER 17, 2005
ICS843404
Integrated
Circuit
Systems, Inc.
LVCMOS/CRYSTAL-TO-3.3V LVPECL AND
LVDS CLOCK GENERATOR
nLVDS0
80%
80%
LVDS0
VOD
Clock
Outputs
nLVDS1
20%
20%
tR
tF
LVDS1
tsk(b)
LVDS BANK SKEW (MAXIMUM VALUE)
LVDS OUTPUT RISE/FALL TIME
VDDO_LVDS
out
80%
DC Input
VSW I N G
Clock
Outputs
LVDS
➤
80%
➤
20%
20%
tR
out
tF
VOS/Δ VOS
➤
OFFSET VOLTAGE SETUP
LVPECL OUTPUT RISE/FALL TIME
VDDO_LVDS
➤
out
➤
LVDS
100
VOD/Δ VOD
out
➤
DC Input
DIFFERENTIAL OUTPUT VOLTAGE SETUP
843404AG
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9
REV. A OCTOBER 17, 2005
ICS843404
Integrated
Circuit
Systems, Inc.
LVCMOS/CRYSTAL-TO-3.3V LVPECL AND
LVDS CLOCK GENERATOR
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS843404 provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VDD, VDDA, and
VDDO_X should be individually connected to the power supply plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 24Ω resistor along with a 10µF and a .01μF bypass
capacitor should be connected to each VDDA. The 24Ω resistor can also be replaced by a ferrite bead.
3.3V
VDD
.01μF
24Ω
VDDA
.01μF
10μF
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS843404 has been characterized with 18pF parallel
resonant crystals. The capacitor values shown in Figure 2
below were determined using a 25.5MHz 18pF parallel
resonant crystal and were chosen to minimize the ppm
error.
XTAL_OUT
C1
18p
X1
18pF Parallel Crystal
XTAL_IN
C2
22p
ICS843404
Figure 2. CRYSTAL INPUt INTERFACE
843404AG
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10
REV. A OCTOBER 17, 2005
ICS843404
Integrated
Circuit
Systems, Inc.
LVCMOS/CRYSTAL-TO-3.3V LVPECL AND
LVDS CLOCK GENERATOR
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
CRYSTAL INPUT:
For applications not requiring the use of the crystal oscillator
input, both XTAL_IN and XTAL_OUT can be left floating.
Though not required, but for additional protection, a 1kΩ
resistor can be tied from XTAL_IN to ground.
LVPECL OUTPUT
All unused LVPECL outputs can be left floating. We
recommend that there is no trace attached. Both sides of the
differential output pair should either be left floating or
terminated.
TEST_CLK INPUT:
For applications not requiring the use of the clock, it can be
left floating. Though not required, but for additional protection,
a 1kΩ resistor can be tied from the TEST_CLK to ground.
LVDS OUTPUT
All unused LVDS output pairs can be either left floating or
terminated with 100Ω across. If they are left floating, we
recommend that there is no trace attached.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 3. In a 100Ω
differential transmission line environment, LVDS drivers
require a matched load termination of 100Ω across near
the receiver input. For a multiple LVDS outputs buffer, if only
partial outputs are used, it is recommended to terminate the
un-used outputs.
3.3V
3.3V
LVDS_Driv er
+
R1
100
-
Ω Differential
100 100Ω
Ohm
Differiential Transmission
Transmission Line
Line
FIGURE 3. TYPICAL LVDS DRIVER TERMINATION
843404AG
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REV. A OCTOBER 17, 2005
ICS843404
Integrated
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LVCMOS/CRYSTAL-TO-3.3V LVPECL AND
LVDS CLOCK GENERATOR
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current
sources must be used for functionality. These outputs are
designed to drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating
frequency and minimize signal distortion. Figures 4A and
4B show two different layouts which are recommended
only as guidelines. Other suitable clock layouts may exist
and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V
Zo = 50Ω
125Ω
FOUT
125Ω
FIN
Zo = 50Ω
Zo = 50Ω
FOUT
50Ω
RTT =
1
Z
((VOH + VOL) / (VCC – 2)) – 2 o
VCC - 2V
Zo = 50Ω
RTT
84Ω
FIGURE 4A. LVPECL OUTPUT TERMINATION
843404AG
FIN
50Ω
84Ω
FIGURE 4B. LVPECL OUTPUT TERMINATION
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ICS843404
Integrated
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TERMINATION
FOR
LVCMOS/CRYSTAL-TO-3.3V LVPECL AND
LVDS CLOCK GENERATOR
2.5V LVPECL OUTPUT
Figure 5A and Figure 5B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating 50Ω to VDD - 2V. For VDDO = 2.5V, the VDDO - 2V is very close to
ground level. The R3 in Figure 5B can be eliminated and the
termination is shown in Figure 5C.
2.5V
VDDO=2.5V
2.5V
2.5V
VDDO=2.5V
R1
250
Zo = 50 Ohm
R3
250
+
Zo = 50 Ohm
Zo = 50 Ohm
+
-
Zo = 50 Ohm
2,5V LVPECL
Driv er
-
R1
50
2,5V LVPECL
Driv er
R2
62.5
R2
50
R4
62.5
R3
18
FIGURE 5B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 5A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VDDO=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
2,5V LVPECL
Driv er
R1
50
R2
50
FIGURE 5C. 2.5V LVPECL TERMINATION EXAMPLE
843404AG
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REV. A OCTOBER 17, 2005
ICS843404
Integrated
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Systems, Inc.
LVCMOS/CRYSTAL-TO-3.3V LVPECL AND
LVDS CLOCK GENERATOR
LAYOUT GUIDELINE
Figure 6 shows a schematic example of the ICS843404. An
example of LVEPCL termination is shown in this schematic.
Additional LVPECL termination approaches are shown in the
LVPECL Termination Application Note. In this example, an
18pF parallel resonant 25.5MHz crystal is used. The C1=27pF
and C2=33pF are recommended for frequency accuracy. For
different board layout, the C1 and C2 may be slightly adjusted for optimizing frequency accuracy.
VDDO
U1
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
R7
24
C5
0.1u
MR
LVDS_FSEL0
VCO_SEL
LVDS_FSEL1
VDDO_LVDS VDDO_LVPECL
LVDS0
LVPECLA0
nLVDS0
nLVPECLA0
LVDS1
LVPECLB0
nLVDS1
nLVPECLB0
nc
XTAL_SEL
LVPECL_FSELB0 TEST_CLK
LVPECL_FSELB1
GND
nc
GND
VDDA
XTAL_IN
LVPECL_FSELA0 XTAL_OUT
VDD
LVPECL_FSELA1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Zo = 50
+
Zo = 50
-
X1
ICS843404
25.5 MHz
C2
22pF
C3
10u
R2
50
R1
50
R3
50
C1
18pF
C4
0.1u
Zo = 50
+
R4
100
Zo = 50
(U1,3)
VDDO
C6
0.1u
-
(U1,26)
C7
0.1u
VDD = 3.3V
VDDO = 3.3V
FIGURE 6. ICS843404 SCHEMATIC EXAMPLE
843404AG
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ICS843404
Integrated
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LVCMOS/CRYSTAL-TO-3.3V LVPECL AND
LVDS CLOCK GENERATOR
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843404.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843404 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IDD_TYP = 3.465V * 100mA = 346.5mW
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power_MAX (3.465V, with all outputs switching) = 346.5mW + 60mW = 406.5mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of
the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. moderate
air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 43.9°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.407W * 43.9°C/W = 87.8°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air
flow,
and the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE θJA FOR 28-PIN TSSOP, FORCED CONVECTION
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
82.9°C/W
49.8°C/W
68.7°C/W
43.9°C/W
60.5°C/W
41.2°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
843404AG
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LVCMOS/CRYSTAL-TO-3.3V LVPECL AND
LVDS CLOCK GENERATOR
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 7.
VCCO
Q1
VOUT
RL
50
VCCO - 2V
FIGURE 7. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a
termination
voltage of V - 2V.
DD
•
For logic high, VOUT = V
OH_MAX
(V
DDO_MAX
•
-V
OH_MAX
OL_MAX
DDO_MAX
-V
CC_MAX
– 0.9V
) = 0.9V
For logic low, VOUT = V
(V
=V
=V
– 1.7V
CC_MAX
) = 1.7V
OL_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
– (V
DD_MAX
- 2V))/R ] * (V
DD_MAX
L
-V
OH_MAX
) = [(2V - (V
DD_MAX
-V
OH_MAX
))/R ] * (V
DD_MAX
L
-V
OH_MAX
)=
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
– (V
DD_MAX
- 2V))/R ] * (V
L
DD_MAX
-V
OL_MAX
) = [(2V - (V
DD_MAX
-V
))/R ] * (V
OL_MAX
L
DD_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
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ICS843404
Integrated
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LVCMOS/CRYSTAL-TO-3.3V LVPECL AND
LVDS CLOCK GENERATOR
RELIABILITY INFORMATION
TABLE 8. θJAVS. AIR FLOW TABLE FOR 28 LEAD TSSOP
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
82.9°C/W
49.8°C/W
68.7°C/W
43.9°C/W
60.5°C/W
41.2°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS843404 is: 2314
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PACKAGE OUTLINE - G SUFFIX
FOR
LVCMOS/CRYSTAL-TO-3.3V LVPECL AND
LVDS CLOCK GENERATOR
28 LEAD TSSOP
TABLE 9. PACKAGE DIMENSIONS
SYMBOL
Millimeters
Minimum
Maximum
N
28
A
--
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
9.60
9.80
E
E1
6.40 BASIC
4.30
e
4.50
0.65 BASIC
L
0.45
0.75
α
0°
8°
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
843404AG
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ICS843404
Integrated
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LVCMOS/CRYSTAL-TO-3.3V LVPECL AND
LVDS CLOCK GENERATOR
TABLE 10. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
ICS843404AG
ICS843404AG
28 Lead TSSOP
tube
0°C to 70°C
ICS843404AGT
ICS843404AG
28 Lead TSSOP
1000 tape & reel
0°C to 70°C
ICS843404AGLF
ICS843404AGLF
28 Lead "Lead Free" TSSOP
tube
0°C to 70°C
ICS843404AGLFT
ICS843404AGLF
28 Lead "Lead Free" TSSOP
1000 tape & reel
0°C to 70°C
NOTE: Pats that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use
in life support devices or critical medical instruments.
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