ICST ICS844003AGI-01 Femtoclocksâ ¢ crystal-to-lvds frequency synthesizer Datasheet

PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844003I-01
FEMTOCLOCKS™CRYSTAL-TO-LVDS
FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
FEATURES
The ICS844003I-01 is a 3 differential output LVDS
Synthesizer designed to generate Ethernet referHiPerClockS™ ence clock frequencies and is a member of the
HiPerClocks™ family of high performance clock
solutions from ICS. Using a 19.53125MHz or
25MHz, 18pF parallel resonant crystal, the following frequencies can be generated based on the settings of 4 frequency
select pins (DIV_SEL[A1:A0], DIV_SEL[B1:B0]): 625MHz,
312.5MHz, 156.25MHz, and 125MHz. The 844003I-01 has 2
output banks, Bank A with 1 differential LVDS output pair and
Bank B with 2 differential LVDS output pairs.
• Three LVDS outputs on two banks, A Bank with one LVDS
pair and B Bank with 2 LVDS output pairs
The two banks have their own dedicated frequency select
pins and can be independently set for the frequencies mentioned above. The ICS844003I-01 uses ICS’ 3rd generation
low phase noise VCO technology and can achieve 1ps or
lower typical rms phase jitter, easily meeting Ethernet jitter
requirements. The ICS844003I-01 is packaged in a small
24-pin TSSOP package.
• 3.3V output supply mode
ICS
• Using a 19.53125MHz or 25MHz crystal, the two output
banks can be independently set for 625MHz, 312.5MHz,
156.25MHz or 125MHz
• Selectable crystal oscillator interface or LVCMOS/LVTTL
single-ended input
• VCO range: 490MHz to 680MHz
• RMS phase jitter @ 156.25MHz (1.875MHz - 20MHz):
0.56ps (typical)
• -40°C to 85°C ambient operating temperature
PIN ASSIGNMENT
DIV_SELB0
VCO_SEL
MR
VDDO_A
QA0
nQA0
CLK_ENB
CLK_ENA
FB_DIV
VDDA
VDD
DIV_SELA0
BLOCK DIAGRAM
24
23
22
21
20
19
18
17
16
15
14
13
DIV_SELB1
VDDO_B
QB0
nQB0
QB1
nQB1
XTAL_SEL
TEST_CLK
XTAL_IN
XTAL_OUT
GND
DIV_SELA1
ICS844003I-01
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
Top View
CLK_ENA Pullup
DIV_SELA[1:0] Pullup
VCO_SEL
1
2
3
4
5
6
7
8
9
10
11
12
Pullup
QA0
TEST_CLK Pulldown
0
XTAL_IN
OSC
1
0
Phase
Detector
VCO
00
÷1
01
10
11
÷2
÷3
÷4 (default)
00
01
÷2
÷4
nQB0
10
11
÷5
÷8 (default)
QB1
nQA0
1
XTAL_OUT
XTAL_SEL Pullup
QB0
FB_DIV
0 = ÷25 (default)
1 = ÷32
FB_DIV Pulldown
DIV_SELB[1:0] Pullup
MR
nQB1
Pulldown
CLK_ENB Pullup
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
844003AGI-01
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1
REV. A MAY 31, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844003I-01
FEMTOCLOCKS™CRYSTAL-TO-LVDS
FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
1,
24
Name
DIV_SELB0,
DIV_SELB1
Type
2
VCO_SEL
Input
3
MR
Input
4
VDDO_A
Power
5, 6
QA0, nQA0
Ouput
7
CLK_ENB
Input
Pullup
8
CLK_ENA
Input
Pullup
9
FB_DIV
Input
Pulldown
10
VDDA
Power
11
12,
13
14
VDD
DIV_SELA0,
DIV_SELA1
GND
Power
15, 16
XTAL_OUT,
XTAL_IN
Input
17
TEST_CLK
Input
18
XTAL_SEL
Input
19, 20
nQB1, QB1
Output
21, 22
nQB0, QB0
Output
Input
Input
Power
Description
Division select pin for Bank B. Default = HIGH.
Pullup
LVCMOS/LVTTL interface levels. See Table 3C.
VCO select pin. When Low, the PLL is bypassed and the crystal reference
or TEST_CLK (depending on XTAL_SEL setting) are passed directly to the
Pullup
output dividers. Has an internal pullup resistor so the PLL is not bypassed
by default. LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs Qx to go low and the inver ted outputs nQx
Pulldown to go high. When logic LOW, the internal dividers and the outputs are
enabled. Has an internal pulldown resistor so the power-up default state
of outputs and dividers are enabled. LVCMOS/LVTTL interface levels.
Output supply pin for Bank A outputs.
Differential output pair. LVDS interface levels.
Synchronizing clock enable for Bank B outputs. Active High output enable.
When logic HIGH, the output pair in Bank B is enabled. When logic LOW,
the QB outputs are LOW and nQB outputs are HIGH. Has an internal
pullup resistor so the default power-up state of output is enabled.
LVCMOS/LVTTL interface levels. See Figure 1.
Synchronizing clock enable for Bank A outputs. Active High output enable.
When logic HIGH, the output pair in Bank A is enabled. When logic LOW,
the QA output is LOW and nQA output is HIGH. Has an internal pullup
resistor so the default power-up state of output is enabled.
LVCMOS/LVTTL interface levels. See Figure 1.
Feedback divide select. When Low (default), the feedback divider is set
for ÷25. When HIGH, the feedback divider is set for ÷32.
LVCMOS/LVTTL interface levels. See Table 3D.
Analog supply pin.
Core supply pin.
Division select pin for Bank A. Default = HIGH.
Pullup
LVCMOS/LVTTL interface levels. See Table 3C.
Power supply ground.
Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is
the input. XTAL_IN is also the overdrive pin if you want to overdrive the
crystal circuit with a single-ended reference clock.
Single-ended reference clock input. Has an internal pulldown resistor to
Pulldown pull to low state by default. Can leave floating if using the crystal interface.
LVCMOS/LVTTL interface levels.
Crystal select pin. Selects between the single-ended TEST_CLK or crystal
interface. Has an internal pullup resistor so the crystal interface is selected
Pullup
by default. LVCMOS/LVTTL interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Power
Output supply pin for Bank B outputs.
23
VDDO_B
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
Input Capacitance
Test Conditions
Minimum
Typical
4
Maximum
Units
pF
RPULLDOWN
Input Pulldown Resistor
51
kΩ
RPULLUP
Input Pullup Resistor
51
kΩ
844003AGI-01
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REV. A MAY 31, 2005
PRELIMINARY
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Circuit
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ICS844003I-01
FEMTOCLOCKS™CRYSTAL-TO-LVDS
FREQUENCY SYNTHESIZER
TABLE 3A. BANK A FREQUENCY TABLE
25
0
0
0
25
1
25
QA0/nQA0
Output
Frequency
(MHz)
625
25
0
0
1
25
2
12.5
312.5
Inputs
Crystal Frequency
(MHz)
FB_DIV
DIV_SELA1 DIV_SELA0
Feedback
Divider
Bank A
Output Divider
M/N
Multiplication
Factor
20
0
0
1
25
2
12.500
250
22.5
0
1
0
25
3
8.333
187.5
25
0
1
1
25
4
6.25
156.25
24
0
1
1
25
4
6.25
150
20
0
1
1
25
4
6.25
125
19.44
1
0
0
32
1
32
622.08
19.44
1
0
1
32
2
16
311.04
15.625
1
0
1
32
2
16
250
18.75
1
1
0
32
3
10.667
200
19.44
1
1
1
32
4
8
155.52
18.75
1
1
1
32
4
8
150
15.625
1
1
1
32
4
8
125
Bank B
Output Divider
M/N
Multiplication
Factor
2
12.5
TABLE 3B. BANK B FREQUENCY TABLE
Inputs
QB0/nQB0
Output
Frequency
(MHz)
312.5
Crystal Frequency
(MHz)
FB_DIV
DIV_SELB1
DIV_SELB0
Feedback
Divider
25
0
0
0
25
20
0
0
0
25
2
12.5
250
25
0
0
1
25
4
6.25
156.25
24
0
0
1
25
4
6.25
150
20
0
0
1
25
4
6.25
125
25
0
1
0
25
5
5
125
25
0
1
1
25
8
3.125
78.125
24
0
1
1
25
8
3.125
75
20
0
1
1
25
8
3.125
62.5
19.44
1
0
0
32
2
16
311.04
15.625
1
0
0
32
2
16
250
19.44
1
0
1
32
4
8
155.52
18.75
1
0
1
32
4
8
150
15.625
1
0
1
32
4
8
125
15.625
1
1
0
32
5
6.4
100
19.44
1
1
1
32
8
4
77.76
18.75
1
1
1
32
8
4
75
15.625
1
1
1
32
8
4
62.5
844003AGI-01
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ICS844003I-01
FEMTOCLOCKS™CRYSTAL-TO-LVDS
FREQUENCY SYNTHESIZER
TABLE 3C. OUTPUT BANK CONFIGURATION SELECT FUNCTION TABLE
Inputs
Outputs
DIV_SELA1
DIV_SELA0
0
0
Inputs
Outputs
QA, nQA
DIV_SELB1
DIV_SELB0
QBx, nQBx
0
÷1
0
0
÷2
1
÷2
0
1
÷4
1
0
÷3
1
0
÷5
1
1
÷4 (default)
1
1
÷8 (default)
TABLE 3D. FEEDBACK DIVIDER CONFIGURATION SELECT
FUNCTION TABLE
Inputs
FB_DIV
Feedback Divide
0
÷2 5
1
÷32
Enabled
Disabled
TEST_CLK
CLK_ENx
nQA0,
nQB0:nQB1
QA0,
QB0:QB1
FIGURE 1. CLK_EN TIMING DIAGRAM
TABLE 3E. CLK_ENA SELECT FUNCTION TABLE
Inputs
TABLE 3F. CLK_ENB SELECT FUNCTION TABLE
Outputs
Inputs
Outputs
CLK_ENA
QA0
nQA0
CLK_ENB
QB0:QB1
nQB0:nQB1
0
LOW
HIGH
0
LOW
HIGH
1
Active
Active
1
Active
Active
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ICS844003I-01
FEMTOCLOCKS™CRYSTAL-TO-LVDS
FREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5V
Outputs, IO
Continuous Current
Surge Current
10mA
15mA
Package Thermal Impedance, θJA
70°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO_A = VDDO_B = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
VDD
Core Supply Voltage
Test Conditions
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
VDDA
Analog Supply Voltage
3.135
3.3
3.465
V
VDDO_A, B
Output Supply Voltage
3.135
3.3
3.465
V
IDD
Power Supply Current
102
mA
IDDA
Analog Supply Current
10
mA
IDDO_A, B
Output Supply Current
50
mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO_A = VDDO_B = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
IIL
844003AGI-01
Input
High Current
Input
Low Current
TEST_CLK, MR, FB_DIV
DIV_SELB0, DIV_SELB1,
DIV_SELA0, DIV_SELA1,
VCO_SEL, XTAL_SEL,
CLK_ENA, CLK_ENB
TEST_CLK, MR, FB_DIV
DIV_SELB0, DIV_SELB1,
DIV_SELA0, DIV_SELA1,
VCO_SEL, XTAL_SEL,
CLK_ENA, CLK_ENB
Test Conditions
Minimum
VDD = 3.3V
2
VDD = 3.3V
-0.3
Typical
Maximum
Units
VDD + 0.3
V
0.8
V
VDD = VIN = 3.465V
150
µA
VDD = VIN = 3.465V
5
µA
VDD = 3.465V, VIN = 0V
-5
µA
VDD = 3.465V, VIN = 0V
-150
µA
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ICS844003I-01
FEMTOCLOCKS™CRYSTAL-TO-LVDS
FREQUENCY SYNTHESIZER
TABLE 4C. LVDS DC CHARACTERISTICS, VDD = VDDA = VDDO_A = VDDO_B = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
VOD
Differential Output Voltage
Δ VOD
VOD Magnitude Change
VOS
Offset Voltage
Δ VOS
VOS Magnitude Change
Test Conditions
Minimum
Typical
Maximum
350
0
mV
50
1.35
0
Units
mV
V
50
mV
Maximum
Units
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Mode of Oscillation
Typical
Fundamental
FB_DIV = ÷25
19.6
27.2
MHz
FB_DIV = ÷32
15.313
21.25
MHz
Equivalent Series Resistance (ESR)
50
Ω
Shunt Capacitance
7
pF
Drive Level
1
mW
Maximum
Units
680
MHz
Frequency
NOTE: Characterized using an 18pF parallel resonant cr ystal.
TABLE 6. AC CHARACTERISTICS, VDD = VDDA = VDDO_A = VDDO_B = 3.3V±5%, TA = -40°C TO 85°C
Symbol
fOUT
tsk(b)
tsk(o)
tjit(Ø)
t R / tF
Parameter
Output Frequency Range
Test Conditions
Minimum
Output Divider = ÷1
490
Output Divider = ÷2
245
340
MHz
Output Divider = ÷3
163.33
226.67
MHz
Output Divider = ÷4
122.5
170
MHz
Output Divider = ÷5
98
136
MHz
Output Divider = ÷8
61.25
85
MHz
Bank Skew, NOTE 1
Output Skew; NOTE 2, 4
RMS Phase Jitter (Random);
NOTE 3
Output Rise/Fall Time
Typical
8
ps
11
ps
Outputs @ Different Frequencies
109
ps
625MHz (1.875MHz - 20MHz)
0.53
ps
312.5MHz (1.875MHz - 20MHz)
0.53
ps
156.25MHz (1.875MHz - 20MHz)
0.56
ps
125MHz (1.875MHz - 20MHz)
0.58
ps
20% to 80%
325
ps
Outputs @ Same Frequency
odc
Output Duty Cycle
50
NOTE 1: Defined as skew within a bank of outputs at the same voltages and with equal load conditions.
NOTE 2: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Please refer to the Phase Noise Plots.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
844003AGI-01
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REV. A MAY 31, 2005
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ICS844003I-01
FEMTOCLOCKS™CRYSTAL-TO-LVDS
FREQUENCY SYNTHESIZER
TYPICAL PHASE NOISE AT 156.25MHZ
➤
0
-10
-20
-30
10Gb Ethernet Filter
156.25MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.56ps (typical)
-70
-80
Raw Phase Noise Data
-90
-100
-110
-120
-130
-140
-150
-160
➤
➤
NOISE POWER dBc
Hz
-40
-50
-60
-170
-180
-190
Phase Noise Result by adding
10Gb Ethernet Filter to raw data
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
844003AGI-01
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ICS844003I-01
FEMTOCLOCKS™CRYSTAL-TO-LVDS
FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
VDD
Noise Power
Phase Noise Plot
SCOPE
Qx
Power Supply
+
Float GND
-
LVDS
Phase Noise Mask
nQx
Offset Frequency
f1
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
LVDS 3.3V OUTPUT LOAD AC TEST CIRCUIT
RMS PHASE JITTER
nQA0,
nQB0, nQB1
nQx
QA0,
QB0, QB1
Qx
t PW
t
nQy
Qy
odc =
tsk(o)
PERIOD
t PW
x 100%
t PERIOD
OUTPUT SKEW
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
nQB0
80%
80%
QB0
VSW I N G
Clock
Outputs
nQB1
20%
20%
tR
tF
QB1
tsk(b)
OUTPUT RISE/FALL TIME
BANK SKEW
VDD
VDD
100
➤
DC Input
VOD/Δ VOD
out
LVDS
➤
LVDS
out
➤
DC Input
➤
out
out
➤
VOS/Δ VOS
➤
DIFFERENTIAL OUTPUT VOLTAGE SETUP
844003AGI-01
OFFSET VOLTAGE SETUP
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FEMTOCLOCKS™CRYSTAL-TO-LVDS
FREQUENCY SYNTHESIZER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS844003I-01 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VDD, VDDA, and VDDOx
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 2 illustrates how
a 10Ω resistor along with a 10μF and a .01μF bypass
capacitor should be connected to each VDDA pin.
3.3V
VDD
.01μF
10 Ω
VDDA
.01μF
10μF
FIGURE 2. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
were determined using a 19.53125MHz or 25MHz 18pF parallel
resonant crystal and were chosen to minimize the ppm error.
The ICS844003I-01 has been characterized with 18pF parallel
resonant crystals. The capacitor values shown in Figure 3 below
XTAL_OUT
C1
22p
X1
18pF Parallel Crystal
XTAL_IN
C2
22p
ICS844003I-01
Figure 3. CRYSTAL INPUt INTERFACE
844003AGI-01
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ICS844003I-01
FEMTOCLOCKS™CRYSTAL-TO-LVDS
FREQUENCY SYNTHESIZER
3.3V LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 4. In a 100Ω
differential transmission line environment, LVDS drivers
require a matched load termination of 100Ω across near
the receiver input. For a multiple LVDS outputs buffer, if only
partial outputs are used, it is recommended to terminate the
unused outputs.
3.3V
3.3V
LVDS
+
R1
100
-
100 Ohm Differential Transmission Line
FIGURE 4. TYPICAL LVDS DRIVER TERMINATION
RELIABILITY INFORMATION
TABLE 7.
θJAVS. AIR FLOW TABLE
FOR
24 LEAD TSSOP
θJA by Velocity (Meters per Second)
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
70°C/W
65°C/W
62°C/W
TRANSISTOR COUNT
The transistor count for ICS844003I-01 is: 3537
844003AGI-01
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PACKAGE OUTLINE - G SUFFIX
FOR
ICS844003I-01
FEMTOCLOCKS™CRYSTAL-TO-LVDS
FREQUENCY SYNTHESIZER
24 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
SYMBOL
Millimeters
Minimum
N
A
Maximum
24
--
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
7.70
7.90
E
E1
6.40 BASIC
4.30
e
4.50
0.65 BASIC
L
0.45
0.75
α
0°
8°
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
844003AGI-01
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ICS844003I-01
FEMTOCLOCKS™CRYSTAL-TO-LVDS
FREQUENCY SYNTHESIZER
TABLE 9. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
ICS844003AGI-01
ICS844003AI01
24 Lead TSSOP
tube
-40°C to 85°C
ICS844003AGI-01T
ICS844003AI01
24 Lead
2500 tape & reel
-40°C to 85°C
The aforementioned trademarks, HiPerClockS™ and FemtoClocks™ are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended
without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in
life support devices or critical medical instruments.
844003AGI-01
www.icst.com/products/hiperclocks.html
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REV. A MAY 31, 2005
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