ICST ICS844031AGI-01 Femtoclocksâ ¢ crystal-to- lvds clock generator Datasheet

PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844031I-01
FEMTOCLOCKS™ CRYSTAL-TO- LVDS
CLOCK GENERATOR
GENERAL DESCRIPTION
F EATURES
The ICS844031I-01 is an Ethernet Clock
Generator and a member of the HiPerClocksTM
HiPerClockS™ family of high performance devices from ICS. The
ICS844031I-01 uses an 18pF parallel resonant
crystal over the range of 19.6MHz - 27.2MHz. For
Ethernet applications, a 25MHz crystal is used to generate
312.5MHz. The ICS844031I-01 has excellent <1ps phase jitter
performance, over the 1.875MHz - 20MHz integration range.
The ICS844031I-01 is packaged in a small 8-pin TSSOP,
making it ideal for use in systems with limited board space.
• (1) Differential LVDS output
ICS
• Crystal oscillator interface, 18pF parallel resonant crystal
(19.6MHz - 27.2MHz)
• Output frequency range: 245MHz - 340MHz
• VCO range: 490MHz - 680MHz
• RMS phase jitter @ 312.5MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.49ps (typical)
• 3.3V or 2.5V operating supply
• -40°C to 85°C ambient operating temperature
COMMON CONFIGURATION TABLE
Inputs
Crystal Frequency (MHz)
M
N
25
25
2
Multiplication
Value M/N
12.5
Output Frequency
(MHz)
312.5
BLOCK DIAGRAM
PIN ASSIGNMENT
OE Pullup
XTAL_IN
OSC
XTAL_OUT
Phase
Detector
VCO
490MHz - 680MHz
N = ÷2 (fixed)
Q
nQ
VDDA
GND
XTAL_OUT
XTAL_IN
1
2
3
4
8
7
6
5
VDD
Q
nQ
OE
ICS844031I-01
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm
package body
G Package
Top View
M = ÷25 (fixed)
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
844031AGI-01
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REV. B JULY 6, 2005
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PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844031I-01
FEMTOCLOCKS™ CRYSTAL-TO- LVDS
CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
1
VDDA
Power
Type
Description
Analog supply pin.
2
GND
Power
3, 4
XTAL_OUT, XTAL_IN
Input
5
OE
Input
6, 7
nQ, Q
Output
Power supply ground.
Cr ystal oscillator interface. XTAL_IN is the input,
XTAL_OUT is the output.
Output enable pin. When HIGH, Q0/nQ0 output is active.
When LOW, the Q0/nQ0 output is in a high impedance state.
LVCMOS/LVTTL interface levels.
Differential clock outputs. LVDS interface levels.
8
VDD
Power
Core supply pin.
Pullup
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
CIN
Input Capacitance
4
pF
RPULLUP
Input Pullup Resistor
51
kΩ
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PRELIMINARY
Integrated
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ICS844031I-01
FEMTOCLOCKS™ CRYSTAL-TO- LVDS
CLOCK GENERATOR
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
NOTE: Stresses beyond those listed under Absolute
Inputs, VI
-0.5V to VDD + 0.5 V
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
Outputs, IO (LVDS)
Continuous Current
Surge Current
10mA
15mA
Package Thermal Impedance, θJA
101.7°C/W (0 mps)
Storage Temperature, TSTG
-65°C to 150°C
operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
VDD
Test Conditions
Minimum
Typical
Maximum
Units
Core Supply Voltage
3.135
3.3
3.465
V
3.135
3.3
3.465
VDDA
Analog Supply Voltage
IDD
Power Supply Current
TBD
mA
IDDA
Analog Supply Current
TBD
mA
V
TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 2.5V±5%, TA = -40°C TO 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VDD
Core Supply Voltage
2.375
2.5
2.625
V
VDDA
Analog Supply Voltage
2.375
2.5
2.625
V
IDD
Power Supply Current
TBD
mA
IDDA
Analog Supply Current
TBD
mA
TABLE 3C. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V±5% OR 2.5V±5%, TA = -40°C TO 85°C
Symbol
Parameter
Test Conditions
Minimum
Maximum
Units
VDD = 3.3V
2
VDD + 0.3
V
VDD = 2.5V
1.7
VDD + 0.3
V
VDD = 3.3V
-0.3
0.8
V
VDD = 2.5V
-0.3
0.7
V
5
µA
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
Input High Current
OE
VDD = VIN = 3.465V or 2.625V
IIL
Input Low Current
OE
VDD = 3.465V or 2.625V, VIN = 0V
Typical
-150
µA
TABLE 3D. LVDS DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
VOD
Differential Output Voltage
Δ VOD
VOD Magnitude Change
VOS
Offset Voltage
Δ VOS
VOS Magnitude Change
Test Conditions
Minimum
Typical
Maximum
Units
350
mV
40
mV
1.25
V
50
mV
NOTE: Please refer to Parameter Measurement Information for output information.
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PRELIMINARY
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ICS844031I-01
FEMTOCLOCKS™ CRYSTAL-TO- LVDS
CLOCK GENERATOR
TABLE 3E. LVDS DC CHARACTERISTICS, VDD = VDDA = 2.5V±5%, TA = -40°C TO 85°C
Symbol
Parameter
VOD
Differential Output Voltage
Test Conditions
Minimum
Typical
350
Maximum
Units
mV
Δ VOD
VOD Magnitude Change
50
mV
VOS
Offset Voltage
1.2
V
Δ VOS
VOS Magnitude Change
40
mV
NOTE: Please refer to Parameter Measurement Information for output information.
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Mode of Oscillation
Typical
Maximum
Units
Fundamental
27.2
MHz
Equivalent Series Resistance (ESR)
Frequency
19.6
50
Ω
Shunt Capacitance
7
pF
Drive Level
1
mW
Maximum
Units
340
MHz
TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
fOUT
Output Frequency
RMS Phase Jitter ( Random);
NOTE 1
Output Rise/Fall Time
tjit(Ø)
tR / tF
Test Conditions
Minimum
Typical
245
312.5MHz @ Integration Range:
1.875MHz - 20MHz
20% to 80%
odc
Output Duty Cycle
NOTE 1: Please refer to the Phase Noise Plots following this section.
0.49
ps
300
ps
50
%
TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = 2.5V±5%, TA = -40°C TO 85°C
Symbol
Parameter
fOUT
Output Frequency
RMS Phase Jitter ( Random);
NOTE 1
Output Rise/Fall Time
tjit(Ø)
tR / tF
Test Conditions
Typical
245
312.5MHz @ Integration Range:
1.875MHz - 20MHz
20% to 80%
odc
Output Duty Cycle
NOTE 1: Please refer to the Phase Noise Plots following this section.
844031AGI-01
Minimum
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4
Maximum
Units
340
MHz
0.70
ps
300
ps
50
%
REV. B JULY 6, 2005
PRELIMINARY
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ICS844031I-01
FEMTOCLOCKS™ CRYSTAL-TO- LVDS
CLOCK GENERATOR
TYPICAL PHASE NOISE AT 312.5MHZ
➤
0
-10
-20
Ethernet Filter
-40
312.5MHz
-50
-60
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.49ps (typical)
-70
-80
Raw Phase Noise Data
-90
-100
➤
NOISE POWER dBc
Hz
-30
-110
-120
-130
-140
-150
➤
-160
-170
-180
-190
100
1k
Phase Noise Result by adding
an Ethernet Filter to raw data
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
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ICS844031I-01
FEMTOCLOCKS™ CRYSTAL-TO- LVDS
CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
SCOPE
Qx
3.3V±5%
POWER SUPPLY
Qx
2.5V±5%
POWER SUPPLY
LVDS
+ Float GND -
+ Float GND -
SCOPE
LVDS
nQx
nQx
LVDS 3.3V OUTPUT LOAD AC TEST CIRCUIT
LVDS 2.5V OUTPUT LOAD AC TEST CIRCUIT
Phase Noise Plot
Noise Power
nQ
Q
t PW
t
Phase Noise Mask
odc =
f1
Offset Frequency
PERIOD
t PW
x 100%
t PERIOD
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
VVDD
DD
out
80%
DC Input
VSW I N G
Clock
Outputs
LVDS
➤
80%
20%
20%
tR
out
tF
➤
VOS/Δ VOS
➤
OFFSET VOLTAGE SETUP
OUTPUT RISE/FALL TIME
VDD
V
DD
LVDS
100
➤
VOD/Δ VOD
out
➤
DC Input
➤
out
DIFFERENTIAL OUTPUT VOLTAGE SETUP
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PRELIMINARY
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ICS844031I-01
FEMTOCLOCKS™ CRYSTAL-TO- LVDS
CLOCK GENERATOR
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS844031I-01 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VDD and VDDA should
be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10μF and a .01μF bypass
capacitor should be connected to each VDDA pin.
3.3V or 2.5V
VDD
.01μF
10 Ω
VDDA
.01μF
10μF
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS844031I-01 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 2 below were determined using a 25MHz, 18pF parallel
resonant crystal and were chosen to minimize the ppm error.
The optimum C1 and C2 values can be slightly adjusted for different board layouts.
XTAL_OUT
C1
33p
X1
18pF Parallel Crystal
XTAL_IN
C2
27p
Figure 2. CRYSTAL INPUt INTERFACE
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ICS844031I-01
FEMTOCLOCKS™ CRYSTAL-TO- LVDS
CLOCK GENERATOR
3.3V, 2.5V LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 3. In a 100Ω
differential transmission line environment, LVDS drivers
require a matched load termination of 100Ω across near
the receiver input. For a multiple LVDS outputs buffer, if only
partial outputs are used, it is recommended to terminate the
un-used outputs.
2.5V or 3.3V
VDD
LVDS_Driv er
+
R1
100
-
100 Ohm Differential Transmission Line
FIGURE 3. TYPICAL LVDS DRIVER TERMINATION
844031AGI-01
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REV. B JULY 6, 2005
PRELIMINARY
Integrated
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Systems, Inc.
ICS844031I-01
FEMTOCLOCKS™ CRYSTAL-TO- LVDS
CLOCK GENERATOR
APPLICATION SCHEMATIC
Figure 4A provides a schematic example of ICS844031I. In this
example, an 18 pF parallel resonant crystal is used. The
C1=22pF and C2=22pF are recommended for frequency. The
C1 and C2 values may be slightly adjusted for optimizing fre-
VDD
quency accuracy. At least one decoupling capacitor near the
power pin is required. Suggested value range is from 0.01uF to
0.1uF. Other filter type can be added depending on the system
power supply noise type.
VDDA
VDD
R2
10
C3
10uF
C4
0.01u
R1
1K
U1
Zo = 50 Ohm
1
2
3
4
C2
22pF
VCCA
GND
XTAL_OUT
XTAL_IN
VDD
Q0
nQ0
OE
VDD
8
7
6
5
+
R3
100
Zo = 50 Ohm
X1
CL=18pF
ICS844031
C5
0.1u
LVDS
C1
22pF
VDD= 3.3V or 2.5V
FIGURE 4A. APPLICATION SCHEMATIC EXAMPLE
PC BOARD LAYOUT EXAMPLE
Figure 4B shows an example of ICS844031I P.C. board layout.
The crystal X1 footprint shown in this example allows installation of either surface mount HC49S or through-hole HC49 package. The footprints of other components in this example are listed
in the Table 6. There should be at least one decoupling capacitor
per power pin. The decoupling capacitors should be located as
close as possible to the power pins. The layout assumes that
the board has clean analog power ground plane.
TABLE 6. FOOTPRINT TABLE
Reference
Size
C1, C2
0402
C3
0805
C4, C5
0603
R2
0603
NOTE: Table 6, lists component
sizes shown in this layout example.
FIGURE 4B. ICS843001 PC BOARD LAYOUT EXAMPLE
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ICS844031I-01
FEMTOCLOCKS™ CRYSTAL-TO- LVDS
CLOCK GENERATOR
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE
FOR
8 LEAD TSSOP
θJA by Velocity (Meters per Second)
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
101.7°C/W
90.5°C/W
89.8°C/W
TRANSISTOR COUNT
The transistor count for ICS844031I-01 is: 2519
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PACKAGE OUTLINE - G SUFFIX
FOR
ICS844031I-01
FEMTOCLOCKS™ CRYSTAL-TO- LVDS
CLOCK GENERATOR
8 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
SYMBOL
Millimeters
Minimum
N
Maximum
8
A
--
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
2.90
E
E1
3.10
6.40 BASIC
4.30
e
4.50
0.65 BASIC
L
0.45
0.75
α
0°
8°
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
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Systems, Inc.
ICS844031I-01
FEMTOCLOCKS™ CRYSTAL-TO- LVDS
CLOCK GENERATOR
TABLE 9. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
ICS844031AGI-01
TBD
8 lead TSSOP
tube
-40°C to 85°C
ICS844031AGI-01T
TBD
8 lead TSSOP
2500 tape & reel
-40°C to 85°C
The aforementioned trademarks, HiPerClockS™ and FemtoClocks™ are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
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REV. B JULY 6, 2005
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