ICS ICS844071AGIT

PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844071I
FEMTOCLOCKS™ CRYSTAL-TO- LVDS
CLOCK GENERATOR
GENERAL DESCRIPTION
FEATURES
The ICS844071I is a Serial ATA (SATA)/Serial
Attached SCSI (SAS) Clock Generator and a
HiPerClockS™ member of the HiPerClocks TM family of high
performance devices from ICS. The ICS844071I
uses an 18pF parallel resonant crystal over the
range of 20.833MHz - 28.3MHz. For SATA/SAS applications,
a 25MHz crystal is used and either 75MHz or 150MHz may
be selected with the FREQ_SEL pin. The ICS844071I has
excellent <1ps phase jitter performance, over the 12kHz 20MHz integration range. The ICS844071I is packaged in a
small 8-pin TSSOP, making it ideal for use in systems with
limited board space.
• (1) Differential LVDS output
ICS
• Crystal oscillator interface, 18pF parallel resonant crystal
(20.833MHz - 28.3MHz)
• Output frequency range: 62.5MHz - 170MHz
• VCO range: 500MHz - 680MHz
• RMS phase jitter @ 150MHz, using a 25MHz crystal
(12kHz - 20MHz): 0.75ps (typical)
• 3.3V or 2.5V operating supply
• -40°C to 85°C ambient operating temperature
• Replaces ICS844051-11
COMMON CONFIGURATION TABLE
Inputs
Output Frequency
(MHz)
Crystal Frequency (MHz)
FREQ_SEL
M
N
Multiplication Value
M/N
25
0
24
4
6
150
25
1
24
8
3
75
26.041666
0
24
4
6
156.25
26.041666
1
24
8
3
78.125
26.5625
0
24
4
6
159.375
26.5625
1
24
8
3
79.675
BLOCK DIAGRAM
PIN ASSIGNMENT
FREQ_SEL Pullup
XTAL_IN
OSC
XTAL_OUT
Phase
Detector
VCO
500MHz - 680MHz
FREQ_SEL N
0
÷4
1
÷8
Q
nQ
VDDA
GND
XTAL_OUT
XTAL_IN
1
2
3
4
8
7
6
5
VDD
Q
nQ
FREQ_SEL
ICS844071I
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm
package body
G Package
Top View
M = ÷24 (fixed)
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
844071AGI
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REV. A JULY 13, 2005
1
PRELIMINARY
ICS844071I
FEMTOCLOCKS™ CRYSTAL-TO- LVDS
CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
Number
Name
1
VDDA
Power
Analog supply pin.
2
Power
5
GND
XTAL_OUT,
XTAL_IN
FREQ_SEL
Power supply ground.
Crystal oscillator interface. XTAL_IN is the input,
XTAL_OUT is the output.
Frequency select pin. LVCMOS/LVTTL interface levels.
6, 7
nQ, Q
Output
Differential clock outputs. HSTL interface levels.
8
VDD
Power
Core supply pin.
3, 4
Type
Description
Input
Input
Pullup
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
Input Capacitance
4
pF
RPULLUP
Input Pullup Resistor
51
kΩ
844071AGI
Test Conditions
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2
Minimum
Typical
Maximum
Units
REV. A JULY 13, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844071I
FEMTOCLOCKS™ CRYSTAL-TO- LVDS
CLOCK GENERATOR
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5 V
Outputs, IO (LVDS)
Continuous Current
Surge Current
10mA
15mA
Package Thermal Impedance, θJA
101.7°C/W (0 mps)
Storage Temperature, TSTG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
Minimum
Typical
Maximum
Units
VDD
Core Supply Voltage
Test Conditions
3.135
3.3
3.465
V
VDDA
Analog Supply Voltage
3.135
3.3
3.465
V
IDD
Power Supply Current
TBD
mA
IDDA
Analog Supply Current
TBD
mA
TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 2.5V±5%, TA = -40°C TO 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VDD
Core Supply Voltage
2.375
2.5
2.625
V
VDDA
Analog Supply Voltage
2.375
2.5
2.625
V
IDD
Power Supply Current
TBD
mA
IDDA
Analog Supply Current
TBD
mA
TABLE 3C. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V±5% OR 2.5V±5%, TA = -40°C TO 85°C
Symbol
Parameter
Test Conditions
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
Input High Current
FREQ_SEL
VDD = VIN = 3.465V or 2.625V
IIL
Input Low Current
FREQ_SEL
VDD = 3.465V or 2.625V, VIN = 0V
Minimum
Typical
Maximum
Units
VDD = 3.3V
2
VDD + 0.3
V
VDD = 2.5V
1.7
VDD + 0.3
V
VDD = 3.3V
-0.3
0.8
V
VDD = 2.5V
-0.3
0.7
V
5
µA
-150
µA
NOTE 1: Outputs terminated with 50Ω to VDD/2. See Parameter Measurement Information Section,
"3.3V Output Load Test Circuit".
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REV. A JULY 13, 2005
PRELIMINARY
ICS844071I
FEMTOCLOCKS™ CRYSTAL-TO- LVDS
CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
TABLE 3D. LVDS DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
VOD
Differential Output Voltage
Δ VOD
VOD Magnitude Change
VOS
Offset Voltage
Δ VOS
VOS Magnitude Change
Test Conditions
Minimum
Typical
Maximum
Units
350
mV
40
mV
1.25
V
50
mV
TABLE 3E. LVDS DC CHARACTERISTICS, VDD = VDDA = 2.5V±5%, TA = -40°C TO 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VOD
Differential Output Voltage
350
mV
Δ VOD
VOD Magnitude Change
50
mV
VOS
Offset Voltage
1.2
V
Δ VOS
VOS Magnitude Change
40
mV
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Mode of Oscillation
Typical
Maximum
Units
28.3
MHz
Fundamental
Frequency
20.833
Equivalent Series Resistance (ESR)
50
Ω
Shunt Capacitance
7
pF
Drive Level
1
mW
Maximum
Units
170
MHz
TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
fOUT
Output Frequency
tjit(Ø)
RMS Phase Jitter ( Random);
NOTE 1
tR / tF
Output Rise/Fall Time
Test Conditions
Minimum
Typical
62.5
150MHz @ Integration Range:
12kHz - 20MHz
75MHz @ Integration Range:
12kHz - 20MHzz
20% to 80%
odc
Output Duty Cycle
NOTE 1: Please refer to the Phase Noise Plots following this section.
0.75
ps
0.68
ps
300
ps
50
%
TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = 2.5V±5%, TA = -40°C TO 85°C
Symbol
Parameter
fOUT
Output Frequency
tjit(Ø)
RMS Phase Jitter ( Random);
NOTE 1
tR / tF
Output Rise/Fall Time
Test Conditions
Typical
62.5
150MHz @ Integration Range:
12kHz - 20MHz
75MHz @ Integration Range:
12kHz - 20MHzz
20% to 80%
odc
Output Duty Cycle
NOTE 1: Please refer to the Phase Noise Plots following this section.
844071AGI
Minimum
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4
Maximum
Units
170
MHz
0.96
ps
0.98
ps
300
ps
50
%
REV. A JULY 13, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844071I
FEMTOCLOCKS™ CRYSTAL-TO- LVDS
CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
SCOPE
Qx
3.3V±5%
POWER SUPPLY
Qx
2.5V±5%
POWER SUPPLY
LVDS
+ Float GND -
+ Float GND -
SCOPE
LVDS
nQx
nQx
LVDS 3.3V OUTPUT LOAD AC TEST CIRCUIT
LVDS 2.5V OUTPUT LOAD AC TEST CIRCUIT
nQ
80%
80%
Q
VSW I N G
Clock
Outputs
t PW
20%
20%
t
tF
tR
odc =
PERIOD
t PW
x 100%
t PERIOD
OUTPUT RISE/FALL TIME
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
Phase Noise Plot
Noise Power
VDD
DD
out
LVDS
➤
DC Input
Phase Noise Mask
out
Offset Frequency
f2
➤
f1
➤
VOS/Δ VOS
RMS Jitter = Area Under the Masked Phase Noise Plot
OFFSET VOLTAGE SETUP
RMS PHASE JITTER
VDD
V
DD
LVDS
100
➤
VOD/Δ VOD
out
➤
DC Input
➤
out
DIFFERENTIAL OUTPUT VOLTAGE SETUP
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REV. A JULY 13, 2005
PRELIMINARY
ICS844071I
FEMTOCLOCKS™ CRYSTAL-TO- LVDS
CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS844071I provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VDD and VDDA should
be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10μF and a .01μF bypass
capacitor should be connected to each VDDA pin.
RECOMMENDATIONS FOR UNUSED INPUT
INPUTS:
AND
3.3V or 2.5V
VDD
.01μF
10 Ω
VDDA
.01μF
10μF
FIGURE 1. POWER SUPPLY FILTERING
OUTPUT PINS
OUTPUTS:
CRYSTAL INPUT:
For applications not requiring the use of the crystal oscillator
input, both XTAL_IN and XTAL_OUT can be left floating. Though
not required, but for additional protection, a 1kΩ resister can be
tied from XTAL_IN to ground.
LVCMOS OUTPUT:
All unused LVCMOS output can be left floating. We recommend
that there is no trace attached.
LVPECL OUTPUT
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential
output pair should either be left floating or terminated.
CLK INPUT:
For applications not requiring the use of the test clock, it can be
left floating. Though not required, but for additional protection, a
1kΩ resister can be tied from the CLK input to ground.
LVHSTL OUTPUT
All unused LVHSTL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential
output pair should either be left floating or terminated.
TEST_CLK INPUT:
For applications not requiring the use of the test clock, it can be
left floating. Though not required, but for additional protection, a
1kΩ resister can be tied from the TEST_CLK to ground.
LVDS OUTPUT
All unused LVDS outputs should be terminated with 100Ω resister
between the differential pair.
CLK/nCLK INPUT:
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required,
but for additional protection, a 1kΩ resister can be tied from CLK
to ground.
LVDS – Like OUTPUT
All unused LVDS outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential
output pair should either be left floating or terminated.
PCLK/nPCLK INPUT:
For applications not requiring the use of a differential input, both
the PCLK and nPCLK pins can be left floating. Though not
required, but for additional protection, a 1kΩ resister can be tied
from PCLK to ground.
HCSL OUTPUT
All unused HCSL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential
output pair should either be left floating or terminated.
SELECT PINS:
All select pins have internal pull-ups and pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resister can be used.
SSTL OUTPUT
All unused SSTL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential
output pair should either be left floating or terminated.
844071AGI
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REV. A JULY 13, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844071I
FEMTOCLOCKS™ CRYSTAL-TO- LVDS
CLOCK GENERATOR
CRYSTAL INPUT INTERFACE
The ICS844071I has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 2 below were determined using a 25MHz, 18pF parallel
resonant crystal and were chosen to minimize the ppm error.
The optimum C1 and C2 values can be slightly adjusted for different board layouts.
XTAL_OUT
C1
22p
X1
18pF Parallel Crystal
XTAL_IN
C2
33p
Figure 2. CRYSTAL INPUt INTERFACE
3.3V, 2.5V LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 3. In a 100Ω
differential transmission line environment, LVDS drivers
require a matched load termination of 100Ω across near
the receiver input. For a multiple LVDS outputs buffer, if only
partial outputs are used, it is recommended to terminate the
un-used outputs.
2.5V or 3.3V
VDD
LVDS_Driv er
+
R1
100
-
100 Ohm Differential Transmission Line
FIGURE 3. TYPICAL LVDS DRIVER TERMINATION
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REV. A JULY 13, 2005
PRELIMINARY
ICS844071I
FEMTOCLOCKS™ CRYSTAL-TO- LVDS
CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE
FOR
8 LEAD TSSOP
θJA by Velocity (Meters per Second)
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
101.7°C/W
90.5°C/W
89.8°C/W
TRANSISTOR COUNT
The transistor count for ICS844071I is: 2533
844071AGI
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REV. A JULY 13, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - G SUFFIX
FOR
ICS844071I
FEMTOCLOCKS™ CRYSTAL-TO- LVDS
CLOCK GENERATOR
8 LEAD TSSOP
TABLE 7. PACKAGE DIMENSIONS
SYMBOL
Millimeters
Minimum
N
Maximum
8
A
--
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
2.90
E
E1
3.10
6.40 BASIC
4.30
e
4.50
0.65 BASIC
L
0.45
0.75
α
0°
8°
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
844071AGI
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REV. A JULY 13, 2005
PRELIMINARY
ICS844071I
FEMTOCLOCKS™ CRYSTAL-TO- LVDS
CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
TABLE 8. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
ICS844071AGI
4071A
8 Lead TSSOP
tube
-40°C to 85°C
ICS844071AGIT
4071A
8 Lead TSSOP
2500 tape & reel
-40°C to 85°C
The aforementioned trademarks, HiPerClockS and FemtoClocks are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
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10
REV. A JULY 13, 2005