ICST ICS950818 Frequency generator with 200mhz differential cpu clock Datasheet

ICS950818
Integrated
Circuit
Systems, Inc.
Frequency Generator with 200MHz Differential CPU Clocks
Output Features:
•
2 - Differential CPU Clock Pairs @ 3.3V
•
8 - PCI (3.3V) @ 33.3MHz including 2 1x/2x
selectable PCI clocks
•
3 - PCI_F/PCI selectable (3.3V) @ 33.3MHz
•
1 - USB (3.3V) @ 48MHz, 1 DOT (3.3V) @ 48MHz
•
1 - REF (3.3V) @ 14.318MHz
•
4 - 3V66 (3.3V) @ 66.6MHz
•
1 - VCH/3V66 (3.3V) @ 48MHz or 66.6MHz
Features:
•
Selectable 1X or 2X strength for REF and PCI via
SMBus interface
•
Programmable group to group skew
•
Linear programmable frequency and spreading %
•
Efficient power management scheme through PD#,
CPU_STOP# and PCI_STOP#.
•
Uses external 14.318MHz crystal
•
Stop clocks and functional control available through
SMBus interface.
Key Specifications:
•
CPU Output Jitter <150ps
•
3V66 Output Jitter <250ps
•
CPU Output Skew <100ps
Pin Configuration
X1
X2
GND
PCICLK_F0/PCICLK6
PCICLK_F1/PCICLK7
PCICLK_F2/PCICLK8
GND
PCICLK0
PCICLK1
*PCICLK2
VDDPCI
*PCICLK3
PCICLK4
PCICLK5
VDD3V66
GND
3V66_2
3V66_3
3V66_4
PCICLK9
PD#
VDDA
GND
Vtt_PWRGD#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
ICS950818
Recommended Application:
CK-408 clock for Brookdale/Odem/Montara-GM for P4/Banias
processor.
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDREF
REF
FS1
CPU_STOP#
VDDCPU
CPUCLKT0
CPUCLKC0
GND
VDDCPU
CPUCLKT1
CPUCLKC1
IREF
FS0
48MHz_USB
48MHz_DOT
VDD48
GND
3V66_1/VCH_CLK
PCI_STOP#
PCICLK10
VDD3V66
GND
SCLK
SDATA
48-Pin 6.10 mm. Body, 0.50 mm. pitch TSSOP
*These outputs have selectable 1X/2X strength via SMBus
Block Diagram
Frequency Select Table 1
48MHz_USB
PLL2
48MHz_DOT
X1
X2
XTAL
OSC
3V66 (4:2)
PLL1
Spread
Spectrum
REF
CPU
DIVDER
Stop
3
3
Vtt_PWRGD#
PD#
CPU_STOP#
PCI_STOP#
FS (1:0)
SDATA
SCLK
0825F—11/19/03
Control
Logic
Config.
Reg.
PCI
DIVDER
Stop
CPUCLKT (1:0)
CPUCLKC (1:0)
PCICLK (10:0)
7
PCICLK_F (2:0)
3V66
DIVDER
3
3V66_1/VCH_CLK
I REF
Freq
Sel
FS FS
1
0
0
0
1
1
0
1
0
1
CPU MHz
3V66(4:1)
MHz
PCI MHz
REF MHz
USB/DOT
MHz
100.00
166.67
133.33
200.00
66.66
66.66
66.66
66.66
33.33
33.33
33.33
33.33
14.318
14.318
14.318
14.318
48.008
48.008
48.008
48.008
ICS950818
Pin Description
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PIN NAME
X1
X2
GND
PCICLK_F0/PCICLK6
PCICLK_F1/PCICLK7
PCICLK_F2/PCICLK8
GND
PCICLK0
PCICLK1
*PCICLK2
VDDPCI
*PCICLK3
PCICLK4
PCICLK5
VDD3V66
GND
3V66_2
3V66_3
3V66_4
PCICLK9
21
PD#
22
23
VDDA
GND
24
Vtt_PWRGD#
PIN TYPE
IN
OUT
PWR
OUT
OUT
OUT
PWR
OUT
OUT
OUT
PWR
I/O
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
IN
PWR
PWR
IN
DESCRIPTION
Crystal input, Nominally 14.318MHz.
Crystal output, Nominally 14.318MHz
Ground pin.
Free running/Non-Free running PCI clock selected by SMBus.
Free running/Non-Free running PCI clock selected by SMBus.
Free running/Non-Free running PCI clock selected by SMBus.
Ground pin.
PCI clock output.
PCI clock output.
PCI clock output.
Power supply for PCI clocks, nominal 3.3V
PCI clock output.
PCI clock output.
PCI clock output.
Power pin for the 3V66 clocks.
Ground pin.
3.3V 66.66MHz clock output
3.3V 66.66MHz clock output
3.3V 66.66MHz clock output
PCI clock output.
Asynchronous active low input pin used to power down the device into a low
power state. The internal clocks are disabled and the VCO and the crystal
are stopped.
3.3V power for the PLL core.
Ground pin.
This 3.3V LVTTL input is a level sensitive strobe used to determine when
latch inputs are valid and are ready to be sampled. This is an active low
input.
0825F—11/19/03
2
ICS950818
Pin Description (Continued)
PIN #
25
26
27
28
29
PIN NAME
SDATA
SCLK
GND
VDD3V66
PCICLK10
PIN TYPE
I/O
IN
PWR
PWR
OUT
30
PCI_STOP#
31
32
33
34
35
36
3V66_1/VCH_CLK
GND
VDD48
48MHz_DOT
48MHz_USB
FS0
OUT
PWR
PWR
OUT
OUT
IN
37
IREF
OUT
38
CPUCLKC1
OUT
39
CPUCLKT1
OUT
40
41
VDDCPU
GND
PWR
PWR
42
CPUCLKC0
OUT
43
CPUCLKT0
OUT
44
45
46
47
48
VDDCPU
CPU_STOP#
FS1
REF
VDDREF
PWR
IN
IN
OUT
PWR
IN
DESCRIPTION
Data pin for I2C circuitry 5V tolerant
Clock pin of I2C circuitry 5V tolerant
Ground pin.
Power pin for the 3V66 clocks.
PCI clock output.
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input
low
3.3V 66.66MHz clock output / 48MHz VCH clock output.
Ground pin.
Power pin for the 48MHz output.3.3V
48MHz clock output.
48MHz clock output.
Frequency select pin.
This pin establishes the reference current for the differential current-mode
output pairs. This pin requires a fixed precision resistor tied to ground in
order to establish the appropriate current. 475 ohms is the standard value.
Complimentary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
Ground pin.
Complimentary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
Stops all CPUCLK besides the free running clocks
Frequency select pin.
14.318 MHz reference clock.
Ref, XTAL power supply, nominal 3.3V
Power Supply
Pin Number
VDD
48
GND
3
Description
Xtal, Ref
11
7
15, 28
16, 27
3V66
22
23
Master clock, CPU Analog
33
32
48MHz, Fix Digital, Fix Analog
41
Inputs
41
CPUCLK clocks
40, 44
PCICLK outputs
0825F—11/19/03
3
ICS950818
Default Setup of Byte 11-17
CPU (MHz)
100.00
100.00
100.00
100.00
100.00
100.00
SS%
0
0 to -0.5%
0 to -1%
+/- 0.25%
+/- 0.50%
+/- 1.0%
11
8E
8D
90
8E
8E
8E
12
B7
9A
ED
B7
B7
B7
13
F8
F2
EE
0A
06
15
Bytes
14
17
17
17
18
18
18
15
94
94
94
94
94
94
16
95
95
95
95
95
95
17
0F
0F
0F
0F
0F
0F
CPU (MHz)
166.66
166.66
166.66
166.66
166.66
166.66
SS%
0
0 to -0.5%
0 to -1%
+/- 0.25%
+/- 0.50%
+/- 1.0%
11
87
87
86
87
87
87
12
9B
9A
6B
9B
9B
9B
13
F8
EE
E5
15
10
28
Bytes
14
27
27
27
28
28
28
15
A4
A4
A4
A4
A4
A4
16
A6
A6
A6
A6
A6
A6
17
0F
0F
0F
0F
0F
0F
CPU (MHz)
133.33
133.33
133.33
133.33
133.33
133.33
SS%
0
0 to -0.5%
0 to -1%
+/- 0.25%
+/- 0.50%
+/- 1.0%
11
86
8B
87
86
86
86
12
22
DB
46
22
22
22
13
F9
F0
EB
10
0C
1F
Bytes
14
1F
1F
1F
20
20
20
15
C4
C4
C4
C4
C4
C4
16
C8
C8
C8
C8
C8
C8
17
0F
0F
0F
0F
0F
0F
CPU (MHz)
200.00
200.00
200.00
200.00
200.00
200.00
SS%
0
0 to -0.5%
0 to -1%
+/- 0.25%
+/- 0.50%
+/- 1.0%
11
86
86
84
86
86
86
12
B7
B6
46
B7
B7
B7
13
FB
F0
E4
1D
17
34
Bytes
14
2F
2F
2F
30
30
30
15
D4
D4
D4
D4
D4
D4
16
D9
D9
D9
D9
D9
D9
17
0F
0F
0F
0F
0F
0F
0825F—11/19/03
4
ICS950818
Affected Pin
Name
Spread Enabled
BYTE
0
Bit 7
Pin #
-
Bit 6
-
CPUCLKT(1:0)
Bit 5
Bit 4
31
44
3V66_1/VCH_CLK
CPU_STOP#
Bit 3
30
PCI_STOP#
Bit 2
Bit 1
46
FS1
Bit 0
36
FS0
Note: For PCI_STOP# function, refer to table 2.
BYTE
1
Bit 7
Pin #
-
Affected Pin
Name
-
Control Function
Type
Spread Spectrum Control
Power down mode output level
0= CPU driven in power down
1= undriven
VCH/66.66 Select
Reflects value of pin
Reflects value of pin at power up.
Also can be set.
(Reserved)
Frequency Selection
Frequency Selection
RW
Control Function
(Reserved)
CPU_Stop mode output level
Bit 6
CPUCLKT(1:0)
0= CPU driven when stopped
1 = undriven
CPUCLKT1, CPUCLKC1
Allow control of output with
Bit 5
39, 38
(see note)
assertion of CPU_STOP#.
CPUCLKT0, CPUCLKC0
Allow control of output with
Bit 4
43, 42
(see note)
assertion of CPU_STOP#.
Bit 3
(Reserved)
Bit 2
39, 38
CPUCLKT1, CPUCLKC1
Output control
Bit 1
43, 42
CPUCLKT0, CPUCLKC0
Output control
Bit 0
(Reserved)
Note: CPUCLK(1:0) can be turned on/off by CPU_STOP#. Refer to table 3.
Affected Pin
BYTE
Control Function
2
Pin #
Name
Bit 7
47
REF
1X or 0.5X Strength control
Bit 6
14
PCICLK5
Output control
Bit 5
13
PCICLK4
Output control
Bit 4
12
*PCICLK3
Output control
Bit 3
Reserved
Bit 2
10
*PCICLK2
Output control
Bit 1
9
PCICLK1
Output control
Bit 0
8
PCICLK0
Output control
Note: PCICLK(5:0) can be turned on/off by PCI_STOP#. Refer to table 2.
0825F—11/19/03
5
Bit Control
0
1
OFF
ON
PWD
0
RW
x2 IREF
Hi-Z
0
RW
R
66.66
Stop
48.00
Active
0
X
RW
Stop
Active
X
R
R
R
-
-
X
X
X
Type
R
RW
RW
RW
R
RW
RW
R
Type
RW
RW
RW
RW
X
RW
RW
RW
Bit Control
0
1
x2 IREF
Not
Freerun
Not
Freerun
Disable
Disable
-
PWD
X
Hi-Z
0
Freerun
0
Freerun
0
Enable
Enable
-
X
1
1
X
Bit Control
0
1
1X
0.5X
Disable Enable
Disable Enable
Disable Enable
Disable Enable
Disable Enable
Disable Enable
PWD
0
1
1
1
1
1
1
1
ICS950818
BYTE
3
Affected Pin
Control Function
Name
Bit 7
48MHz_DOT
Output control
Bit 6
48MHz_USB
Output control
PCICLK_F2/PCICLK8 (see
Allow control of output with
Bit 5
6
note)
assertion of PCI_STOP#.
PCICLK_F1/PCICLK7 (see
Allow control of output with
Bit 4
5
note)
assertion of PCI_STOP#.
PCICLK_F0/PCICLK6 (see
Allow control of output with
Bit 3
4
note)
assertion of PCI_STOP#.
Bit 2
6
PCICLK_F2/PCICLK8
Output control
Bit 1
5
PCICLK_F1/PCICLK7
Output control
Bit 0
4
PCICLK_F0/PCICLK6
Output control
Note: PCICLK_F(2:0) can be turned on/off by PCI_STOP#. Refer to table 4.
Pin #
34
35
BYTE
4
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
10
12
29
31
20
19
18
17
Affected Pin
Name
*PCICLK2
*PCICLK3
PCICLK10
3V66_1/VCH_CLK
PCICLK9
3V66_4
3V66_3
3V66_2
BYTE
5
Pin #
Affected Pin
Name
Bit 7
X
PD Mode Iref Mirror Enable
Bit 6
X
Reserved
Bit 5
X
3V66(4:2) (See table 6)
Bit 4
X
3V66(1) (See table 7)
34
48MHz_DOT Slew Control
35
48MHz_USB Slew Control
Bit 3
Bit 2
Bit 1
Bit 0
Type
RW
RW
RW
Freerun
RW
Freerun
RW
Freerun
RW
RW
RW
Disable
Disable
Disable
Control Function
Type
Output strength (1X/2X)
Output strength (1X/2X)
Output control
Output control
Output control
Output control
Output control
Output control
R/W
R/W
RW
RW
RW
RW
RW
RW
Control Function
Type
Allow Iref Mirror to be ON during
Power Down Mode
Reserved
Allow control of output with
assertion of CPU_STOP#.
Allow control of output with
assertion of CPU_STOP#.
00 = Medium (default), 01 = Low,
11,10 =High
00 = Medium (default), 01 = Low,
11,10 =High
Note: Functions in Byte 5 of CK408 were intended as a test and debug byte only.
0825F—11/19/03
6
Bit Control
0
Disable
Disable
1
Enable
Enable
Not
Freerun
Not
Freerun
Not
Freerun
Enable
Enable
Enable
PWD
1
1
0
0
0
1
1
1
Bit Control
0
1
2X
1X
2X
1X
Disable Enable
Disable Enable
Disable Enable
Disable Enable
Disable Enable
Disable Enable
PWD
1
1
1
1
1
1
1
1
Bit Control
0
1
PWD
RW
OFF
ON
0
X
-
0
X
Freerun
X
Freerun
RW
RW
RW
-
Not
Freerun
Not
Freerun
-
0
0
0
RW
-
-
0
0
0
ICS950818
BYTE
6
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
X
X
X
X
X
X
X
X
Affected Pin
Name
Revision ID Bit 3
Revision ID Bit 2
Revision ID Bit 1
Revision ID Bit 0
Vendor ID Bit 3
Vendor ID Bit 2
Vendor ID Bit 1
Vendor ID Bit 0
BYTE
7
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
X
X
X
X
X
X
X
X
Affected Pin
Name
-
BYTE
8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Pin #
X
X
X
X
X
X
Affected Pin
Name
-
Bit 1
X
-
Control Function
Type
Bit Control
0
1
-
PWD
0
0
0
0
0
0
0
1
Bit Control
0
1
-
PWD
0
0
0
0
1
1
1
0
PWD
0
0
0
0
1
1
(Reserved)
(Reserved)
(Reserved)
(Reserved)
R
R
R
R
R
R
R
R
Control Function
Type
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
X
X
X
X
X
X
X
X
Control Function
Type
(Reserved)
(Reserved)
(Reserved)
(Reserved)
X
X
X
X
R
R
Bit Control
0
1
-
R
-
Revision ID Value Based on
Device Revision
Readback Byte Count
-
1
Bit 0
X
R
1
Note: Byte 8 is for ICS test only. Do not write as system damage may occur. Bit(3:0) contain the readback Byte count.
BYTE
9
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
X
X
X
X
X
X
X
X
Affected Pin
Name
-
Control Function
Type
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
X
X
X
X
X
X
X
X
0825F—11/19/03
7
Bit Control
0
1
-
PWD
0
0
0
0
0
0
0
0
ICS950818
BYTE
10
Pin #
Affected Pin
Name
Bit 7
X
-
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
X
-
Control Function
M/N Enable (Enable access to
Byte 11 - 14)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Type
RW
X
X
X
X
X
X
X
Bit Control
0
1
Byte
HW/B0
(11-14)
-
BYTE
Affected Pin
Bit Control
Control Function
Type
11
Pin #
Name
0
1
Bit 7
X
VCO Divider Bit8
RW
Bit 6
X
REF Divider Bit6
RW
Bit 5
X
REF Divider Bit5
RW
Bit 4
X
REF Divider Bit4
RW
Bit 3
X
REF Divider Bit3
RW
Bit 2
X
REF Divider Bit2
RW
Bit 1
X
REF Divider Bit1
RW
Bit 0
X
REF Divider Bit0
RW
Note: The decimal representation of these 7 bits (Byte 11 bit[6:0]) + 2 is equal to the REF divider value.
BYTE
12
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
X
X
X
X
X
X
X
X
Affected Pin
Name
-
Control Function
VCO
VCO
VCO
VCO
VCO
VCO
VCO
VCO
Divider Bit7
Divider Bit6
Divider Bit5
Divider Bit4
Divider Bit3
Divider Bit2
Divider Bit1
Divider Bit0
Type
RW
RW
RW
RW
RW
RW
RW
RW
Bit Control
0
1
-
PWD
0
0
1
1
1
1
1
0
PWD
X
X
X
X
X
X
X
X
PWD
X
X
X
X
X
X
X
X
Note: The decimal representation of these 9 bits (Byte 12 bit[7:0]) and Byte 11 bit [7]) + 8 is equal to the VCO divider value.
BYTE
13
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
X
X
X
X
X
X
X
X
Affected Pin
Name
-
Control Function
Type
Spread Spectrum Bit7
Spread Spectrum Bit6
Spread Spectrum Bit5
Spread Spectrum Bit4
Spread Spectrum Bit3
Spread Spectrum Bit2
Spread Spectrum Bit1
Spread Spectrum Bit0
RW
RW
RW
RW
RW
RW
RW
RW
Bit Control
0
1
-
PWD
X
X
X
X
X
X
X
X
Note: Please utilize software utility provided by ICS Application Engineering to configure spread spectrum. Incorrect spread
percentage may cause system failure.
0825F—11/19/03
8
ICS950818
BYTE
14
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
X
X
X
X
X
X
X
X
Affected Pin
Name
-
Control Function
Type
(Reserved)
(Reserved)
Spread Spectrum Bit13
Spread Spectrum Bit12
Spread Spectrum Bit11
Spread Spectrum Bit10
Spread Spectrum Bit9
Spread Spectrum Bit8
RW
RW
RW
RW
RW
RW
RW
RW
Bit Control
0
1
-
PWD
X
X
X
X
X
X
X
X
Note: Please utilize software utility provided by ICS Application Engineering to configure spread spectrum. Incorrect spread
percentage may cause system failure.
0825F—11/19/03
9
ICS950818
Table 2
PCI_STOP# SMBus Control Table-Byte 0, Bit 3
PCI_STOP#
(Pin 30)
Byte 0 Bit 3
Write Bit
Byte 0, Bit 3 Read Bit
(Internal Status)
0
0
0
1
1
0
1
1
Note: When this Byte 0, Bit 3 is low (0), all PCI clocks
0
0
0
1`
are stopped.
Table 3
CPUCLKT/C (1:0) Outputs SMBus Control Table
CPU_STOP#
Byte 1
CPUCLKT/C (1:0) Outputs
Bit 4, 5
(Pin 45)
0
0
Stop
0
1
Running
1
0
Running
1
1
Running
Note: Individual CPUCLK outputs are controlled by Byte 1, Bit 4, and 5.
Table 4
PCICLK_F (2:0) Outputs SMBus Control Table
Byte 3
PCI_STOP#
PCICLK (2:0) Outputs
Bit 3, 4, 5
(Pin 30)
0
0
Stop
0
1
Running
1
0
Running
1
1
Running
Note: Individual PCICLK outputs are controlled by Byte 3, Bit 3, 4, and 5.
Table 5
3V66 (4:2) SMBus Control Table
CPU_STOP#
(Pin 45)
Byte 5
Bit 5
3V66 (4:2)
0
0
Running
0
1
Stopped
1
0
Running
1
1
Running
Note: Activating Byte 5, Bit 5 will allow CPU_STOP# to control stop of pins 17, 18, and 19
Table 6
3V66 (1) SMBus Control Table
CPU_STOP#
Byte 5
3V66 (1)
(Pin 45)
Bit 4
0
0
Running
0
1
Stopped
1
0
Running
1
1
Running
Note: Activating Byte 5, Bit 4 will allow CPU_STOP# to control stop of pins 31.
0825F—11/19/03
10
ICS950818
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD + 0.5 V
Ambient Operating Temperature . . . . . . . . . . 0°C to +90°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only and functional operation of the device at these or any other conditions above those listed
in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 90°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
Input High Voltage
Input Low Voltage
SYMBOL
VIH
VIL
IIH
Input High Current
IIH
I IL1
Input Low Current
I IL2
CONDITIONS
VIN = VDD; Inputs with no pull-down
resistors
VIN = VDD; Inputs with pull-down
resistors
VIN = 0 V; Inputs with no pull-up
resistors
VIN = 0 V; Inputs with pull-up
resistors
MIN
2
VSS-0.3
TYP
MAX
VDD+0.3
0.8
UNITS
V
V
5.75
mA
200
µA
-5.75
mA
-200
µA
IDD3.3OP
CL = Full load; Select @ 100 MHz
182
280
mA
IDD3.3OP
CL =Full load; Select @ 133 MHz
189
280
mA
IDD3.3PD
IDD3.3PDHIz
Fi
Lpin
CIN
COUT
CINX
IREF=5 mA
14
9
14.32
52
0.5
7
5
6
45
mA
mA
MHz
nH
pF
pF
pF
2.1
ms
12
12
ns
ns
Operating Supply Current
Powerdown Current
Input Frequency
Pin Inductance
Input Capacitance1
1,2
Clk Stabilization
Delay 1
TSTAB
t PZH,tPZL
t PHZ,tPLZ
VDD = 3.3 V
Logic Inputs
Output pin capacitance
X1 & X2 pins
From PowerUp or deassertion of
PowerDown to 1st clock.
Output enable delay (all outputs)
Output disable delay (all outputs)
1
Guaranteed by design, not 100% tested in production.
See timing diagrams for buffered and un-buffered timing requirements.
2
0825F—11/19/03
11
27
1
1
ICS950818
Electrical Characteristics - CPU (0.7V Select) 100MHz
TA = 0 - 90°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
Current Source Output
Impedance
Average Period
Voltage High
Voltage Low
Max Voltage
Min Voltage
Crossing Voltage (abs)
Crossing Voltage (var)
Rise Time
Fall Time
Rise Time Variation
Fall Time Variation
Duty Cycle
Skew
Jitter, Cycle to cycle
SYMBOL
CONDITIONS
MIN
TYP
Zo
VO = V x
3000
-
TPERIOD
VHigh
VLow
Vovs
Vuds
Vcross(abs)
d-Vcross
tr
tf
d-tr
d-tf
dt3
t sk3
Fig. 1
Statistical measurement on single ended signal
using oscilloscope math function.
Measurement on single ended signal using
absolute value.
Fig. 3
Variation of crossing over all edges (Fig. 4)
VOL = 0.175V, VOH = 0.525V (Fig. 3)
VOH = 0.525V VOL = 0.175V (Fig. 3)
10.00
660
-150
10.20
850
150
1150
mV
Measurement from differential wavefrom (Fig 1)
VT = 50%
45
10.02
757.1
9.067
774.7
3
386.1
41.57
552.8
558.7
34.25
45.5
50.58
60.5
550
140
810
810
125
125
55
100
mV
mV
ps
ps
ps
ps
%
ps
t jcyc-cyc 1
VT = 50% (Fig. 1)
65.25
175
ps
1
-450
250
175
175
MAX UNITS
Ω
ns
mV
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - CPU (0.7V Select) 133.33MHz
TA = 0 - 90°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
Current Source Output
Impedance
Average Period
Voltage High
Voltage Low
Max Voltage
Min Voltage
Crossing Voltage (abs)
Crossing Voltage (var)
SYMBOL
CONDITIONS
MIN
TYP
Zo1
VO = Vx
3000
-
TPERIOD
VHigh
VLow
Vovs
Vuds
Vcross(abs)
d-Vcross
Fig. 1
Statistical measurement on single ended signal
using oscilloscope math function.
Measurement on single ended signal using
absolute value.
Fig. 3
Variation of crossing over all edges (Fig. 4)
7.50
660
-150
7.58
757
9
775
3
386
42
7.65
850
150
1150
mV
550
140
mV
mV
Rise Time
tr
VOL = 0.175V, VOH = 0.525V (Fig. 3)
175
553
810
ps
Fall Time
tf
VOH = 0.525V VOL = 0.175V (Fig. 3)
175
559
810
ps
Rise Time Variation
Fall Time Variation
d-tr
d-tf
34
46
125
125
ps
ps
Duty Cycle
dt3
51
55
%
Skew
tsk3
VT = 50%
61
100
ps
VT = 50% (Fig. 1)
65
175
ps
Jitter, Cycle to cycle
tjcyc-cyc
Measurement from differential wavefrom (Fig 1)
1
1
Guaranteed by design, not 100% tested in production.
0825F—11/19/03
12
-450
250
45
MAX UNITS
Ω
ns
mV
ICS950818
Electrical Characteristics - 3V66
TA = 0 - 90°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
Output Impedance
Average Period
Output High Voltage
Output Low Voltage
SYMBOL
1
RDSP1
TPERIOD
Output High Current
IOH
Output Low Current
IOL
Rise Time
Fall Time
Duty Cycle
1
tr1
1
tf1
1
dt1
1
tsk1
Skew
1
VOH
1
VOL
1
1
CONDITIONS
VO = VDD*(0.5)
Fig. 8
IOH = -1 mA
IOL = 1 mA
V OH = 1.0 V
V OH = 3.135 V
VOL = 1.95 V
VOL = 0.4 V
VOL = 0.4 V, VOH = 2.4 V (Fig. 7)
VOH = 2.4 V, VOL = 0.4 V (Fig. 7)
VT = 1.5 V (Fig. 8)
MIN
12
15.00
2.05
-33
26
0.5
0.5
45
VT = 1.5 V
1
tjcyc-cyc
1
VT = 1.5 V (Fig. 8)
Jitter
Guaranteed by design, not 100% tested in production.
TYP
64.50
15.01
3.24
0.06
-90
-14
35
103
1.74
1.45
52.05
MAX
65
15.30
38
2.3
2.3
55
ns
ns
%
13.50
250
ps
158.75
290
ps
TYP
48.008
52.50
3.24
0.06
-53
-7
21
60
0.86
0.86
1.37
1.37
51.10
52.80
182.63
0.13
153.25
MAX
UNITS
MHz
Ω
V
V
0.65
-33
UNITS
Ω
ns
V
V
mA
Electrical Characteristics - VCH, 48MHz DOT, 48MHz, USB
TA = 0 - 90°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
FO1
Output Frequency
Fig. 8
VO = VDD*(0.5)
Output Impedance
RDSP11
1
IOH = -1 mA
Output High Voltage
VOH
1
IOL = 1 mA
Output Low Voltage
VOL
V OH = 1.0 V
1
Output High Current
IOH
V OH = 3.135 V
VOL = 0.4 V
Output Low Current
IOL1
VOL 1.95 V
VOL = 0.4 V, VOH = 2.4 V (Fig. 7)
48DOT Rise Time
tr11
1
VOH = 2.4 V, VOL = 0.4 V (Fig. 7)
48DOT Fall Time
tf1
1
VOL = 0.4 V, VOH = 2.4 V (Fig. 7)
VCH 48 USB Rise Time
tr1
1
VOH = 2.4 V, VOL = 0.4 V (Fig. 7)
VCH 48 USB Fall Time
tf1
1
VT = 1.5 V (Fig. 8)
48 DOT Duty Cycle
dt1
VCH 48 USB Duty Cycle
48 DOT Jitter
USB to DOT Skew
VCH Jitter
1
dt11
1
tjcyc-cyc
1
tsk1
tjcyc-cyc1
VT = 1.5 V (Fig. 8)
VT = 1.5 V (Fig. 8)
VT = 1.5 V (0 OR 180 degrees)
VT = 1.5 V (Fig. 8)
Guaranteed by design, not 100% tested in production.
0825F—11/19/03
13
MIN
20
2.05
-20
25
0.5
0.5
1
1
45
45
70
0.5
-29
27
1.15
1.15
2.3
2.3
55
55
410
1
410
mA
mA
ns
ns
ns
ns
%
%
ps
ns
ps
ICS950818
Electrical Characteristics - PCICLK_F, PCICLK 1X
TA = 0 - 90°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
Output Impedance
Average Period
Output High Voltage
Output Low Voltage
SYMBOL
1
RDSP1
TPERIOD
Output High Current
IOH
Output Low Current
IOL
1
VOH
1
VOL
1
1
CONDITIONS
VO = VDD*(0.5)
Fig. 8
IOH = -1 mA
IOL = 1 mA
V OH = 1.0 V
V OH = 3.135 V
VOL = 1.95 V
VOL = 0.4 V
VOL = 0.4 V, VOH = 2.4 V (Fig. 7)
VOH = 2.4 V, VOL = 0.4 V (Fig. 7)
VT = 1.5 V (Fig. 8)
VT = 1.5 V
VT = 1.5 V (Fig. 8)
1
Rise Time
tr1
1
Fall Time
tf1
1
Duty Cycle
dt1
1
Skew
tsk1
1
Jitter,cycle to cyc
tjcyc-cyc
1
Guaranteed by design, not 100% tested in production.
MIN
12
30.00
2.05
-33
26
0.5
0.5
45
TYP
52.50
30.03
3.24
0.06
-90
-14
35
103
1.79
1.82
51.57
136.00
151.5
MAX
65
TYP
52.5
30.03
3.24
0.06
-100
-17
44
100
1.75
1.80
51.95
136
151.5
MAX
0.65
-33
UNITS
Ω
ns
V
V
mA
38
2.3
2.3
55
500
290
ns
ns
%
ps
ps
Electrical Characteristics - PCICLK (3:2) 2X
TA = 0 - 90°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
Output Impedance
Average Period
Output High Voltage
Output Low Voltage
SYMBOL
1
RDSP1
TPERIOD
Output High Current
IOH1
Output Low Current
1
VOH1
VOL1
IOL
CONDITIONS
VO = VDD*(0.5)
Fig. 8
IOH = -1 mA
IOL = 1 mA
V OH = 1.0 V
V OH = 3.135 V
VOL = 1.95 V
VOL = 0.4 V
VOL = 0.4 V, VOH = 2.4 V (Fig. 7)
VOH = 2.4 V, VOL = 0.4 V (Fig. 7)
VT = 1.5 V (Fig. 8)
VT = 1.5 V
VT = 1.5 V (Fig. 8)
Rise Time
tr11
Fall Time
tf11
1
Duty Cycle
dt1
Skew
tsk11
Jitter,cycle to cyc
tjcyc-cyc1
1
Guaranteed by design, not 100% tested in production.
0825F—11/19/03
14
MIN
0.4
-28
26
0.5
0.5
45
2.7
UNITS
Ω
ns
V
V
-60
60
2.3
2.3
55
500
290
mA
ns
ns
%
ps
ps
ICS950818
Electrical Characteristics - REF (1X select)
TA = 0 - 90°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
Output Frequency
Output Impedance
Output High Voltage
Output Low Voltage
SYMBOL
FO1
RDSP1
1
VOH
1
VOL
Output High Current
IOH
Output Low Current
IOL
Rise Time
Fall Time
Duty Cycle
1
1
1
1
tr1
1
tf1
1
dt1
CONDITIONS
Fig. 8
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
V OH = 1.0 V
V OH = 3.135 V
VOL = 0.4 V
VOL 1.95 V
VOL = 0.4 V, VOH = 2.4 V (Fig. 7)
VOH = 2.4 V, VOL = 0.4 V (Fig. 7)
VT = 1.5 V
MIN
26
1
1
TYP
14.318
52.50
3.24
0.06
-70
-12
30
60
1.98
45
54.50
55
%
242
1200
ps
TYP
14.318
52.5
3.24
0.06
-100
-17
44
100
1.98
54.70
MAX
UNITS
MHz
Ω
V
V
2.3
2.3
55
ns
ns
%
242
1200
ps
20
2.05
-25
1
tjcyc-cyc
VT = 1.5 V (Fig. 8)
Jitter
1
Guaranteed by design, not 100% tested in production.
MAX
70
0.45
-29
38
2.3
2.3
UNITS
MHz
Ω
V
V
mA
ns
ns
Electrical Characteristics - REF (2X select)
TA = 0 - 90°C; VDD=3.3V +/-5%; CL = 20-40 pF (unless otherwise specified)
1
PARAMETER
Output Frequency
Output Impedance
Output High Voltage
Output Low Voltage
SYMBOL
FO1
Output High Current
IOH1
Output Low Current
IOL
1
Rise Time
Fall Time
Duty Cycle
tr1
1
tf1
dt11
RDSP11
VOH1
1
VOL
1
CONDITIONS
Fig. 8
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
V OH = 1.0 V
V OH = 3.135 V
VOL = 0.4 V
VOL 1.95 V
VOL = 0.4 V, VOH = 2.4 V (Fig. 7)
VOH = 2.4 V, VOL = 0.4 V (Fig. 7)
VT = 1.5 V
1
VT = 1.5 V (Fig. 8)
Jitter
tjcyc-cyc
Guaranteed by design, not 100% tested in production.
0825F—11/19/03
15
MIN
2.7
-28
26
1
1
45
0.4
-60
60
mA
ICS950818
PCI_STOP# - Assertion (transition from logic "1" to logic "0")
The impact of asserting the PCI_STOP# signal will be the following. All PCI[10:0] and stoppable PCI_F clocks will latch
low in their next high to low transition. The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized by the
next rising edge.
Assertion of PCI_STOP# Waveforms
PCI_STOP#
PCI_F 33MHz
PCI 33MHz
tsu
CPU_STOP# - Assertion (transition from logic "1" to logic "0")
The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the SMBus configuration to be stoppable
via assertion of CPU_STOP# are to be stopped after their next transition. When the SMBus Bit 6 of Byte 1 is
programmed to '0' the final state of the stopped CPU signals is CPU = High and CPU# = Low. There is to be no change
to the output drive current values. The CPU will be driven high with a current value equal to (Mult 0 'select') x (Iref), the
CPU# signal will not be driven . When the SMBus Bit 6 of Byte 1 is programmed to '1' then final state of the stopped
CPU signals is Low, both CPU and CPU# outputs will not be driven.
Assertion of CPU_STOP# Waveforms
CPU_STOP#
CPUCLKT
CPUCLKC
CPU_STOP# Functionality
CPU_STOP#
CPUT
CPUC
1
Normal
Normal
0
iref * Mult
Float
Group to Group Skews at Common Transition Edges: Unbuffered Mode
GROUP
3V66 to PCI1,2
SYMBOL
S3V66-PCI
CONDITIONS
3V66 (4:1) leads 33MHz PCI
1
Guaranteed by design, not 100% tested in production.
500ps Tolerance
2
0825F—11/19/03
16
MIN
1.5
TYP
2.765
MAX
3.5
UNITS
ns
ICS950818
CPU_STOP# - De-assertion (transition from logic "0" to logic "1")
All CPU outputs that were stopped are to resume normal operation in a glitch free manner. The maximum latency from
the de-assertion to active outputs is to be defined to be between 2 - 6 CPU clock periods (2 clocks are shown). If the
SMBus Bit 6 of Byte 1 is programmed to "1" then the stopped CPU outputs will be driven High within 10 nS of CPU_Stop#
de-assertion.
De-assertion of CPU_STOP# Waveforms
CPU_STOP#
CPUCLKT(2:0)
Tdrive_CPU_STOP# <10ns @ 200mV
*CPUCLKT(2:0)TS
CPUCLKC(2:0)
*Signal TS is CPUCLKT in Tri-State mode
PD# - Assertion (transition from logic "1" to logic "0")
When PWRDWN# is sampled low by two consecutive rising edges of CPU clock, then all clock outputs except CPU
clocks must be held low on their next high to low transitions. When the SMBUS Bit 6 of Byte 0 is programmed to '0'
CPU clocks must be held with the CPU clock pin driven high with a value of 2 x Iref, and CPU# undriven. If Bit 6 of
Byte 0 is '1' then both CPU and CPU# are undriven. Note the example below shows CPU = 133 MHz and Bit 6 of Byte
0 = '0', this diagram and description is applicable for all valid CPU frequencies 66, 100, 133, 200 MHz.
Due to the state if the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than
one clock cycle to complete.
Power Down Assertion of Waveforms
25ns
0ns
50ns
PD#
CPUCLKT 100MHz
CPUCLKC 100MHz
3V66MHz
PCICLK 33MHz
USB 48MHz
REF 14.318MHz
PD# Functionality
PD#
CPUCLKT
CPUCLKC
3V66
PCICLK_F
PCICLK
USB/DOT
48MHz
1
Normal
Normal
66MHz
33MHz
48MHz
0
iref * Mult
Float
Low
Low
Low
0825F—11/19/03
17
ICS950818
Power Down De-Assertion Mode
The power-up latency needs to be less than 1.8mS. this is the time from the de-asseration of the powerdown of the
ramping of the power supply until the time that stable clocks are output from the clock chip. If the SMBus Bit 6 of Byte
0 is programmed to "1" then the stopped CPU outputs will be driven high within 3 nS of PD# de-asseration.
Test Configuration Diagram
Rs=33 Ohms
5%
TLA
CLK408
CPUCLKT test
point
Rs=33 Ohms
5%
TLB
Rp=49.9 Ohms
1%
CPUCLKC test
point
Rp=49.9 Ohms
1%
Rset=475 Ohms
1%
2pF
5%
2pF
5%
MULTSEL Pin must be High
CPU 0.7V Configuration test load board termination
0825F—11/19/03
18
ICS950818
Shared Pin Operation Input/Output Pins
Figure 1 shows a means of implementing this function
when a switch or 2 pin header is used. With no jumper is
installed the pin will be pulled high. With the jumper in
place the pin will be pulled low. If programmability is not
necessary, than only a single resistor is necessary. The
programming resistors should be located close to the
series termination resistor to minimize the current loop
area. It is more important to locate the series termination
resistor close to the driver than the programming resistor.
The I/O pins designated by (input/output) serve as dual
signal functions to the device. During initial power-up,
they act as input pins. The logic level (voltage) that is
present on these pins at this time is read and stored into
a 5-bit internal data latch. At the end of Power-On reset,
(see AC characteristics for timing values), the device
changes the mode of operations for these pins to an
output function. In this mode the pins produce the
specified buffered clocks to external loads.
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD
(logic 1) power supply or the GND (logic 0) voltage
potential. A 10 Kilohm (10K) resistor is used to provide
both the solid CMOS programming voltage needed during
the power-up programming period and to provide an
insignificant load on the output clock during the subsequent
operating period.
Via to
VDD
Programming
Header
2K Via to Gnd
Device
Pad
8.2K Clock trace to load
Series Term. Res.
Fig. 1
0825F—11/19/03
19
ICS950818
6.10 mm. Body, 0.50 mm. Pitch TSSOP
(240 mil)
(20 mil)
In Millimeters
In Inches
SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS
MIN
MAX
MIN
MAX
A
-1.20
-.047
A1
0.05
0.15
.002
.006
A2
0.80
1.05
.032
.041
b
0.17
0.27
.007
.011
c
0.09
0.20
.0035
.008
SEE VARIATIONS
SEE VARIATIONS
D
8.10 BASIC
0.319 BASIC
E
E1
6.00
6.20
.236
.244
0.50 BASIC
0.020 BASIC
e
L
0.45
0.75
.018
.030
SEE VARIATIONS
SEE VARIATIONS
N
a
0°
8°
0°
8°
aaa
-0.10
-.004
c
N
L
E1
INDEX
AREA
E
1 2
D
A
A2
VARIATIONS
A1
N
-Ce
48
SEATING
PLANE
b
D mm.
MIN
12.40
D (inch)
MAX
12.60
Reference Doc.: JEDEC Publication 95, MO-153
10-0039
aaa C
6.10 mm. Body, 0.50 mm. pitch TSSOP
(20 mil)
(240 mil)
Ordering Information
ICS950818yGT
Example:
ICS95 XXXX y G - T
Designation for tape and reel packaging
Package Type
G=TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS, AV = Standard Device
0825F—11/19/03
20
MIN
.488
MAX
.496
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