IDT IDT2305-1DCI 3.3v zero delay clock buffer Datasheet

IDT2305
3.3V ZERO DELAY CLOCK BUFFER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT2305
3.3V ZERO DELAY
CLOCK BUFFER
FEATURES:
•
•
•
•
•
•
•
•
•
•
•
•
DESCRIPTION:
Phase-Lock Loop Clock Distribution
10MHz to 133MHz operating frequency
Distributes one clock input to one bank of five outputs
Zero Input-Output Delay
Output Skew < 250ps
Low jitter <200 ps cycle-to-cycle
IDT2305-1 for Standard Drive
IDT2305-1H for High Drive
No external RC network required
Operates at 3.3V VDD
Power down mode
Available in SOIC package
The IDT2305 is a high-speed phase-lock loop (PLL) clock buffer,
designed to address high-speed clock distribution applications. The zero
delay is achieved by aligning the phase between the incoming clock and
the output clock, operable within the range of 10 to 133MHz.
The IDT2305 is an 8-pin version of the IDT2309. IDT2305 accepts one
reference input, and drives out five low skew clocks. The -1H version of this
device operates, up to 133MHz frequency and has a higher drive than the
-1 device. All parts have on-chip PLLs which lock to an input clock on the
REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT
pad. In the absence of an input clock, the IDT2305 enters power down. In
this mode, the device will draw less than 25μA, the outputs are tri-stated,
and the PLL is not running, resulting in a significant reduction of power.
The IDT2305 is characterized for both Industrial and Commercial
operation.
FUNCTIONAL BLOCK DIAGRAM
8
CLKOUT
3
PLL
REF
1
CLK1
Control
Logic
2
5
CLK2
CLK3
7
CLK4
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
DECEMBER 2007
1
c
2007
Integrated Device Technology, Inc.
DSC 5174/8
IDT2305
3.3V ZERO DELAY CLOCK BUFFER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
PIN CONFIGURATION
Symbol
REF
1
8
CLKOUT
CLK2
2
7
CLK4
CLK1
3
6
VDD
GND
4
5
CLK3
Rating
Max.
Unit
VDD
Supply Voltage Range
–0.5 to +4.6
V
VI (2)
Input Voltage Range (REF)
–0.5 to +5.5
V
VI
Input Voltage Range
–0.5 to
V
IIK (VI < 0)
Input Clamp Current
IO (VO = 0 to VDD)
VDD or GND
TA = 55°C
(except REF)
VDD+0.5
–50
mA
Continuous Output Current
±50
mA
Continuous Current
±100
mA
Maximum Power Dissipation
0.7
W
TSTG
Storage Temperature Range
–65 to +150
°C
0 to +70
°C
-40 to +85
°C
(3)
(in still air)
SOIC
TOP VIEW
Operating
Commercial Temperature
Temperature
Range
Operating
Industrial Temperature
Temperature
Range
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and output
clamp-current ratings are observed.
3. The maximum package power dissipation is calculated using a junction temperature
of 150°C and a board trace length of 750 mils.
APPLICATIONS:
•
•
•
•
•
SDRAM
Telecom
Datacom
PC Motherboards/Workstations
Critical Path Delay Designs
PIN DESCRIPTION
Pin Name
REF
(1)
Pin Number
Type
Functional Description
1
IN
Input reference clock, 5 Volt tolerant input
CLK2(2)
2
Out
Output clock
(2)
3
Out
Output clock
4
Ground
CLK1
GND
CLK3
(2)
VDD
CLK4
(2)
CLKOUT
(2)
Ground
5
Out
Output clock
6
PWR
3.3V Supply
7
Out
Output clock
8
Out
Output clock, internal feedback on this pin
NOTES:
1. Weak pull down.
2. Weak pull down on all outputs.
2
IDT2305
3.3V ZERO DELAY CLOCK BUFFER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
OPERATING CONDITIONS - COMMERCIAL
Symbol
Parameter
Min.
Max.
Unit
3
3.6
V
Operating Temperature (Ambient Temperature)
0
70
°C
Load Capacitance < 100MHz
—
30
pF
Load Capacitance 100MHz - 133MHz
—
10
Input Capacitance
—
7
VDD
Supply Voltage
TA
CL
CIN
pF
DC ELECTRICAL CHARACTERISTICS - COMMERCIAL
Symbol
Parameter
Conditions
Min.
Max.
Unit
VIL
Input LOW Voltage Level
—
0.8
V
VIH
Input HIGH Voltage Level
2
—
V
IIL
Input LOW Current
VIN = 0V
—
50
µA
IIH
Input HIGH Current
VIN = VDD
—
100
µA
VOL
Output LOW Voltage
Standard Drive
IOL = 8mA
—
0.4
V
High Drive
IOL = 12mA (-1H)
VOH
Output HIGH Voltage
Standard Drive
IOH = -8mA
2.4
—
V
High Drive
IOH = -12mA (-1H)
IDD_PD
Power Down Current
REF = 0MHz
—
12
µA
Supply Current
Unloaded Outputs at 66.66MHz
—
32
mA
IDD
SWITCHING CHARACTERISTICS (2305-1) - COMMERCIAL
Symbol
t1
Parameter
Output Frequency
(1,2)
Conditions
10pF Load
Min.
Typ.
Max.
Unit
10
—
133
MHz
30pF Load
10
—
100
Duty Cycle = t2 ÷ t1
Measured at 1.4V, FOUT = 66.66MHz
40
50
60
%
t3
Rise Time
Measured between 0.8V and 2V
—
—
2.5
ns
t4
Fall Time
Measured between 0.8V and 2V
—
—
2.5
ns
t5
Output to Output Skew
All outputs equally loaded
—
—
250
ps
t6
Delay, REF Rising Edge to CLKOUT Rising Edge
Measured at VDD/2
—
0
±350
ps
t7
Device-to-Device Skew
Measured at VDD/2 on the CLKOUT pins of devices
—
0
700
ps
tJ
Cycle-to-Cycle Jitter, pk - pk
Measured at 66.66MHz, loaded outputs
—
—
200
ps
PLL Lock Time
Stable power supply, valid clock presented on REF pin
—
—
1
ms
tLOCK
NOTES:
1. REF Input has a threshold voltage of VDD/2.
2. All parameters specified with loaded outputs.
3
IDT2305
3.3V ZERO DELAY CLOCK BUFFER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
(1,2)
SWITCHING CHARACTERISTICS (2305-1H) - COMMERCIAL
Symbol
Min.
Typ.
Max.
Unit
Output Frequency
10pF Load
30pF Load
10
10
—
—
133
100
MHz
Duty Cycle = t2 ÷ t1
Measured at 1.4V, FOUT = 66.66MHz
40
50
60
%
Duty Cycle = t2 ÷ t1
Measured at 1.4V, FOUT <50MHz
45
50
55
%
t3
Rise Time
Measured between 0.8V and 2V
—
—
1.5
ns
t4
Fall Time
Measured between 0.8V and 2V
—
—
1.5
ns
t5
Output to Output Skew
All outputs equally loaded
—
—
250
ps
t6
Delay, REF Rising Edge to CLKOUT Rising Edge
Measured at VDD/2
—
0
±350
ps
t7
Device-to-Device Skew
Measured at VDD/2 on the CLKOUT pins of devices
—
0
700
ps
t8
Output Slew Rate
Measured between 0.8V and 2V using Test Circuit #2
1
—
—
V/ns
tJ
Cycle-to-Cycle Jitter, pk - pk
Measured at 66.66MHz, loaded outputs
—
—
200
ps
PLL Lock Time
Stable power supply, valid clock presented on REF pin
—
—
1
ms
t1
tLOCK
Parameter
Conditions
NOTES:
1. REF Input has a threshold voltage of VDD/2.
2. All parameters specified with loaded outputs.
OPERATING CONDITIONS - INDUSTRIAL
Symbol
Parameter
Min.
Max.
Unit
VDD
Supply Voltage
3
3.6
V
TA
Operating Temperature (Ambient Temperature)
-40
+85
°C
CL
Load Capacitance < 100MHz
—
30
pF
Load Capacitance 100MHz - 133MHz
—
10
Input Capacitance
—
7
CIN
pF
DC ELECTRICAL CHARACTERISTICS - INDUSTRIAL
Symbol
Parameter
Conditions
Min.
Max.
Unit
—
0.8
V
VIL
Input LOW Voltage Level
VIH
Input HIGH Voltage Level
2
—
V
IIL
Input LOW Current
VIN = 0V
—
50
µA
IIH
Input HIGH Current
VIN = VDD
—
100
µA
VOL
Output LOW Voltage
—
0.4
V
2.4
—
V
VOH
IDD_PD
IDD
Output HIGH Voltage
Standard Drive
IOL = 8mA
High Drive
IOL = 12mA (-1H)
Standard Drive
IOH = -8mA
High Drive
IOH = -12mA (-1H)
Power Down Current
REF = 0MHz
—
25
µA
Supply Current
Unloaded Outputs at 66.66MHz
—
35
mA
4
IDT2305
3.3V ZERO DELAY CLOCK BUFFER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS (2305-1) - INDUSTRIAL
Symbol
t1
Parameter
Output Frequency
(1,2)
Conditions
Min.
Typ.
Max.
Unit
10pF Load
10
—
133
MHz
30pF Load
10
—
100
Duty Cycle = t2 ÷ t1
Measured at 1.4V, FOUT = 66.66MHz
40
50
60
%
t3
Rise Time
Measured between 0.8V and 2V
—
—
2.5
ns
t4
Fall Time
Measured between 0.8V and 2V
—
—
2.5
ns
t5
Output to Output Skew
All outputs equally loaded
—
—
250
ps
t6
Delay, REF Rising Edge to CLKOUT Rising Edge
Measured at VDD/2
—
0
±350
ps
t7
Device-to-Device Skew
Measured at VDD/2 on the CLKOUT pins of devices
—
0
700
ps
tJ
Cycle-to-Cycle Jitter, pk - pk
Measured at 66.66MHz, loaded outputs
—
—
200
ps
PLL Lock Time
Stable power supply, valid clock presented on REF pin
—
—
1
ms
tLOCK
NOTES:
1. REF Input has a threshold voltage of VDD/2.
2. All parameters specified with loaded outputs.
SWITCHING CHARACTERISTICS (2305-1H) - INDUSTRIAL
Symbol
t1
Parameter
(1,2)
Min.
Typ.
Max.
Unit
Output Frequency
10pF Load
30pF Load
Conditions
10
10
—
—
133
100
MHz
Duty Cycle = t2 ÷ t1
Measured at 1.4V, FOUT = 66.66MHz
40
50
60
%
Duty Cycle = t2 ÷ t1
Measured at 1.4V, FOUT <50MHz
45
50
55
%
t3
Rise Time
Measured between 0.8V and 2V
—
—
1.5
ns
t4
Fall Time
Measured between 0.8V and 2V
—
—
1.5
ns
t5
Output to Output Skew
All outputs equally loaded
—
—
250
ps
t6
Delay, REF Rising Edge to CLKOUT Rising Edge
Measured at VDD/2
—
0
±350
ps
t7
Device-to-Device Skew
Measured at VDD/2 on the CLKOUT pins of devices
—
0
700
ps
t8
Output Slew Rate
Measured between 0.8V and 2V using Test Circuit #2
1
—
—
V/ns
tJ
Cycle-to-Cycle Jitter, pk - pk
Measured at 66.66MHz, loaded outputs
—
—
200
ps
PLL Lock Time
Stable power supply, valid clock presented on REF pin
—
—
1
ms
tLOCK
NOTES:
1. REF Input has a threshold voltage of VDD/2.
2. All parameters specified with loaded outputs.
5
IDT2305
3.3V ZERO DELAY CLOCK BUFFER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ZERO DELAY AND SKEW CONTROL
All outputs should be uniformly loaded in order to achieve Zero I/O Delay. Since the CLKOUT pin is the internal feedback for the PLL, its relative
loading can affect and adjust the input/output delay. The Output Load Difference diagram illustrates the PLL's relative loading with respect to the other
outputs that can adjust the Input-Output (I/O) Delay.
For designs utilizing zero I/O Delay, all outputs including CLKOUT must be equally loaded. Even if the output is not used, it must have a capacitive
load equal to that on the other outputs in order to obtain true zero I/O Delay. If I/O Delay adjustments are needed, use the Output Load Difference diagram
to calculate loading differences between the CLKOUT pin and other outputs. For zero output-to-output skew, all outputs must be loaded equally.
REF TO CLKA/CLKB RELAY vs. OUTPUT LOAD DIFFERENCE BETWEEN CLKOUT PIN AND CLKA/CLKB PINS
1500
REF to CLKA/CLKB Delay (ps)
1000
500
0
-30
-25
-20
-15
-10
-5
0
5
10
15
-500
-1000
-1500
OUTPUT LOAD DIFFERENCE BETWEEN CLKOUT PIN AND CLKA/CLKB PINS (pF)
6
20
25
30
IDT2305
3.3V ZERO DELAY CLOCK BUFFER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
SWITCHING WAVEFORMS
1.4V
t1
Output
t2
1.4V
1.4V
1.4V
1.4V
Output
t5
Output to Output Skew
Duty Cycle Timing
Output
0.8V
2V
2V
3.3V
0.8V
V DD/2
REF
0V
t4
t3
V DD/2
Output
t6
Input to Output Propagation Delay
All Outputs Rise/Fall Time
CLK O UT
Device 1
CLK O U T
Device 2
V DD /2
V DD /2
t7
Device to Device Skew
TEST CIRCUITS
V DD
0.1 μ F
CLK O U T
OUTPUTS
V DD
0.1 μ F
1K Ω
C LK O UT
OUTPUTS
C LO A D
1K Ω
10pF
V DD
V DD
0.1 μ F
0.1 μ F
GND
GND
GND
GND
Test Circuit 2 (t8, Output Slew Rate On -1H Devices)
Test Circuit 1 (all Parameters Except t8)
7
IDT2305
3.3V ZERO DELAY CLOCK BUFFER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
TYPICAL DUTY CYCLE(1) AND IDD TRENDS(2) FOR IDT2305-1
Duty Cycle vs V DD
(for 30pf loads over frequency - 3.3V, 25C)
Du ty Cycle vs V D D
(for 10pF load s over frequency - 3.3V, 25C)
60
58
58
56
56
54
54
Duty Cycle (% )
Duty Cycle (% )
60
52
33M H z
66M H z
100M Hz
50
48
52
48
46
46
44
44
42
42
40
33M Hz
66M Hz
100M Hz
133M Hz
50
40
3
3.1
3.2
3.3
3.4
3.5
3
3.6
3.1
3.2
V DD (V)
3.5
3.6
Du ty C ycle vs Fre qu ency
(for 10pF loads over tem perature - 3.3V)
60
60
58
58
56
56
Duty Cycle (% )
Duty Cycle (% )
3.4
V DD (V)
Duty Cycle vs Frequency
(for 30pf loads over temperature - 3.3V)
54
52
-40C
0C
25C
70C
85C
50
48
54
52
-40C
0C
25C
70C
85C
50
48
46
46
44
44
42
42
40
40
20
40
60
80
100
120
140
20
40
60
Frequency (MHz)
80
100
120
140
Frequency (M Hz)
IDD vs Number of Loaded Outputs
(for 30pf loads over frequency - 3.3V, 25C)
I D D vs Num ber of Loade d O utputs
(for 10pF loads over frequency - 3.3V, 25C)
140
140
120
120
100
100
80
I DD (mA)
I DD (m A)
3.3
33M H z
66M H z
100M Hz
60
80
60
40
40
20
20
0
33M H z
66M Hz
100M Hz
0
0
2
4
6
0
8
Number of Loaded Outputs
2
4
6
Number of Loaded O utputs
NOTES:
1. Duty Cycle is taken from typical chip measured at 1.4V.
2. IDD data is calculated from IDD = ICORE + nCVf, where ICORE is the unloaded current. (n = Number of outputs; C = Capacitance load per output (F);
V = Supply Voltage (V); f = Frequency (Hz))
8
8
IDT2305
3.3V ZERO DELAY CLOCK BUFFER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
TYPICAL DUTY CYCLE(1) AND IDD TRENDS(2) FOR IDT2305-1H
Duty C ycle vs V DD
(for 10pF loads over freque ncy - 3.3V, 25C)
60
60
58
58
56
56
54
54
Duty Cycle (% )
Duty Cycle (% )
Duty Cycle vs V DD
(for 30pf loads over frequency - 3.3V, 25C)
52
33M Hz
66M H z
100M Hz
50
48
52
33M H z
50
46
46
44
44
42
42
40
66M H z
100M H z
133M H z
48
40
3
3.1
3.2
3.3
3.4
3.5
3
3.6
3.1
3.2
V DD (V)
3.5
3.6
Duty C ycle vs Fre quency
(for 10pF loads ove r tem perature - 3.3V)
60
60
58
58
56
56
Duty Cycle (% )
Duty Cycle (% )
3.4
V DD (V)
Duty Cycle vs Frequency
(for 30pf loads over temperature - 3.3V)
54
52
-40C
0C
25C
70C
85C
50
48
54
52
-40C
50
0C
25C
70C
85C
48
46
46
44
44
42
42
40
40
20
40
60
80
100
120
140
20
40
60
Frequency (MHz)
80
100
120
140
Frequency (M Hz)
IDD vs Number of Loaded Outputs
(for 30pf loads over frequency - 3.3V, 25C)
I D D vs Nu m ber of Loaded O utp uts
(for 10pF load s over frequency - 3.3V, 25C)
160
160
140
140
120
120
100
100
80
I DD (m A)
I DD (m A)
3.3
33M Hz
66M H z
100M Hz
60
80
33M H z
66M H z
100M H z
60
40
40
20
20
0
0
0
2
4
6
0
8
2
4
6
8
Num ber of Loaded Outputs
Num ber of Loaded Outputs
NOTES:
1. Duty Cycle is taken from typical chip measured at 1.4V.
2. IDD data is calculated from IDD = ICORE + nCVf, where ICORE is the unloaded current. (n = Number of outputs; C = Capacitance load per output (F); V = Supply Voltage (V);
f = Frequency (Hz))
9
IDT2305
3.3V ZERO DELAY CLOCK BUFFER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PACKAGE OUTLINE AND PACKAGE DIMENSIONS - SOIC
N
C
L
E
H
INDEX
AREA
1
h x 45°
2
α
D
A
A1
e
SEATING
PLANE
B
.10 (.004)
150 mil (Narrow Body) SOIC
SYMBOL
VARIATIONS
In Inches (1)
In Millimeters
COMMON DIMENSIONS COMMON DIMENSIONS
D (inch) (1)
D (mm)
N
MIN
MAX
MIN
MAX
4.80
5.00
.1890
.1968
MIN
MAX
MIN
MAX
8
A
1.35
1.75
.0532
.0688
14
8.55
8.75
.3367
.3444
A1
0.10
0.25
.0040
.0098
16
9.80
10.00
.3859
.3937
B
0.33
0.51
.0130
.0200
C
0.19
0.25
.0075
.0098
D
SEE VARIATIONS
SEE VARIATIONS
E
3.80
.1497
e
4.00
1.27 BASIC
.1574
0.050 BASIC
H
5.80
6.20
.2284
.2440
h
0.25
0.50
.010
.020
L
0.40
1.27
.016
.050
N
SEE VARIATIONS
α
0°
NOTE:
1. For reference only. Controlling dimensions are in mm.
SEE VARIATIONS
8°
0°
8°
NOTE:
1. For reference only. Controlling dimensions are in mm.
10
IDT2305
3.3V ZERO DELAY CLOCK BUFFER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
XXXXX
Device Type
XX
Package
X
Process
Ordering Code
Blank
I
Commercial (0oC to +70oC)
Industrial (-40oC to +85oC)
DC
DCG
Small Outline
SOIC - Green
2305-1
2305-1H
Zero Delay Clock Buffer
High Drive Output
Package Type
Operating Range
IDT2305-1DC
8-Pin SOIC
Commercial
IDT2305-1DCG
8-Pin SOIC
Commercial
IDT2305-1DCI
8-Pin SOIC
Industrial
IDT2305-1DCGI
8-Pin SOIC
Industrial
IDT2305-1HDC
8-Pin SOIC
Commercial
IDT2305-1HDCI
8-Pin SOIC
Industrial
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
11
for Tech Support:
[email protected]
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